sb_mac.h

一个很好的嵌入式linux平台下的bootloader

#define G_MIIDATA_SB(x)         _DD_GETVALUE(x,S_MIIDATA_SB,M_MIIDATA_SB)
#define K_MII_START             0x1

/* EIMR: Ethernet Interrupt Mask Register (0x418, R/W) */
/* EISR: Ethernet Interrupt Status Register (0x41C, R/W) */

#define M_EINT_MI               _DD_MAKEMASK1(0)        /* MIIInt */
#define M_EINT_MB               _DD_MAKEMASK1(1)        /* MIBInt */
#define M_EINT_FM               _DD_MAKEMASK1(2)        /* FlowInt */

/* CAM: CAM Data Low Register (0x420, R/W) */

#define S_CAM_CD_L              0                       /* CAMDataL */
#define M_CAM_CD_L              _DD_MAKEMASK(32,S_CAM_CD_L)
#define V_CAM_CD_L(x)           _DD_MAKEVALUE(x,S_CAM_CD_L)
#define G_CAM_CD_L(x)           _DD_GETVALUE(x,S_CAM_CD_L,M_CAM_CD_L)

/* CAM: CAM Data High Register (0x424, R/W) */

#define S_CAM_CD_H              0                       /* CAMDataH */
#define M_CAM_CD_H              _DD_MAKEMASK(16,S_CAM_CD_H)
#define V_CAM_CD_H(x)           _DD_MAKEVALUE(x,S_CAM_CD_H)
#define G_CAM_CD_H(x)           _DD_GETVALUE(x,S_CAM_CD_H,M_CAM_CD_H)

#define M_CAM_VB                _DD_MAKEMASK1(16)       /* ValidBit */

/* CAMCTL: CAM Control Register (0x428, R/W) */

#define M_CAMCTL_CE             _DD_MAKEMASK1(0)        /* CAMEnable */
#define M_CAMCTL_MS             _DD_MAKEMASK1(1)        /* MaskSelect */
#define M_CAMCTL_CR             _DD_MAKEMASK1(2)        /* CAMRead */
#define M_CAMCTL_CW             _DD_MAKEMASK1(3)        /* CAMWrite */

#define S_CAMCTL_IX             16                      /* Index */
#define M_CAMCTL_IX             _DD_MAKEMASK(6,S_CAMCTL_IX)
#define V_CAMCTL_IX(x)          _DD_MAKEVALUE(x,S_CAMCTL_IX)
#define G_CAMCTL_IX(x)          _DD_GETVALUE(x,S_CAMCTL_IX,M_CAMCTL_IX)

#define M_CAMCTL_CB             _DD_MAKEMASK1(31)       /* CAMBusy */

/* ECTL: Ethernet Control Register (0x42C, R/W) */

#define M_ECTL_EE               _DD_MAKEMASK1(0)        /* EMACEnable */
#define M_ECTL_ED               _DD_MAKEMASK1(1)        /* EMACDisable */
#define M_ECTL_ES               _DD_MAKEMASK1(2)        /* EMACSoftReset */
#define M_ECTL_EP               _DD_MAKEMASK1(3)        /* ExtPHYSelect */

/* TCTL: Transmit Control Register (0x430, R/W) */

#define M_TCTL_FD               _DD_MAKEMASK1(0)        /* FullDuplex */
#define M_TCTL_FM               _DD_MAKEMASK1(1)        /* FlowMode */
#define M_TCTL_SB               _DD_MAKEMASK1(2)        /* SingleBackoffEn */
#define M_TCTL_SS               _DD_MAKEMASK1(3)        /* SmSlotTime */

/* MIBCTL: MIB Control Register (0x438, R/W) */

#define M_MIBCTL_RO              _DD_MAKEMASK1(0)       /* RO */


/* DMA Control Registers */

/* XCTL: Transmit Channel Control Register (0x200, R/W) */

#define M_XCTL_XE               _DD_MAKEMASK1(0)        /* XmtEn */
#define M_XCTL_SE               _DD_MAKEMASK1(1)        /* SuspEn */
#define M_XCTL_LE               _DD_MAKEMASK1(2)        /* LoopbackEn */
#define M_XCTL_FP               _DD_MAKEMASK1(3)        /* FairPriority */

/* XADDR: Transmit Descriptor Table Address Register (0x204, R/W) */

#define S_XADDR_BA              12                      /* BaseAddr */
#define M_XADDR_BA              _DD_MAKEMASK(20,S_XADDR_BA)
#define V_XADDR_BA(x)           _DD_MAKEVALUE(x,S_XADDR_BA)
#define G_XADDR_BA(x)           _DD_GETVALUE(x,S_XADDR_BA,M_XADDR_BA)

/* XPTR: Transmit Descriptor Table Pointer Register (0x208, R/W) */

#define S_XPTR_LD              0                        /* LastDscr */
#define M_XPTR_LD              _DD_MAKEMASK(12,S_XPTR_LD)
#define V_XPTR_LD(x)           _DD_MAKEVALUE(x,S_XPTR_LD)
#define G_XPTR_LD(x)           _DD_GETVALUE(x,S_XPTR_LD,M_XPTR_LD)

/* XSTAT: Transmit Channel Status Register (0x20C, RO) */

#define S_XSTAT_CD             0                        /* CurrDscr */
#define M_XSTAT_CD             _DD_MAKEMASK(12,S_XSTAT_CD)
#define V_XSTAT_CD(x)          _DD_MAKEVALUE(x,S_XSTAT_CD)
#define G_XSTAT_CD(x)          _DD_GETVALUE(x,S_XSTAT_CD,M_XSTAT_CD)

#define S_XSTAT_XS             12                       /* XmtState */
#define M_XSTAT_XS             _DD_MAKEMASK(4,S_XSTAT_XS)
#define V_XSTAT_XS(x)          _DD_MAKEVALUE(x,S_XSTAT_XS)
#define G_XSTAT_XS(x)          _DD_GETVALUE(x,S_XSTAT_XS,M_XSTAT_XS)
#define K_XS_DISABLED          0x0
#define K_XS_ACTIVE            0x1
#define K_XS_IDLE_WAIT         0x2
#define K_XS_STOPPED           0x3
#define K_XS_SUSPEND_PENDING   0x4

#define S_XSTAT_XE             16                       /* XmtErr */
#define M_XSTAT_XE             _DD_MAKEMASK(4,S_XSTAT_XE)
#define V_XSTAT_XE(x)          _DD_MAKEVALUE(x,S_XSTAT_XE)
#define G_XSTAT_XE(x)          _DD_GETVALUE(x,S_XSTAT_XE,M_XSTAT_XE)
#define K_XE_NONE              0x0
#define K_XE_DSCR_PROTOCOL     0x1
#define K_XE_FIFO_UNDERRUN     0x2
#define K_XE_DATA_TRANSFER     0x3
#define K_XE_DSCR_READ         0x4

/* RCTL: Receive Channel Control Register (0x210, R/W) */

#define M_RCTL_RE               _DD_MAKEMASK1(0)        /* RcvEn */

#define S_RCTL_RO               1                       /* RcvOffset */
#define M_RCTL_RO               _DD_MAKEMASK(7,S_RCTL_RO)
#define V_RCTL_RO(x)            _DD_MAKEVALUE(x,S_RCTL_RO)
#define G_RCTL_RO(x)            _DD_GETVALUE(x,S_RCTL_RO,M_RCTL_RO)

#define M_RCTL_FM               _DD_MAKEMASK1(8)        /* FIFOMode */

/* RADDR: Receive Descriptor Table Address Register (0x214, R/W) */

#define S_RADDR_BA              12                      /* BaseAddr */
#define M_RADDR_BA              _DD_MAKEMASK(20,S_RADDR_BA)
#define V_RADDR_BA(x)           _DD_MAKEVALUE(x,S_RADDR_BA)
#define G_RADDR_BA(x)           _DD_GETVALUE(x,S_RADDR_BA,M_RADDR_BA)

/* RPTR: Receive Descriptor Table Pointer Register (0x218, R/W) */

#define S_RPTR_LD              0                        /* LastDscr */
#define M_RPTR_LD              _DD_MAKEMASK(12,S_RPTR_LD)
#define V_RPTR_LD(x)           _DD_MAKEVALUE(x,S_RPTR_LD)
#define G_RPTR_LD(x)           _DD_GETVALUE(x,S_RPTR_LD,M_RPTR_LD)

/* RSTAT: Receive Channel Status Register (0x21C, RO) */

#define S_RSTAT_CD             0                        /* CurrDscr */
#define M_RSTAT_CD             _DD_MAKEMASK(12,S_RSTAT_CD)
#define V_RSTAT_CD(x)          _DD_MAKEVALUE(x,S_RSTAT_CD)
#define G_RSTAT_CD(x)          _DD_GETVALUE(x,S_RSTAT_CD,M_RSTAT_CD)

#define S_RSTAT_RS             12                       /* RcvState */
#define M_RSTAT_RS             _DD_MAKEMASK(4,S_RSTAT_RS)
#define V_RSTAT_RS(x)          _DD_MAKEVALUE(x,S_RSTAT_RS)
#define G_RSTAT_RS(x)          _DD_GETVALUE(x,S_RSTAT_RS,M_RSTAT_RS)
#define K_RS_DISABLED          0x0
#define K_RS_ACTIVE            0x1
#define K_RS_IDLE_WAIT         0x2
#define K_RS_STOPPED           0x3

#define S_RSTAT_RE             16                       /* RcvErr */
#define M_RSTAT_RE             _DD_MAKEMASK(4,S_RSTAT_RE)
#define V_RSTAT_RE(x)          _DD_MAKEVALUE(x,S_RSTAT_RE)
#define G_RSTAT_RE(x)          _DD_GETVALUE(x,S_RSTAT_RE,M_RSTAT_RE)
#define K_RE_NONE              0x0
#define K_RE_DSCR_PROTOCOL     0x1
#define K_RE_FIFO_OVERFLOW     0x2
#define K_RE_DATA_TRANSFER     0x3
#define K_RE_DSCR_READ         0x4


/* DMA Descriptor Structure (Table 66) */

/* Word 0: Flags and Count */

#define S_DSCR0_BC             0                        /* BufCount */
#define M_DSCR0_BC             _DD_MAKEMASK(13,S_DSCR0_BC)
#define V_DSCR0_BC(x)          _DD_MAKEVALUE(x,S_DSCR0_BC)
#define G_DSCR0_BC(x)          _DD_GETVALUE(x,S_DSCR0_BC,M_DSCR0_BC)

#define S_DSCR0_FL             20                       /* Flags */
#define M_DSCR0_FL             _DD_MAKEMASK(8,S_DSCR0_FL)
#define V_DSCR0_FL(x)          _DD_MAKEVALUE(x,S_DSCR0_FL)
#define G_DSCR0_FL(x)          _DD_GETVALUE(x,S_DSCR0_FL,M_DSCR0_FL)

#define M_DSCR0_ET             _DD_MAKEMASK1(28)        /* EOT */
#define M_DSCR0_IC             _DD_MAKEMASK1(29)        /* IOC */
#define M_DSCR0_EF             _DD_MAKEMASK1(30)        /* EOF */
#define M_DSCR0_SF             _DD_MAKEMASK1(31)        /* SOF */

/* Word 1: Data Buffer Pointer */

#define S_DSCR1_DB             0                        /* DataBufPtr */
#define M_DSCR1_DB             _DD_MAKEMASK(32, S_DSCR1_DB)
#define V_DSCR1_DB(x)          _DD_MAKEVALUE(x,S_DSCR1_DB)
#define G_DSCR1_DB(x)          _DD_GETVALUE(x,S_DSCR1_DB,M_DSCR1_DB)


/* DMA Receive Headers (Table 67) */

#define S_RCVHDR0_CD           0                        /* FrameLen (!) */
#define M_RCVHDR0_CD           _DD_MAKEMASK(16,S_RCVHDR0_CD)
#define V_RCVHDR0_CD(x)        _DD_MAKEVALUE(x,S_RCVHDR0_CD)
#define G_RCVHDR0_CD(x)        _DD_GETVALUE(x,S_RCVHDR0_CD,M_RCVHDR0_CD)

#define S_RCVHDR0_DC           24                       /* DescrCnt */
#define M_RCVHDR0_DC           _DD_MAKEMASK(4,S_RCVHDR0_DC)
#define V_RCVHDR0_DC(x)        _DD_MAKEVALUE(x,S_RCVHDR0_DC)
#define G_RCVHDR0_DC(x)        _DD_GETVALUE(x,S_RCVHDR0_DC,M_RCVHDR0_DC)

/* The presence of these flags can depend on which version of the core you have. */
#define M_RCVHDR0_L            _DD_MAKEMASK1(27)         /* Last */
#define M_RCVHDR0_F            _DD_MAKEMASK1(26)         /* First */
#define M_RCVHDR0_W            _DD_MAKEMASK1(25)         /* Wrap */
#define M_RCVHDR0_MISS         _DD_MAKEMASK1(23)         /* Miss */
#define M_RCVHDR0_BRDCAST      _DD_MAKEMASK1(22)         /* Broadcast */
#define M_RCVHDR0_MULT         _DD_MAKEMASK1(21)         /* Multicast */
#define M_RCVHDR0_LG           _DD_MAKEMASK1(20)         /* Large */
#define M_RCVHDR0_NO           _DD_MAKEMASK1(19)         /* NonOctet Aligned */
#define M_RCVHDR0_RXER         _DD_MAKEMASK1(18)         /* Symbol Error */
#define M_RCVHDR0_CRC          _DD_MAKEMASK1(17)         /* CRC */
#define M_RCVHDR0_OV           _DD_MAKEMASK1(16)         /* Overflow */
#define M_RCVHDR0_ERRORS       (M_RCVHDR0_NO | M_RCVHDR0_RXER | M_RCVHDR0_CRC \
                                | M_RCVHDR0_OV)


/* Offsets of MIB counters in Statistics Block (Table 161)
   Registers are 16 bits except as noted. */

#define TX_GD_OCTETS            0x500        /* 32 bits */
#define TX_GD_PKTS              0x504
#define TX_ALL_OCTETS           0x508        /* 32 bits */
#define TX_ALL_PKTS             0x50C
#define TX_BRDCAST              0x510
#define TX_MULT                 0x514
#define TX_64                   0x518
#define TX_65_127               0x51C
#define TX_128_255              0x520
#define TX_256_511              0x524
#define TX_512_1023             0x528
#define TX_1024_MAX             0x52C
#define TX_JAB                  0x530
#define TX_OVR                  0x534
#define TX_FRAG                 0x538
#define TX_UNDERRUN             0x53C
#define TX_COL                  0x540
#define TX_1_COL                0x544
#define TX_M_COL                0x548
#define TX_EX_COL               0x54C
#define TX_LATE                 0x550
#define TX_DEF                  0x554
#define TX_CRS                  0x558
#define TX_PAUS                 0x55C

#define RX_GD_OCTETS            0x580        /* 32 bits */
#define RX_GD_PKTS              0x584
#define RX_ALL_OCTETS           0x588        /* 32 bits */
#define RX_ALL_PKTS             0x58C
#define RX_BRDCAST              0x590
#define RX_MULT                 0x594
#define RX_64                   0x598
#define RX_65_127               0x59C
#define RX_128_255              0x5A0
#define RX_256_511              0x5A4
#define RX_512_1023             0x5A8
#define RX_1024_MAX             0x5AC
#define RX_JAB                  0x5B0
#define RX_OVR                  0x5B4
#define RX_FRAG                 0x5B8
#define RX_DROP                 0x5BC
#define RX_CRC_ALIGN            0x5C0
#define RX_UND                  0x5C4
#define RX_CRC                  0x5C8
#define RX_ALIGN                0x5CC
#define RX_SYM                  0x5D0
#define RX_PAUSE                0x5D4
#define RX_CNTRL                0x5D8


/* In the default mapping, the top 4K of the BAR0 window maps into the
   SPROM.  Note that access latency is high and the corresponding code
   must be prepared to avoid or deal with bus errors caused by PCI
   timeouts. */

#define SPROM_BASE             0x1000

#define SPROM_MAC_ADDR         0x4E         /* 6 bytes */
#define SPROM_PHY_ADDR         90           /* 2 bytes, bits [4:0] (undoc) */

#endif /* _SBMAC_H_ */