📄 bcm1480_hsp.h

📁 一个很好的嵌入式linux平台下的bootloader
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#define G_BCM1480_HSP_RX_ALPHA(x)        _SB_GETVALUE(x,S_BCM1480_HSP_RX_ALPHA,M_BCM1480_HSP_RX_ALPHA)/* * RX SPI4 Calendar registers (Table 364) * Use these macros for both the _0 and _1 registers.  The arg 'c' is the calendar location */#define S_BCM1480_HSP_RX_CALENDAR_X(c)	(((c)&7)*8)#define M_BCM1480_HSP_RX_CALENDAR_X(c)      _SB_MAKEMASK(12,S_BCM1480_HSP_RX_CALENDAR_X(c))#define V_BCM1480_HSP_RX_CALENDAR_X(c,x)    _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_CALENDAR_X(c))#define G_BCM1480_HSP_RX_CALENDAR_X(c,x)    _SB_GETVALUE(x,S_BCM1480_HSP_RX_CALENDAR_X(c),M_BCM1480_HSP_RX_CALENDAR_X(c))/*  * RX SPI4 Watermark registers (Table 365) */#define S_BCM1480_HSP_RX_ALMOSTEMPTY_EVEN          0#define M_BCM1480_HSP_RX_ALMOSTEMPTY_EVEN          _SB_MAKEMASK(10,S_BCM1480_HSP_RX_ALMOSTEMPTY_EVEN)#define V_BCM1480_HSP_RX_ALMOSTEMPTY_EVEN(x)       _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_ALMOSTEMPTY_EVEN)#define G_BCM1480_HSP_RX_ALMOSTEMPTY_EVEN(x)       _SB_GETVALUE(x,S_BCM1480_HSP_RX_ALMOSTEMPTY_EVEN,M_BCM1480_HSP_RX_ALMOSTEMPTY_EVEN)#define S_BCM1480_HSP_RX_ALMOSTFULL_EVEN          16#define M_BCM1480_HSP_RX_ALMOSTFULL_EVEN          _SB_MAKEMASK(10,S_BCM1480_HSP_RX_ALMOSTFULL_EVEN)#define V_BCM1480_HSP_RX_ALMOSTFULL_EVEN(x)       _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_ALMOSTFULL_EVEN)#define G_BCM1480_HSP_RX_ALMOSTFULL_EVEN(x)       _SB_GETVALUE(x,S_BCM1480_HSP_RX_ALMOSTFULL_EVEN,M_BCM1480_HSP_RX_ALMOSTFULL_EVEN)#define S_BCM1480_HSP_RX_ALMOSTEMPTY_ODD          32#define M_BCM1480_HSP_RX_ALMOSTEMPTY_ODD          _SB_MAKEMASK(10,S_BCM1480_HSP_RX_ALMOSTEMPTY_ODD)#define V_BCM1480_HSP_RX_ALMOSTEMPTY_ODD(x)       _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_ALMOSTEMPTY_ODD)#define G_BCM1480_HSP_RX_ALMOSTEMPTY_ODD(x)       _SB_GETVALUE(x,S_BCM1480_HSP_RX_ALMOSTEMPTY_ODD,M_BCM1480_HSP_RX_ALMOSTEMPTY_ODD)#define S_BCM1480_HSP_RX_ALMOSTFULL_ODD          48#define M_BCM1480_HSP_RX_ALMOSTFULL_ODD          _SB_MAKEMASK(10,S_BCM1480_HSP_RX_ALMOSTFULL_ODD)#define V_BCM1480_HSP_RX_ALMOSTFULL_ODD(x)       _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_ALMOSTFULL_ODD)#define G_BCM1480_HSP_RX_ALMOSTFULL_ODD(x)       _SB_GETVALUE(x,S_BCM1480_HSP_RX_ALMOSTFULL_ODD,M_BCM1480_HSP_RX_ALMOSTFULL_ODD)/* * TX SPI4 Configuration Register 1 (Table 366) */#define S_BCM1480_HSP_TX_CALENDAR_LEN           0#define M_BCM1480_HSP_TX_CALENDAR_LEN           _SB_MAKEMASK(8,S_BCM1480_HSP_TX_CALENDAR_LEN)#define V_BCM1480_HSP_TX_CALENDAR_LEN(x)        _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_CALENDAR_LEN)#define G_BCM1480_HSP_TX_CALENDAR_LEN(x)        _SB_GETVALUE(x,S_BCM1480_HSP_TX_CALENDAR_LEN,M_BCM1480_HSP_TX_CALENDAR_LEN)#define S_BCM1480_HSP_TX_CALENDAR_M           16#define M_BCM1480_HSP_TX_CALENDAR_M           _SB_MAKEMASK(8,S_BCM1480_HSP_TX_CALENDAR_M)#define V_BCM1480_HSP_TX_CALENDAR_M(x)        _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_CALENDAR_M)#define G_BCM1480_HSP_TX_CALENDAR_M(x)        _SB_GETVALUE(x,S_BCM1480_HSP_TX_CALENDAR_M,M_BCM1480_HSP_TX_CALENDAR_M)#define S_BCM1480_HSP_TX_MAXBURST1           24#define M_BCM1480_HSP_TX_MAXBURST1           _SB_MAKEMASK(8,S_BCM1480_HSP_TX_MAXBURST1)#define V_BCM1480_HSP_TX_MAXBURST1(x)        _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_MAXBURST1)#define G_BCM1480_HSP_TX_MAXBURST1(x)        _SB_GETVALUE(x,S_BCM1480_HSP_TX_MAXBURST1,M_BCM1480_HSP_TX_MAXBURST1)#define S_BCM1480_HSP_TX_MAXBURST2           32#define M_BCM1480_HSP_TX_MAXBURST2           _SB_MAKEMASK(8,S_BCM1480_HSP_TX_MAXBURST2)#define V_BCM1480_HSP_TX_MAXBURST2(x)        _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_MAXBURST2)#define G_BCM1480_HSP_TX_MAXBURST2(x)        _SB_GETVALUE(x,S_BCM1480_HSP_TX_MAXBURST2,M_BCM1480_HSP_TX_MAXBURST2)#define S_BCM1480_HSP_TX_ALPHA           40#define M_BCM1480_HSP_TX_ALPHA           _SB_MAKEMASK(12,S_BCM1480_HSP_TX_ALPHA)#define V_BCM1480_HSP_TX_ALPHA(x)        _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_ALPHA)#define G_BCM1480_HSP_TX_ALPHA(x)        _SB_GETVALUE(x,S_BCM1480_HSP_TX_ALPHA,M_BCM1480_HSP_TX_ALPHA)#define S_BCM1480_HSP_TX_ACTIVE_CHANNELS           56#define M_BCM1480_HSP_TX_ACTIVE_CHANNELS           _SB_MAKEMASK(8,S_BCM1480_HSP_TX_ACTIVE_CHANNELS)#define V_BCM1480_HSP_TX_ACTIVE_CHANNELS(x)        _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_ACTIVE_CHANNELS)#define G_BCM1480_HSP_TX_ACTIVE_CHANNELS(x)        _SB_GETVALUE(x,S_BCM1480_HSP_TX_ACTIVE_CHANNELS,M_BCM1480_HSP_TX_ACTIVE_CHANNELS)/* * TX SPI4 Calendar registers (Table 367) * Use these macros for both the _0 and _1 registers.  The arg 'c' is the calendar location */#define S_BCM1480_HSP_TX_CALENDAR_X(c)	(((c)&7)*8)#define M_BCM1480_HSP_TX_CALENDAR_X(c)      _SB_MAKEMASK(12,S_BCM1480_HSP_TX_CALENDAR_X(c))#define V_BCM1480_HSP_TX_CALENDAR_X(c,x)    _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_CALENDAR_X(c))#define G_BCM1480_HSP_TX_CALENDAR_X(c,x)    _SB_GETVALUE(x,S_BCM1480_HSP_TX_CALENDAR_X(c),M_BCM1480_HSP_TX_CALENDAR_X(c))/* * TX Packet Buffer Allocation Physical Unit Count Registers (Table 368) */#define S_BCM1480_HSP_RX_PHITCNT_0          0#define M_BCM1480_HSP_RX_PHITCNT_0          _SB_MAKEMASK(10,S_BCM1480_HSP_RX_PHITCNT_0)#define V_BCM1480_HSP_RX_PHITCNT_0(x)       _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_PHITCNT_0)#define G_BCM1480_HSP_RX_PHITCNT_0(x)       _SB_GETVALUE(x,S_BCM1480_HSP_RX_PHITCNT_0,M_BCM1480_HSP_RX_PHITCNT_0)#define S_BCM1480_HSP_RX_PHITCNT_1          16#define M_BCM1480_HSP_RX_PHITCNT_1          _SB_MAKEMASK(10,S_BCM1480_HSP_RX_PHITCNT_1)#define V_BCM1480_HSP_RX_PHITCNT_1(x)       _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_PHITCNT_1)#define G_BCM1480_HSP_RX_PHITCNT_1(x)       _SB_GETVALUE(x,S_BCM1480_HSP_RX_PHITCNT_1,M_BCM1480_HSP_RX_PHITCNT_1)#define S_BCM1480_HSP_RX_PHITCNT_2          32#define M_BCM1480_HSP_RX_PHITCNT_2          _SB_MAKEMASK(10,S_BCM1480_HSP_RX_PHITCNT_2)#define V_BCM1480_HSP_RX_PHITCNT_2(x)       _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_PHITCNT_2)#define G_BCM1480_HSP_RX_PHITCNT_2(x)       _SB_GETVALUE(x,S_BCM1480_HSP_RX_PHITCNT_2,M_BCM1480_HSP_RX_PHITCNT_2)#define S_BCM1480_HSP_RX_PHITCNT_3          48#define M_BCM1480_HSP_RX_PHITCNT_3          _SB_MAKEMASK(10,S_BCM1480_HSP_RX_PHITCNT_3)#define V_BCM1480_HSP_RX_PHITCNT_3(x)       _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_PHITCNT_3)#define G_BCM1480_HSP_RX_PHITCNT_3(x)       _SB_GETVALUE(x,S_BCM1480_HSP_RX_PHITCNT_3,M_BCM1480_HSP_RX_PHITCNT_3)/* * TX HT I/O Physical Unit Count Register (Table 369) */#define S_BCM1480_HSP_RX_NPC_CMD_PHITCNT    0#define M_BCM1480_HSP_RX_NPC_CMD_PHITCNT    _SB_MAKEMASK(8,S_BCM1480_HSP_RX_NPC_CMD_PHITCNT)#define V_BCM1480_HSP_RX_NPC_CMD_PHITCNT(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_NPC_CMD_PHITCNT)#define G_BCM1480_HSP_RX_NPC_CMD_PHITCNT(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_NPC_CMD_PHITCNT,M_BCM1480_HSP_RX_NPC_CMD_PHITCNT)#define S_BCM1480_HSP_RX_NPC_DAT_PHITCNT    8#define M_BCM1480_HSP_RX_NPC_DAT_PHITCNT    _SB_MAKEMASK(8,S_BCM1480_HSP_RX_NPC_DAT_PHITCNT)#define V_BCM1480_HSP_RX_NPC_DAT_PHITCNT(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_NPC_DAT_PHITCNT)#define G_BCM1480_HSP_RX_NPC_DAT_PHITCNT(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_NPC_DAT_PHITCNT,M_BCM1480_HSP_RX_NPC_DAT_PHITCNT)#define S_BCM1480_HSP_RX_RSP_DAT_PHITCNT    24#define M_BCM1480_HSP_RX_RSP_DAT_PHITCNT    _SB_MAKEMASK(8,S_BCM1480_HSP_RX_RSP_DAT_PHITCNT)#define V_BCM1480_HSP_RX_RSP_DAT_PHITCNT(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_RSP_DAT_PHITCNT)#define G_BCM1480_HSP_RX_RSP_DAT_PHITCNT(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_RSP_DAT_PHITCNT,M_BCM1480_HSP_RX_RSP_DAT_PHITCNT)#define S_BCM1480_HSP_RX_PC_CMD_PHITCNT     32#define M_BCM1480_HSP_RX_PC_CMD_PHITCNT     _SB_MAKEMASK(8,S_BCM1480_HSP_RX_PC_CMD_PHITCNT)#define V_BCM1480_HSP_RX_PC_CMD_PHITCNT(x)  _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_PC_CMD_PHITCNT)#define G_BCM1480_HSP_RX_PC_CMD_PHITCNT(x)  _SB_GETVALUE(x,S_BCM1480_HSP_RX_PC_CMD_PHITCNT,M_BCM1480_HSP_RX_PC_CMD_PHITCNT)#define S_BCM1480_HSP_RX_PC_DAT_PHITCNT     48#define M_BCM1480_HSP_RX_PC_DAT_PHITCNT     _SB_MAKEMASK(8,S_BCM1480_HSP_RX_PC_DAT_PHITCNT)#define V_BCM1480_HSP_RX_PC_DAT_PHITCNT(x)  _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_PC_DAT_PHITCNT)#define G_BCM1480_HSP_RX_PC_DAT_PHITCNT(x)  _SB_GETVALUE(x,S_BCM1480_HSP_RX_PC_DAT_PHITCNT,M_BCM1480_HSP_RX_PC_DAT_PHITCNT)/* * TX HTCC Buffer Allocation Registers (Table 370)  */#define S_BCM1480_HSP_TX_HTCC_PRB_PHITCNT          0#define M_BCM1480_HSP_TX_HTCC_PRB_PHITCNT          _SB_MAKEMASK(8,S_BCM1480_HSP_TX_HTCC_PRB_PHITCNT)#define V_BCM1480_HSP_TX_HTCC_PRB_PHITCNT(x)       _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_HTCC_PRB_PHITCNT)#define G_BCM1480_HSP_TX_HTCC_PRB_PHITCNT(x)       _SB_GETVALUE(x,S_BCM1480_HSP_TX_HTCC_PRB_PHITCNT,M_BCM1480_HSP_TX_HTCC_PRB_PHITCNT)#define S_BCM1480_HSP_TX_HTCC_ACK_PHITCNT          8#define M_BCM1480_HSP_TX_HTCC_ACK_PHITCNT          _SB_MAKEMASK(8,S_BCM1480_HSP_TX_HTCC_ACK_PHITCNT)#define V_BCM1480_HSP_TX_HTCC_ACK_PHITCNT(x)       _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_HTCC_ACK_PHITCNT)#define G_BCM1480_HSP_TX_HTCC_ACK_PHITCNT(x)       _SB_GETVALUE(x,S_BCM1480_HSP_TX_HTCC_ACK_PHITCNT,M_BCM1480_HSP_TX_HTCC_ACK_PHITCNT)#define S_BCM1480_HSP_TX_HTCC_WB_PHITCNT          24#define M_BCM1480_HSP_TX_HTCC_WB_PHITCNT          _SB_MAKEMASK(8,S_BCM1480_HSP_TX_HTCC_WB_PHITCNT)#define V_BCM1480_HSP_TX_HTCC_WB_PHITCNT(x)       _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_HTCC_WB_PHITCNT)#define G_BCM1480_HSP_TX_HTCC_WB_PHITCNT(x)       _SB_GETVALUE(x,S_BCM1480_HSP_TX_HTCC_WB_PHITCNT,M_BCM1480_HSP_TX_HTCC_WB_PHITCNT)#define S_BCM1480_HSP_TX_HTCC_CFILL_PHITCNT          32#define M_BCM1480_HSP_TX_HTCC_CFILL_PHITCNT          _SB_MAKEMASK(8,S_BCM1480_HSP_TX_HTCC_CFILL_PHITCNT)#define V_BCM1480_HSP_TX_HTCC_CFILL_PHITCNT(x)       _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_HTCC_CFILL_PHITCNT)#define G_BCM1480_HSP_TX_HTCC_CFILL_PHITCNT(x)       _SB_GETVALUE(x,S_BCM1480_HSP_TX_HTCC_CFILL_PHITCNT,M_BCM1480_HSP_TX_HTCC_CFILL_PHITCNT)#define S_BCM1480_HSP_TX_HTCC_CRD_PHITCNT          40#define M_BCM1480_HSP_TX_HTCC_CRD_PHITCNT          _SB_MAKEMASK(8,S_BCM1480_HSP_TX_HTCC_CRD_PHITCNT)#define V_BCM1480_HSP_TX_HTCC_CRD_PHITCNT(x)       _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_HTCC_CRD_PHITCNT)#define G_BCM1480_HSP_TX_HTCC_CRD_PHITCNT(x)       _SB_GETVALUE(x,S_BCM1480_HSP_TX_HTCC_CRD_PHITCNT,M_BCM1480_HSP_TX_HTCC_CRD_PHITCNT)/* * TX Packet Buffer Allocation Registers (Table 371) */#define S_BCM1480_HSP_TX_PHITCNT_0          0#define M_BCM1480_HSP_TX_PHITCNT_0          _SB_MAKEMASK(8,S_BCM1480_HSP_TX_PHITCNT_0)#define V_BCM1480_HSP_TX_PHITCNT_0(x)       _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_PHITCNT_0)#define G_BCM1480_HSP_TX_PHITCNT_0(x)       _SB_GETVALUE(x,S_BCM1480_HSP_TX_PHITCNT_0,M_BCM1480_HSP_TX_PHITCNT_0)#define S_BCM1480_HSP_TX_PHITCNT_1          16#define M_BCM1480_HSP_TX_PHITCNT_1          _SB_MAKEMASK(8,S_BCM1480_HSP_TX_PHITCNT_1)#define V_BCM1480_HSP_TX_PHITCNT_1(x)       _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_PHITCNT_1)#define G_BCM1480_HSP_TX_PHITCNT_1(x)       _SB_GETVALUE(x,S_BCM1480_HSP_TX_PHITCNT_1,M_BCM1480_HSP_TX_RAMPHITCNT_1)#define S_BCM1480_HSP_TX_PHITCNT_2          32#define M_BCM1480_HSP_TX_PHITCNT_2          _SB_MAKEMASK(8,S_BCM1480_HSP_TX_PHITCNT_2)#define V_BCM1480_HSP_TX_PHITCNT_2(x)       _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_PHITCNT_2)#define G_BCM1480_HSP_TX_PHITCNT_2(x)       _SB_GETVALUE(x,S_BCM1480_HSP_TX_PHITCNT_2,M_BCM1480_HSP_TX_PHITCNT_2)#define S_BCM1480_HSP_TX_PHITCNT_3          48#define M_BCM1480_HSP_TX_PHITCNT_3          _SB_MAKEMASK(8,S_BCM1480_HSP_TX_PHITCNT_3)#define V_BCM1480_HSP_TX_PHITCNT_3(x)       _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_PHITCNT_3)#define G_BCM1480_HSP_TX_PHITCNT_3(x)       _SB_GETVALUE(x,S_BCM1480_HSP_TX_PHITCNT_3,M_BCM1480_HSP_TX_RAMPHITCNT_3)/* * TX Non-Posted Command (NPC) Allocation Register (Table 372) */#define S_BCM1480_HSP_TX_NPC_PHITCNT          0#define M_BCM1480_HSP_TX_NPC_PHITCNT          _SB_MAKEMASK(8,S_BCM1480_HSP_TX_NPC_PHITCNT)#define V_BCM1480_HSP_TX_NPC_PHITCNT(x)       _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_NPC_PHITCNT)#define G_BCM1480_HSP_TX_NPC_PHITCNT(x)       _SB_GETVALUE(x,S_BCM1480_HSP_TX_NPC_PHITCNT,M_BCM1480_HSP_TX_NPC_PHITCNT)#define S_BCM1480_HSP_TX_RSP_PHITCNT          24#define M_BCM1480_HSP_TX_RSP_PHITCNT          _SB_MAKEMASK(8,S_BCM1480_HSP_TX_RSP_PHITCNT)#define V_BCM1480_HSP_TX_RSP_PHITCNT(x)       _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_RSP_PHITCNT)#define G_BCM1480_HSP_TX_RSP_PHITCNT(x)       _SB_GETVALUE(x,S_BCM1480_HSP_TX_RSP_PHITCNT,M_BCM1480_HSP_TX_RSP_PHITCNT)#define S_BCM1480_HSP_TX_PC_PHITCNT           48#define M_BCM1480_HSP_TX_PC_PHITCNT           _SB_MAKEMASK(8,S_BCM1480_HSP_TX_PC_PHITCNT)#define V_BCM1480_HSP_TX_PC_PHITCNT(x)        _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_PC_PHITCNT)#define G_BCM1480_HSP_TX_PC_PHITCNT(x)        _SB_GETVALUE(x,S_BCM1480_HSP_TX_PC_PHITCNT,M_BCM1480_HSP_TX_PC_PHITCNT)#define S_BCM1480_HSP_TX_NEXT_ADDR_EVEN       0#define M_BCM1480_HSP_TX_NEXT_ADDR_EVEN       _SB_MAKEMASK(32,S_BCM1480_HSP_TX_NEXT_ADDR_EVEN)#define V_BCM1480_HSP_TX_NEXT_ADDR_EVEN(x)    _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_NEXT_ADDR_EVEN)#define G_BCM1480_HSP_TX_NEXT_ADDR_EVEN(x)    _SB_GETVALUE(x,S_BCM1480_HSP_TX_NEXT_ADDR_EVEN,M_BCM1480_HSP_TX_NEXT_ADDR_EVEN)#define S_BCM1480_HSP_TX_NEXT_ADDR_ODD       32#define M_BCM1480_HSP_TX_NEXT_ADDR_ODD       _SB_MAKEMASK(32,S_BCM1480_HSP_TX_NEXT_ADDR_ODD)#define V_BCM1480_HSP_TX_NEXT_ADDR_ODD(x)    _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_NEXT_ADDR_ODD)#define G_BCM1480_HSP_TX_NEXT_ADDR_ODD(x)    _SB_GETVALUE(x,S_BCM1480_HSP_TX_NEXT_ADDR_ODD,M_BCM1480_HSP_TX_NEXT_ADDR_ODD)/* * TX HTCC Physical Unot Count (Table 373) *//* See definitions for table 370. *//*  *********************************************************************    *  Managability/Testability registers    *  BROADCOM USE ONLY    ********************************************************************* *//* * RX PLL Config (Table 374) * BROADCOM USE ONLY */#define S_BCM1480_HSP_RXPLL_FREQF_SEL                0#define M_BCM1480_HSP_RXPLL_FREQF_SEL                _SB_MAKEMASK(4,S_BCM1480_HSP_RXPLL_FREQF_SEL)#define V_BCM1480_HSP_RXPLL_FREQF_SEL(x)             _SB_MAKEVALUE(x,S_BCM1480_HSP_RXPLL_FREQF_SEL)#define G_BCM1480_HSP_RXPLL_FREQF_SEL(x)             _SB_GETVALUE(x,S_BCM1480_HSP_RXPLL_FREQF_SEL,M_BCM1480_HSP_RXPLL_FREQF_SEL)#define S_BCM1480_HSP_RXPLL_FDBK_SEL                4#define M_BCM1480_HSP_RXPLL_FDBK_SEL                _SB_MAKEMASK(4,S_BCM1480_HSP_RXPLL_FDBK_SEL)#define V_BCM1480_HSP_RXPLL_FDBK_SEL(x)             _SB_MAKEVALUE(x,S_BCM1480_HSP_RXPLL_FDBK_SEL)#define G_BCM1480_HSP_RXPLL_FDBK_SEL(x)             _SB_GETVALUE(x,S_BCM1480_HSP_RXPLL_FDBK_SEL,M_BCM1480_HSP_RXPLL_FDBK_SEL)#define S_BCM1480_HSP_RXPLL_VCO_RANGE                8#define M_BCM1480_HSP_RXPLL_VCO_RANGE                _SB_MAKEMASK(2,S_BCM1480_HSP_RXPLL_VCO_RANGE)#define V_BCM1480_HSP_RXPLL_VCO_RANGE(x)             _SB_MAKEVALUE(x,S_BCM1480_HSP_RXPLL_VCO_RANGE)#define G_BCM1480_HSP_RXPLL_VCO_RANGE(x)             _SB_GETVALUE(x,S_BCM1480_HSP_RXPLL_VCO_RANGE,M_BCM1480_HSP_RXPLL_VCO_RANGE)#define M_BCM1480_HSP_RXPLL_DIV4 		_SB_MAKEMASK1(10)#define M_BCM1480_HSP_RXPLL_PLLOVERRIDE		_SB_MAKEMASK1(12)#define M_BCM1480_HSP_RXPLL_VCOOVERRIDE		_SB_MAKEMASK1(13)#define S_BCM1480_HSP_RXPLL_RX_PLLTEST                14#define M_BCM1480_HSP_RXPLL_RX_PLLTEST                _SB_MAKEMASK(2,S_BCM1480_HSP_RXPLL_RX_PLLTEST)#define V_BCM1480_HSP_RXPLL_RX_PLLTEST(x)             _SB_MAKEVALUE(x,S_BCM1480_HSP_RXPLL_RX_PLLTEST)#define G_BCM1480_HSP_RXPLL_RX_PLLTEST(x)             _SB_GETVALUE(x,S_BCM1480_HSP_RXPLL_RX_PLLTEST,M_BCM1480_HSP_RXPLL_RX_PLLTEST)#define S_BCM1480_HSP_RXPLL_RX_PLLCTRL                16#define M_BCM1480_HSP_RXPLL_RX_PLLCTRL                _SB_MAKEMASK(6,S_BCM1480_HSP_RXPLL_RX_PLLCTRL)#define V_BCM1480_HSP_RXPLL_RX_PLLCTRL(x)             _SB_MAKEVALUE(x,S_BCM1480_HSP_RXPLL_RX_PLLCTRL)#define G_BCM1480_HSP_RXPLL_RX_PLLCTRL(x)             _SB_GETVALUE(x,S_BCM1480_HSP_RXPLL_RX_PLLCTRL,M_BCM1480_HSP_RXPLL_RX_PLLCTRL)/* * TX PLL Config (Table 375) * BROADCOM USE ONLY */#define S_BCM1480_HSP_TXPLL_FREQF_SEL                0#define M_BCM1480_HSP_TXPLL_FREQF_SEL                _SB_MAKEMASK(4,S_BCM1480_HSP_TXPLL_FREQF_SEL)
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