📄 bcm1480_hsp.h

📁 一个很好的嵌入式linux平台下的bootloader
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#define M_BCM1480_HSP_RX_DIAGDET_SPI4_HRMULTMATCH	_SB_MAKEMASK1(48)#define M_BCM1480_HSP_RX_DIAGDET_SPI4_ESTOREOVR		_SB_MAKEMASK1(49)#define M_BCM1480_HSP_RX_DIAGDET_SPI4_INTOVR		_SB_MAKEMASK1(51)#define S_BCM1480_HSP_RX_DIAGDET_STATUS     32#define M_BCM1480_HSP_RX_DIAGDET_STATUS     _SB_MAKEMASK(20,S_BCM1480_HSP_RX_DIAGDET_STATUS)#define V_BCM1480_HSP_RX_DIAGDET_STATUS(x)  _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_DIAGDET_STATUS)#define G_BCM1480_HSP_RX_DIAGDET_STATUS(x)  _SB_GETVALUE(x,S_BCM1480_HSP_RX_DIAGDET_STATUS,M_BCM1480_HSP_RX_DIAGDET_STATUS)#define S_BCM1480_HSP_RX_DIAGDET_PUSHPOP_DISTANCE     56#define M_BCM1480_HSP_RX_DIAGDET_PUSHPOP_DISTANCE     _SB_MAKEMASK(4,S_BCM1480_HSP_RX_DIAGDET_PUSHPOP_DISTANCE)#define V_BCM1480_HSP_RX_DIAGDET_PUSHPOP_DISTANCE(x)  _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_DIAGDET_PUSHPOP_DISTANCE)#define G_BCM1480_HSP_RX_DIAGDET_PUSHPOP_DISTANCE(x)  _SB_GETVALUE(x,S_BCM1480_HSP_RX_DIAGDET_PUSHPOP_DISTANCE,M_BCM1480_HSP_RX_DIAGDET_PUSHPOP_DISTANCE)#define S_BCM1480_HSP_RX_DIAGDET_ESTORE_DISTANCE     60#define M_BCM1480_HSP_RX_DIAGDET_ESTORE_DISTANCE     _SB_MAKEMASK(4,S_BCM1480_HSP_RX_DIAGDET_ESTORE_DISTANCE)#define V_BCM1480_HSP_RX_DIAGDET_ESTORE_DISTANCE(x)  _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_DIAGDET_ESTORE_DISTANCE)#define G_BCM1480_HSP_RX_DIAGDET_ESTORE_DISTANCE(x)  _SB_GETVALUE(x,S_BCM1480_HSP_RX_DIAGDET_ESTORE_DISTANCE,M_BCM1480_HSP_RX_DIAGDET_ESTORE_DISTANCE)/* * TX SPI4 Interrupt Enable and Interrupt Status (Table 346, 347) */#define M_BCM1480_HSP_TX_INT_TSTATTIMEOUT	_SB_MAKEMASK1(0)#define M_BCM1480_HSP_TX_INT_DIP2RXERR		_SB_MAKEMASK1(1)#define M_BCM1480_HSP_TX_INT_SPI4RESET		_SB_MAKEMASK1(2)/* * RX Packet Buffer Allocation Registers (Table 349) *//* * XXX Depending on the revision of the manual, the fields may look *     incorrect here.  Check the errata for the correct layout *     of this register. */#define S_BCM1480_HSP_RX_RAMCEILING_0       0#define M_BCM1480_HSP_RX_RAMCEILING_0       _SB_MAKEMASK(10,S_BCM1480_HSP_RX_RAMCEILING_0)#define V_BCM1480_HSP_RX_RAMCEILING_0(x)    _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_RAMCEILING_0)#define G_BCM1480_HSP_RX_RAMCEILING_0(x)    _SB_GETVALUE(x,S_BCM1480_HSP_RX_RAMCEILING_0,M_BCM1480_HSP_RX_RAMCEILING_0)#define S_BCM1480_HSP_RX_RAMFLOOR_0         16#define M_BCM1480_HSP_RX_RAMFLOOR_0         _SB_MAKEMASK(10,S_BCM1480_HSP_RX_RAMFLOOR_0)#define V_BCM1480_HSP_RX_RAMFLOOR_0(x)      _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_RAMFLOOR_0)#define G_BCM1480_HSP_RX_RAMFLOOR_0(x)      _SB_GETVALUE(x,S_BCM1480_HSP_RX_RAMFLOOR_0,M_BCM1480_HSP_RX_RAMFLOOR_0)#define S_BCM1480_HSP_RX_RAMCEILING_1       32#define M_BCM1480_HSP_RX_RAMCEILING_1       _SB_MAKEMASK(10,S_BCM1480_HSP_RX_RAMCEILING_1)#define V_BCM1480_HSP_RX_RAMCEILING_1(x)    _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_RAMCEILING_1)#define G_BCM1480_HSP_RX_RAMCEILING_1(x)    _SB_GETVALUE(x,S_BCM1480_HSP_RX_RAMCEILING_1,M_BCM1480_HSP_RX_RAMCEILING_1)#define S_BCM1480_HSP_RX_RAMFLOOR_1         48#define M_BCM1480_HSP_RX_RAMFLOOR_1         _SB_MAKEMASK(10,S_BCM1480_HSP_RX_RAMFLOOR_1)#define V_BCM1480_HSP_RX_RAMFLOOR_1(x)      _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_RAMFLOOR_1)#define G_BCM1480_HSP_RX_RAMFLOOR_1(x)      _SB_GETVALUE(x,S_BCM1480_HSP_RX_RAMFLOOR_1,M_BCM1480_HSP_RX_RAMFLOOR_1)/* * RX HT RAM Allocation Register 0 (Table 350 + Errata) */#define S_BCM1480_HSP_RX_NPC_CMD_CEILING    0#define M_BCM1480_HSP_RX_NPC_CMD_CEILING    _SB_MAKEMASK(10,S_BCM1480_HSP_RX_NPC_CMD_CEILING)#define V_BCM1480_HSP_RX_NPC_CMD_CEILING(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_NPC_CMD_CEILING)#define G_BCM1480_HSP_RX_NPC_CMD_CEILING(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_NPC_CMD_CEILING,M_BCM1480_HSP_RX_NPC_CMD_CEILING)#define S_BCM1480_HSP_RX_NPC_CMD_FLOOR      16#define M_BCM1480_HSP_RX_NPC_CMD_FLOOR      _SB_MAKEMASK(10,S_BCM1480_HSP_RX_NPC_CMD_FLOOR)#define V_BCM1480_HSP_RX_NPC_CMD_FLOOR(x)   _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_NPC_CMD_FLOOR)#define G_BCM1480_HSP_RX_NPC_CMD_FLOOR(x)   _SB_GETVALUE(x,S_BCM1480_HSP_RX_NPC_CMD_FLOOR,M_BCM1480_HSP_RX_NPC_CMD_FLOOR)/* * RX HT RAM Allocation Register 1 (Table 351 + Errata) */#define S_BCM1480_HSP_RX_PC_CMD_CEILING     0#define M_BCM1480_HSP_RX_PC_CMD_CEILING     _SB_MAKEMASK(10,S_BCM1480_HSP_RX_PC_CMD_CEILING)#define V_BCM1480_HSP_RX_PC_CMD_CEILING(x)  _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_PC_CMD_CEILING)#define G_BCM1480_HSP_RX_PC_CMD_CEILING(x)  _SB_GETVALUE(x,S_BCM1480_HSP_RX_PC_CMD_CEILING,M_BCM1480_HSP_RX_PC_CMD_CEILING)#define S_BCM1480_HSP_RX_PC_CMD_FLOOR       16#define M_BCM1480_HSP_RX_PC_CMD_FLOOR       _SB_MAKEMASK(10,S_BCM1480_HSP_RX_PC_CMD_FLOOR)#define V_BCM1480_HSP_RX_PC_CMD_FLOOR(x)    _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_PC_CMD_FLOOR)#define G_BCM1480_HSP_RX_PC_CMD_FLOOR(x)    _SB_GETVALUE(x,S_BCM1480_HSP_RX_PC_CMD_FLOOR,M_BCM1480_HSP_RX_PC_CMD_FLOOR)#define S_BCM1480_HSP_RX_PRB_CEILING        32#define M_BCM1480_HSP_RX_PRB_CEILING        _SB_MAKEMASK(10,S_BCM1480_HSP_RX_PRB_CEILING)#define V_BCM1480_HSP_RX_PRB_CEILING(x)     _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_PRB_CEILING)#define G_BCM1480_HSP_RX_PRB_CEILING(x)     _SB_GETVALUE(x,S_BCM1480_HSP_RX_PRB_CEILING,M_BCM1480_HSP_RX_PRB_CEILING)#define S_BCM1480_HSP_RX_PRB_FLOOR          48#define M_BCM1480_HSP_RX_PRB_FLOOR          _SB_MAKEMASK(10,S_BCM1480_HSP_RX_PRB_FLOOR)#define V_BCM1480_HSP_RX_PRB_FLOOR(x)       _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_PRB_FLOOR)#define G_BCM1480_HSP_RX_PRB_FLOOR(x)       _SB_GETVALUE(x,S_BCM1480_HSP_RX_PRB_FLOOR,M_BCM1480_HSP_RX_PRB_FLOOR)/* * RX HT RAM Allocation Register 2 (Table 352 + Errata) */#define S_BCM1480_HSP_RX_ACK_CEILING        0#define M_BCM1480_HSP_RX_ACK_CEILING        _SB_MAKEMASK(10,S_BCM1480_HSP_RX_ACK_CEILING)#define V_BCM1480_HSP_RX_ACK_CEILING(x)     _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_ACK_CEILING)#define G_BCM1480_HSP_RX_ACK_CEILING(x)     _SB_GETVALUE(x,S_BCM1480_HSP_RX_ACK_CEILING,M_BCM1480_HSP_RX_ACK_CEILING)#define S_BCM1480_HSP_RX_ACK_FLOOR          16#define M_BCM1480_HSP_RX_ACK_FLOOR          _SB_MAKEMASK(10,S_BCM1480_HSP_RX_ACK_FLOOR)#define V_BCM1480_HSP_RX_ACK_FLOOR(x)       _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_ACK_FLOOR)#define G_BCM1480_HSP_RX_ACK_FLOOR(x)       _SB_GETVALUE(x,S_BCM1480_HSP_RX_ACK_FLOOR,M_BCM1480_HSP_RX_ACK_FLOOR)#define S_BCM1480_HSP_RX_WB_CEILING         32#define M_BCM1480_HSP_RX_WB_CEILING         _SB_MAKEMASK(10,S_BCM1480_HSP_RX_WB_CEILING)#define V_BCM1480_HSP_RX_WB_CEILING(x)      _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_WB_CEILING)#define G_BCM1480_HSP_RX_WB_CEILING(x)      _SB_GETVALUE(x,S_BCM1480_HSP_RX_WB_CEILING,M_BCM1480_HSP_RX_WB_CEILING)#define S_BCM1480_HSP_RX_WB_FLOOR           48#define M_BCM1480_HSP_RX_WB_FLOOR           _SB_MAKEMASK(10,S_BCM1480_HSP_RX_WB_FLOOR)#define V_BCM1480_HSP_RX_WB_FLOOR(x)        _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_WB_FLOOR)#define G_BCM1480_HSP_RX_WB_FLOOR(x)        _SB_GETVALUE(x,S_BCM1480_HSP_RX_WB_FLOOR,M_BCM1480_HSP_RX_WB_FLOOR)/* * RX HT RAM Allocation Register 3 (Table 353 + Errata) */#define S_BCM1480_HSP_RX_CFILL_CEILING      0#define M_BCM1480_HSP_RX_CFILL_CEILING      _SB_MAKEMASK(10,S_BCM1480_HSP_RX_CFILL_CEILING)#define V_BCM1480_HSP_RX_CFILL_CEILING(x)   _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_CFILL_CEILING)#define G_BCM1480_HSP_RX_CFILL_CEILING(x)   _SB_GETVALUE(x,S_BCM1480_HSP_RX_CFILL_CEILING,M_BCM1480_HSP_RX_CFILL_CEILING)#define S_BCM1480_HSP_RX_CFILL_FLOOR        16#define M_BCM1480_HSP_RX_CFILL_FLOOR        _SB_MAKEMASK(10,S_BCM1480_HSP_RX_CFILL_FLOOR)#define V_BCM1480_HSP_RX_CFILL_FLOOR(x)     _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_CFILL_FLOOR)#define G_BCM1480_HSP_RX_CFILL_FLOOR(x)     _SB_GETVALUE(x,S_BCM1480_HSP_RX_CFILL_FLOOR,M_BCM1480_HSP_RX_CFILL_FLOOR)#define S_BCM1480_HSP_RX_CRD_CEILING        32#define M_BCM1480_HSP_RX_CRD_CEILING        _SB_MAKEMASK(10,S_BCM1480_HSP_RX_CRD_CEILING)#define V_BCM1480_HSP_RX_CRD_CEILING(x)     _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_CRD_CEILING)#define G_BCM1480_HSP_RX_CRD_CEILING(x)     _SB_GETVALUE(x,S_BCM1480_HSP_RX_CRD_CEILING,M_BCM1480_HSP_RX_CRD_CEILING)#define S_BCM1480_HSP_RX_CRD_FLOOR          48#define M_BCM1480_HSP_RX_CRD_FLOOR          _SB_MAKEMASK(10,S_BCM1480_HSP_RX_CRD_FLOOR)#define V_BCM1480_HSP_RX_CRD_FLOOR(x)       _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_CRD_FLOOR)#define G_BCM1480_HSP_RX_CRD_FLOOR(x)       _SB_GETVALUE(x,S_BCM1480_HSP_RX_CRD_FLOOR,M_BCM1480_HSP_RX_CRD_FLOOR)/* * RX HT RAM Allocation Register 4 (Table 354 + Errata) */#define S_BCM1480_HSP_RX_NPC_DAT_CEILING    0#define M_BCM1480_HSP_RX_NPC_DAT_CEILING    _SB_MAKEMASK(10,S_BCM1480_HSP_RX_NPC_DAT_CEILING)#define V_BCM1480_HSP_RX_NPC_DAT_CEILING(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_NPC_DAT_CEILING)#define G_BCM1480_HSP_RX_NPC_DAT_CEILING(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_NPC_DAT_CEILING,M_BCM1480_HSP_RX_NPC_DAT_CEILING)#define S_BCM1480_HSP_RX_NPC_DAT_FLOOR      16#define M_BCM1480_HSP_RX_NPC_DAT_FLOOR      _SB_MAKEMASK(10,S_BCM1480_HSP_RX_NPC_DAT_FLOOR)#define V_BCM1480_HSP_RX_NPC_DAT_FLOOR(x)   _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_NPC_DAT_FLOOR)#define G_BCM1480_HSP_RX_NPC_DAT_FLOOR(x)   _SB_GETVALUE(x,S_BCM1480_HSP_RX_NPC_DAT_FLOOR,M_BCM1480_HSP_RX_NPC_DAT_FLOOR)#define S_BCM1480_HSP_RX_RSP_DAT_CEILING    32#define M_BCM1480_HSP_RX_RSP_DAT_CEILING    _SB_MAKEMASK(10,S_BCM1480_HSP_RX_RSP_DAT_CEILING)#define V_BCM1480_HSP_RX_RSP_DAT_CEILING(x) _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_RSP_DAT_CEILING)#define G_BCM1480_HSP_RX_RSP_DAT_CEILING(x) _SB_GETVALUE(x,S_BCM1480_HSP_RX_RSP_DAT_CEILING,M_BCM1480_HSP_RX_RSP_DAT_CEILING)#define S_BCM1480_HSP_RX_RSP_DAT_FLOOR      48#define M_BCM1480_HSP_RX_RSP_DAT_FLOOR      _SB_MAKEMASK(10,S_BCM1480_HSP_RX_RSP_DAT_FLOOR)#define V_BCM1480_HSP_RX_RSP_DAT_FLOOR(x)   _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_RSP_DAT_FLOOR)#define G_BCM1480_HSP_RX_RSP_DAT_FLOOR(x)   _SB_GETVALUE(x,S_BCM1480_HSP_RX_RSP_DAT_FLOOR,M_BCM1480_HSP_RX_RSP_DAT_FLOOR)/* * RX HT RAM Allocation Register 5 (Table 355 + Errata) */#define S_BCM1480_HSP_RX_PC_DAT_CEILING     0#define M_BCM1480_HSP_RX_PC_DAT_CEILING     _SB_MAKEMASK(10,S_BCM1480_HSP_RX_PC_DAT_CEILING)#define V_BCM1480_HSP_RX_PC_DAT_CEILING(x)  _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_PC_DAT_CEILING)#define G_BCM1480_HSP_RX_PC_DAT_CEILING(x)  _SB_GETVALUE(x,S_BCM1480_HSP_RX_PC_DAT_CEILING,M_BCM1480_HSP_RX_PC_DAT_CEILING)#define S_BCM1480_HSP_RX_PC_DAT_FLOOR       16#define M_BCM1480_HSP_RX_PC_DAT_FLOOR       _SB_MAKEMASK(10,S_BCM1480_HSP_RX_PC_DAT_FLOOR)#define V_BCM1480_HSP_RX_PC_DAT_FLOOR(x)    _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_PC_DAT_FLOOR)#define G_BCM1480_HSP_RX_PC_DAT_FLOOR(x)    _SB_GETVALUE(x,S_BCM1480_HSP_RX_PC_DAT_FLOOR,M_BCM1480_HSP_RX_PC_DAT_FLOOR)/* ... *//* * TX Packet Buffer Allocation Registers (Table 356) */#define S_BCM1480_HSP_TX_RAMCEILING_0       0#define M_BCM1480_HSP_TX_RAMCEILING_0       _SB_MAKEMASK(8,S_BCM1480_HSP_TX_RAMCEILING_0)#define V_BCM1480_HSP_TX_RAMCEILING_0(x)    _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_RAMCEILING_0)#define G_BCM1480_HSP_TX_RAMCEILING_0(x)    _SB_GETVALUE(x,S_BCM1480_HSP_TX_RAMCEILING_0,M_BCM1480_HSP_TX_RAMCEILING_0)#define S_BCM1480_HSP_TX_RAMFLOOR_0         16#define M_BCM1480_HSP_TX_RAMFLOOR_0         _SB_MAKEMASK(8,S_BCM1480_HSP_TX_RAMFLOOR_0)#define V_BCM1480_HSP_TX_RAMFLOOR_0(x)      _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_RAMFLOOR_0)#define G_BCM1480_HSP_TX_RAMFLOOR_0(x)      _SB_GETVALUE(x,S_BCM1480_HSP_TX_RAMFLOOR_0,M_BCM1480_HSP_TX_RAMFLOOR_0)#define S_BCM1480_HSP_TX_RAMCEILING_1       32#define M_BCM1480_HSP_TX_RAMCEILING_1       _SB_MAKEMASK(8,S_BCM1480_HSP_TX_RAMCEILING_1)#define V_BCM1480_HSP_TX_RAMCEILING_1(x)    _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_RAMCEILING_1)#define G_BCM1480_HSP_TX_RAMCEILING_1(x)    _SB_GETVALUE(x,S_BCM1480_HSP_TX_RAMCEILING_1,M_BCM1480_HSP_TX_RAMCEILING_1)#define S_BCM1480_HSP_TX_RAMFLOOR_1         48#define M_BCM1480_HSP_TX_RAMFLOOR_1         _SB_MAKEMASK(8,S_BCM1480_HSP_TX_RAMFLOOR_1)#define V_BCM1480_HSP_TX_RAMFLOOR_1(x)      _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_RAMFLOOR_1)#define G_BCM1480_HSP_TX_RAMFLOOR_1(x)      _SB_GETVALUE(x,S_BCM1480_HSP_TX_RAMFLOOR_1,M_BCM1480_HSP_TX_RAMFLOOR_1)/* * TX Non-Posted Command (NPC) Allocation Register (Table 357) */#define S_BCM1480_HSP_TX_NPC_CEILING        0#define M_BCM1480_HSP_TX_NPC_CEILING        _SB_MAKEMASK(8,S_BCM1480_HSP_TX_NPC_CEILING)#define V_BCM1480_HSP_TX_NPC_CEILING(x)     _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_NPC_CEILING)#define G_BCM1480_HSP_TX_NPC_CEILING(x)     _SB_GETVALUE(x,S_BCM1480_HSP_TX_NPC_CEILING,M_BCM1480_HSP_TX_NPC_CEILING)#define S_BCM1480_HSP_TX_NPC_FLOOR          16#define M_BCM1480_HSP_TX_NPC_FLOOR          _SB_MAKEMASK(8,S_BCM1480_HSP_TX_NPC_FLOOR)#define V_BCM1480_HSP_TX_NPC_FLOOR(x)       _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_NPC_FLOOR)#define G_BCM1480_HSP_TX_NPC_FLOOR(x)       _SB_GETVALUE(x,S_BCM1480_HSP_TX_NPC_FLOOR,M_BCM1480_HSP_TX_NPC_FLOOR)/* * TX Response (RSP) Allocation Register (Table 358) */#define S_BCM1480_HSP_TX_RSP_CEILING        0#define M_BCM1480_HSP_TX_RSP_CEILING        _SB_MAKEMASK(8,S_BCM1480_HSP_TX_RSP_CEILING)#define V_BCM1480_HSP_TX_RSP_CEILING(x)     _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_RSP_CEILING)#define G_BCM1480_HSP_TX_RSP_CEILING(x)     _SB_GETVALUE(x,S_BCM1480_HSP_TX_RSP_CEILING,M_BCM1480_HSP_TX_RSP_CEILING)#define S_BCM1480_HSP_TX_RSP_FLOOR          16#define M_BCM1480_HSP_TX_RSP_FLOOR          _SB_MAKEMASK(8,S_BCM1480_HSP_TX_RSP_FLOOR)#define V_BCM1480_HSP_TX_RSP_FLOOR(x)       _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_RSP_FLOOR)#define G_BCM1480_HSP_TX_RSP_FLOOR(x)       _SB_GETVALUE(x,S_BCM1480_HSP_TX_RSP_FLOOR,M_BCM1480_HSP_TX_RSP_FLOOR)/* * TX Posted Command (PC) Allocation Register (Table 359) */#define S_BCM1480_HSP_TX_PC_CEILING         0#define M_BCM1480_HSP_TX_PC_CEILING         _SB_MAKEMASK(8,S_BCM1480_HSP_TX_PC_CEILING)#define V_BCM1480_HSP_TX_PC_CEILING(x)      _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_PC_CEILING)#define G_BCM1480_HSP_TX_PC_CEILING(x)      _SB_GETVALUE(x,S_BCM1480_HSP_TX_PC_CEILING,M_BCM1480_HSP_TX_PC_CEILING)#define S_BCM1480_HSP_TX_PC_FLOOR           16#define M_BCM1480_HSP_TX_PC_FLOOR           _SB_MAKEMASK(8,S_BCM1480_HSP_TX_PC_FLOOR)#define V_BCM1480_HSP_TX_PC_FLOOR(x)        _SB_MAKEVALUE(x,S_BCM1480_HSP_TX_PC_FLOOR)#define G_BCM1480_HSP_TX_PC_FLOOR(x)        _SB_GETVALUE(x,S_BCM1480_HSP_TX_PC_FLOOR,M_BCM1480_HSP_TX_PC_FLOOR)/* ... *//* XXX TBD:  Tables 360, 361, 362 *//*  * RX SPI4 Config Register 1 (Table 363)  */#define S_BCM1480_HSP_RX_CALENDAR_LEN           0#define M_BCM1480_HSP_RX_CALENDAR_LEN           _SB_MAKEMASK(8,S_BCM1480_HSP_RX_CALENDAR_LEN)#define V_BCM1480_HSP_RX_CALENDAR_LEN(x)        _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_CALENDAR_LEN)#define G_BCM1480_HSP_RX_CALENDAR_LEN(x)        _SB_GETVALUE(x,S_BCM1480_HSP_RX_CALENDAR_LEN,M_BCM1480_HSP_RX_CALENDAR_LEN)#define S_BCM1480_HSP_RX_CALENDAR_M           16#define M_BCM1480_HSP_RX_CALENDAR_M           _SB_MAKEMASK(8,S_BCM1480_HSP_RX_CALENDAR_M)#define V_BCM1480_HSP_RX_CALENDAR_M(x)        _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_CALENDAR_M)#define G_BCM1480_HSP_RX_CALENDAR_M(x)        _SB_GETVALUE(x,S_BCM1480_HSP_RX_CALENDAR_M,M_BCM1480_HSP_RX_CALENDAR_M)#define S_BCM1480_HSP_RX_ALPHA           40#define M_BCM1480_HSP_RX_ALPHA           _SB_MAKEMASK(12,S_BCM1480_HSP_RX_ALPHA)#define V_BCM1480_HSP_RX_ALPHA(x)        _SB_MAKEVALUE(x,S_BCM1480_HSP_RX_ALPHA)
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