sbmips.h

一个很好的嵌入式linux平台下的bootloader

#define V_SR_KSU(x)	_MM_MAKEVALUE(x,S_SR_KSU)
#define G_SR_KSU(x)	_MM_GETVALUE(x,S_SR_KSU,M_SR_KSU)
#define K_SR_KSU_KERNEL	0
#define K_SR_KSU_SUPR	1
#define K_SR_KSU_USER	2

#define M_SR_UM		_MM_MAKEMASK1(4)

#define S_SR_ERL	2
#define M_SR_ERL	_MM_MAKEMASK1(2)
#define G_SR_ERL(x)	_MM_GETVALUE(x,S_SR_ERL,M_SR_ERL)

#define S_SR_EXL	1
#define M_SR_EXL	_MM_MAKEMASK1(1)
#define G_SR_EXL(x)	_MM_GETVALUE(x,S_SR_EXL,M_SR_EXL)

#define S_SR_IE		0
#define M_SR_IE		_MM_MAKEMASK1(0)
#define G_SR_IE(x)	_MM_GETVALUE(x,S_SR_IE,M_SR_IE)

/* 
 * Cause Register 
 */
#define M_CAUSE_BD	_MM_MAKEMASK1(31) /* exception in BD slot */

#define S_CAUSE_CE	28		/* coprocessor error */
#define M_CAUSE_CE	_MM_MAKEMASK(2,S_CAUSE_CE)
#define V_CAUSE_CE(x)	_MM_MAKEVALUE(x,S_CAUSE_CE)
#define G_CAUSE_CE(x)	_MM_GETVALUE(x,S_CAUSE_CE,M_CAUSE_CE)

#define M_CAUSE_IV	_MM_MAKEMASK1(23) /* special interrupt */
#define M_CAUSE_WP      _MM_MAKEMASK1(22) /* watch interrupt deferred */

#define S_CAUSE_IPMASK	8
#define M_CAUSE_IPMASK	_MM_MAKEMASK(8,S_CAUSE_IPMASK)
#define M_CAUSE_IP8	_MM_MAKEMASK1(15)	/* hardware interrupts */
#define M_CAUSE_IP7	_MM_MAKEMASK1(14)
#define M_CAUSE_IP6	_MM_MAKEMASK1(13)
#define M_CAUSE_IP5	_MM_MAKEMASK1(12)
#define M_CAUSE_IP4	_MM_MAKEMASK1(11)
#define M_CAUSE_IP3	_MM_MAKEMASK1(10)
#define M_CAUSE_SW2	_MM_MAKEMASK1(9)	/* software interrupts */
#define M_CAUSE_SW1	_MM_MAKEMASK1(8)

#define S_CAUSE_EXC	2
#define M_CAUSE_EXC	_MM_MAKEMASK(5,S_CAUSE_EXC)
#define V_CAUSE_EXC(x)	_MM_MAKEVALUE(x,S_CAUSE_EXC)
#define G_CAUSE_EXC(x)	_MM_GETVALUE(x,S_CAUSE_EXC,M_CAUSE_EXC)

/* Exception Code */
#define K_CAUSE_EXC_INT		0	/* External interrupt */
#define K_CAUSE_EXC_MOD		1	/* TLB modification */
#define K_CAUSE_EXC_TLBL	2    	/* TLB miss (Load or Ifetch) */
#define K_CAUSE_EXC_TLBS	3	/* TLB miss (Save) */
#define K_CAUSE_EXC_ADEL	4    	/* Address error (Load or Ifetch) */
#define K_CAUSE_EXC_ADES	5	/* Address error (Save) */
#define K_CAUSE_EXC_IBE		6	/* Bus error (Ifetch) */
#define K_CAUSE_EXC_DBE		7	/* Bus error (data load or store) */
#define K_CAUSE_EXC_SYS		8	/* System call */
#define K_CAUSE_EXC_BP		9	/* Break point */
#define K_CAUSE_EXC_RI		10	/* Reserved instruction */
#define K_CAUSE_EXC_CPU		11	/* Coprocessor unusable */
#define K_CAUSE_EXC_OVF		12	/* Arithmetic overflow */
#define K_CAUSE_EXC_TRAP	13	/* Trap exception */
#define K_CAUSE_EXC_VCEI	14	/* Virtual Coherency Exception (I) */
#define K_CAUSE_EXC_FPE		15	/* Floating Point Exception */
#define K_CAUSE_EXC_CP2		16	/* Cp2 Exception */
#define K_CAUSE_EXC_WATCH	23	/* Watchpoint exception */
#define K_CAUSE_EXC_VCED	31	/* Virtual Coherency Exception (D) */

#define	K_NTLBENTRIES	64

#define HI_HALF(x)	((x) >> 16)
#define LO_HALF(x)	((x) & 0xffff)

/* FPU stuff */

#if defined(__ASSEMBLER__)
#define C1_CSR		$31
#define C1_FRID		$0
#else
#define C1_CSR		31
#define C1_FRID		0
#endif

#define S_FCSR_CAUSE	12
#define M_FCSR_CAUSE	_MM_MAKEMASK(5,S_FCSR_CAUSE)
#define V_FCSR_CAUSE(x)	_MM_MAKEVALUE(x,S_FCSR_CAUSE)
#define G_FCSR_CAUSE(x)	_MM_GETVALUE(x,S_FCSR_CAUSE,M_FCSR_CAUSE)

#define S_FCSR_ENABLES	7
#define M_FCSR_ENABLES	_MM_MAKEMASK(5,S_FCSR_ENABLES)
#define V_FCSR_ENABLES(x) _MM_MAKEVALUE(x,S_FCSR_ENABLES)
#define G_FCSR_ENABLES(x) _MM_GETVALUE(x,S_FCSR_ENABLES,M_FCSR_ENABLES)

#define S_FCSR_FLAGS	2
#define M_FCSR_FLAGS	_MM_MAKEMASK(5,S_FCSR_FLAGS)
#define V_FCSR_FLAGS(x)	_MM_MAKEVALUE(x,S_FCSR_FLAGS)
#define G_FCSR_FLAGS(x)	_MM_GETVALUE(x,S_FCSR_FLAGS,M_FCSR_FLAGS)


/*
 * MIPS64 Config Register (select 0)
 */
#define S_CFG_CFG1	31			/* Config1 */
#define M_CFG_CFG1	_MM_MAKEMASK1(31)	/* config1 select1 is impl */
#define G_CFG_CFG1(x)	_MM_GETVALUE(x,S_CFG_CFG1,M_CFG_CFG1)

#define S_CFG_MK1	21			/* Map KSEG1, SB-1 rev3+ */
#define M_CFG_MK1        _MM_MAKEMASK1(S_CFG_MK1)
#define V_CFG_MK1(x)	_MM_MAKEVALUE(x,S_CFG_MK1)
#define G_CFG_MK1(x)	_MM_GETVALUE(x,S_CFG_MK1,M_CFG_MK1)

#define S_CFG_MK0	20			/* Map KSEG0, SB-1 rev3+ */
#define M_CFG_MK0        _MM_MAKEMASK1(S_CFG_MK0)
#define V_CFG_MK0(x)	_MM_MAKEVALUE(x,S_CFG_MK0)
#define G_CFG_MK0(x)	_MM_GETVALUE(x,S_CFG_MK0,M_CFG_MK0)

#define S_CFG_MPV	16			/* Multi proc. vector offset */
#define M_CFG_MPV        _MM_MAKEMASK(4,S_CFG_MPV)
#define V_CFG_MPV(x)	_MM_MAKEVALUE(x,S_CFG_MPV)
#define G_CFG_MPV(x)	_MM_GETVALUE(x,S_CFG_MPV,M_CFG_MPV)

#define S_CFG_BE	15			/* Endian mode */
#define M_CFG_BE        _MM_MAKEMASK1(15)	/* big-endian mode */
#define G_CFG_BE(x)	_MM_GETVALUE(x,S_CFG_BE,M_CFG_BE)

#define S_CFG_AT	13			/* Architecture Type */
#define M_CFG_AT	_MM_MAKEMASK(2,S_CFG_AT)
#define V_CFG_AT(x)	_MM_MAKEVALUE(x,S_CFG_AT)
#define G_CFG_AT(x)	_MM_GETVALUE(x,S_CFG_AT,M_CFG_AT)
#define K_CFG_AT_MIPS32	0
#define K_CFG_AT_MIPS64_32 1
#define K_CFG_AT_MIPS64	2

#define S_CFG_AR	10			/* Architecture Revision */
#define M_CFG_AR        _MM_MAKEMASK(3,S_CFG_AR)
#define V_CFG_AR(x)	_MM_MAKEVALUE(x,S_CFG_AR)
#define G_CFG_AR(x)	_MM_GETVALUE(x,S_CFG_AR,M_CFG_AR)
#define K_CFG_AR_REV1	0

#define S_CFG_MMU	7			/* MMU Type */
#define M_CFG_MMU       _MM_MAKEMASK(3,S_CFG_MMU)
#define V_CFG_MMU(x)	_MM_MAKEVALUE(x,S_CFG_MMU)
#define G_CFG_MMU(x)	_MM_GETVALUE(x,S_CFG_MMU,M_CFG_MMU)
#define K_CFG_MMU_NONE	0
#define K_CFG_MMU_TLB	1
#define K_CFG_MMU_BAT	2
#define K_CFG_MMU_FIXED	3

#define S_CFG_K0COH	0			/* K0seg coherency */
#define M_CFG_K0COH	_MM_MAKEMASK(3,S_CFG_K0COH)
#define V_CFG_K0COH(x)	_MM_MAKEVALUE(x,S_CFG_K0COH)
#define G_CFG_K0COH(x)	_MM_GETVALUE(x,S_CFG_K0COH,M_CFG_K0COH)
#define K_CFG_K0COH_UNCACHED	2
#define K_CFG_K0COH_CACHEABLE	3
#define K_CFG_K0COH_COHERENT	5

/*
 * MIPS64 Config Register (select 1)
 */

#define M_CFG_CFG2	_MM_MAKEMASK1(31)	/* config2 select2 is impl */

#define S_CFG_MMUSIZE	25
#define M_CFG_MMUSIZE	_MM_MAKEMASK(6,S_CFG_MMUSIZE)
#define G_CFG_MMUSIZE(x) _MM_GETVALUE(x,S_CFG_MMUSIZE,M_CFG_MMUSIZE)

#define S_CFG_IS	22
#define M_CFG_IS	_MM_MAKEMASK(3,S_CFG_IS)
#define V_CFG_IS(x)	_MM_MAKEVALUE(x,S_CFG_IS)
#define G_CFG_IS(x)	_MM_GETVALUE(x,S_CFG_IS,M_CFG_IS)

#define S_CFG_IL	19
#define M_CFG_IL	_MM_MAKEMASK(3,S_CFG_IL)
#define V_CFG_IL(x)	_MM_MAKEVALUE(x,S_CFG_IL)
#define G_CFG_IL(x)	_MM_GETVALUE(x,S_CFG_IL,M_CFG_IL)

#define S_CFG_IA	16
#define M_CFG_IA	_MM_MAKEMASK(3,S_CFG_IA)
#define V_CFG_IA(x)	_MM_MAKEVALUE(x,S_CFG_IA)
#define G_CFG_IA(x)	_MM_GETVALUE(x,S_CFG_IA,M_CFG_IA)

#define S_CFG_DS	13
#define M_CFG_DS	_MM_MAKEMASK(3,S_CFG_DS)
#define V_CFG_DS(x)	_MM_MAKEVALUE(x,S_CFG_DS)
#define G_CFG_DS(x)	_MM_GETVALUE(x,S_CFG_DS,M_CFG_DS)

#define S_CFG_DL	10
#define M_CFG_DL	_MM_MAKEMASK(3,S_CFG_DL)
#define V_CFG_DL(x)	_MM_MAKEVALUE(x,S_CFG_DL)
#define G_CFG_DL(x)	_MM_GETVALUE(x,S_CFG_DL,M_CFG_DL)

#define S_CFG_DA	7
#define M_CFG_DA	_MM_MAKEMASK(3,S_CFG_DA)
#define V_CFG_DA(x)	_MM_MAKEVALUE(x,S_CFG_DA)
#define G_CFG_DA(x)	_MM_GETVALUE(x,S_CFG_DA,M_CFG_DA)

#define S_CFG_PC	4			/* perf ctrs present */
#define M_CFG_PC	_MM_MAKEMASK1(4)	/* perf ctrs present */
#define G_CFG_PC(x)	_MM_GETVALUE(x,S_CFG_PC,M_CFG_PC)

#define S_CFG_WR	3			/* watch regs present */
#define M_CFG_WR	_MM_MAKEMASK1(3)	/* watch regs present */
#define G_CFG_WR(x)	_MM_GETVALUE(x,S_CFG_WR,M_CFG_WR)

#define S_CFG_CA	2			/* MIPS16 present */
#define M_CFG_CA	_MM_MAKEMASK1(2)	/* MIPS16 present */
#define G_CFG_CA(x)	_MM_GETVALUE(x,S_CFG_CA,M_CFG_CA)

#define S_CFG_EP	1			/* EJTAG present */
#define M_CFG_EP	_MM_MAKEMASK1(1)	/* EJTAG present */
#define G_CFG_EP(x)	_MM_GETVALUE(x,S_CFG_EP,M_CFG_EP)

#define S_CFG_FP	0			/* FPU present */
#define M_CFG_FP	_MM_MAKEMASK1(0)	/* FPU present */
#define G_CFG_FP(x)	_MM_GETVALUE(x,S_CFG_FP,M_CFG_FP)



/* 
 * Primary Cache TagLo 
 */

#define S_TAGLO_PTAG	8
#define M_TAGLO_PTAG 	_MM_MAKEMASK(56,S_TAGLO_PTAG)

#define S_TAGLO_PSTATE	6
#define M_TAGLO_PSTATE	_MM_MAKEMASK(2,S_TAGLO_PSTATE)
#define V_TAGLO_PSTATE(x) _MM_MAKEVALUE(x,S_TAGLO_PSTATE)
#define G_TAGLO_PSTATE(x) _MM_GETVALUE(x,S_TAGLO_PSTATE,M_TAGLO_PSTATE)
#define K_TAGLO_PSTATE_INVAL		0
#define K_TAGLO_PSTATE_SHARED		1
#define K_TAGLO_PSTATE_CLEAN_EXCL	2
#define K_TAGLO_PSTATE_DIRTY_EXCL	3

#define M_TAGLO_LOCK	_MM_MAKEMASK1(5)
#define M_TAGLO_PARITY	_MM_MAKEMASK1(0)


/*
 * CP0 ErrCtl register
 */
#define M_ERRCTL_RECOVERABLE _MM_MAKEMASK1(31)
#define M_ERRCTL_DCACHE      _MM_MAKEMASK1(30)
#define M_ERRCTL_ICACHE      _MM_MAKEMASK1(29)
#define M_ERRCTL_MULTIBUS    _MM_MAKEMASK1(23)
#define M_ERRCTL_MC_TLB      _MM_MAKEMASK1(15)
#define M_ERRCTL_MC_TIMEOUT  _MM_MAKEMASK1(14)

/*
 * CP0 CacheErr-I register
 */
#define M_CERRI_TAG_PARITY   _MM_MAKEMASK1(29)
#define M_CERRI_DATA_PARITY  _MM_MAKEMASK1(28)
#define M_CERRI_EXTERNAL     _MM_MAKEMASK1(26)

/*
 * CP0 CacheErr-D register
 */
#define M_CERRD_MULTIPLE     _MM_MAKEMASK1(31)
#define M_CERRD_TAG_STATE    _MM_MAKEMASK1(30)
#define M_CERRD_TAG_ADDRESS  _MM_MAKEMASK1(29)
#define M_CERRD_DATA_SBE     _MM_MAKEMASK1(28)
#define M_CERRD_DATA_DBE     _MM_MAKEMASK1(27)
#define M_CERRD_EXTERNAL     _MM_MAKEMASK1(26)
#define M_CERRD_LOAD         _MM_MAKEMASK1(25)
#define M_CERRD_STORE        _MM_MAKEMASK1(24)
#define M_CERRD_FILLWB       _MM_MAKEMASK1(23)
#define M_CERRD_COHERENCY    _MM_MAKEMASK1(22)
#define M_CERRD_DUPTAG       _MM_MAKEMASK1(21)


/*
 * Primary Cache operations
 */
#define Index_Invalidate_I               0x0         /* 0       0 */
#define Index_Writeback_Inv_D            0x1         /* 0       1 */
#define Index_Invalidate_SI              0x2         /* 0       2 */
#define Index_Writeback_Inv_SD           0x3         /* 0       3 */
#define Index_Load_Tag_I                 0x4         /* 1       0 */
#define Index_Load_Tag_D                 0x5         /* 1       1 */
#define Index_Load_Tag_SI                0x6         /* 1       2 */
#define Index_Load_Tag_SD                0x7         /* 1       3 */
#define Index_Store_Tag_I                0x8         /* 2       0 */
#define Index_Store_Tag_D                0x9         /* 2       1 */
#define Index_Store_Tag_SI               0xA         /* 2       2 */
#define Index_Store_Tag_SD               0xB         /* 2       3 */
#define Create_Dirty_Exc_D               0xD         /* 3       1 */
#define Create_Dirty_Exc_SD              0xF         /* 3       3 */
#define Hit_Invalidate_I                 0x10        /* 4       0 */
#define Hit_Invalidate_D                 0x11        /* 4       1 */
#define Hit_Invalidate_SI                0x12        /* 4       2 */
#define Hit_Invalidate_SD                0x13        /* 4       3 */
#define Fill_I                           0x14        /* 5       0 */
#define Hit_Writeback_Inv_D              0x15        /* 5       1 */
#define Hit_Writeback_Inv_SD             0x17        /* 5       3 */
#define Hit_Writeback_I                  0x18        /* 6       0 */
#define Hit_Writeback_D                  0x19        /* 6       1 */
#define Hit_Writeback_SD                 0x1B        /* 6       3 */
#define Hit_Set_Virtual_SI               0x1E        /* 7       2 */
#define Hit_Set_Virtual_SD               0x1F        /* 7       3 */

/* Watchpoint Register */
#define M_WATCH_PA		0xfffffff8
#define M_WATCH_R		0x00000002
#define M_WATCH_W		0x00000001


/* TLB entries */
#define S_TLBHI_ASID            0
#define M_TLBHI_ASID		_MM_MAKEMASK_64(8,S_TLBHI_ASID)
#define V_TLBHI_ASID(x) 	_MM_MAKEVALUE_64(x,S_TLBHI_ASID)
#define G_TLBHI_ASID(x) 	_MM_GETVALUE_64(x,S_TLBHI_ASID,M_TLBHI_ASID)

/* SEGBITS = 44 on sb1 */
#define S_TLBHI_VPN2		13
#define M_TLBHI_VPN2		_MM_MAKEMASK_64(31,S_TLBHI_VPN2)
#define V_TLBHI_VPN2(x) 	_MM_MAKEVALUE_64(x,S_TLBHI_VPN2)
#define G_TLBHI_VPN2(x) 	_MM_GETVALUE_64(x,S_TLBHI_VPN2,M_TLBHI_VPN2)

#define S_TLBLO_G		0
#define M_TLBLO_G		_MM_MAKEMASK1_64(S_TLBLO_G)
#define V_TLBLO_G(x) 	        _MM_MAKEVALUE_64(x,S_TLBLO_G)
#define G_TLBLO_G(x) 	        _MM_GETVALUE_64(x,S_TLBLO_G,M_TLBLO_G)

#define S_TLBLO_V		1
#define M_TLBLO_V		_MM_MAKEMASK1_64(S_TLBLO_V)
#define V_TLBLO_V(x) 	        _MM_MAKEVALUE_64(x,S_TLBLO_V)
#define G_TLBLO_V(x) 	        _MM_GETVALUE_64(x,S_TLBLO_V,M_TLBLO_V)

#define S_TLBLO_D		2
#define M_TLBLO_D		_MM_MAKEMASK1_64(S_TLBLO_D)
#define V_TLBLO_D(x) 	        _MM_MAKEVALUE_64(x,S_TLBLO_D)
#define G_TLBLO_D(x) 	        _MM_GETVALUE_64(x,S_TLBLO_D,M_TLBLO_D)

#define S_TLBLO_CALG		3
#define M_TLBLO_CALG		_MM_MAKEMASK_64(3,S_TLBLO_CALG)
#define V_TLBLO_CALG(x) 	_MM_MAKEVALUE_64(x,S_TLBLO_CALG)
#define G_TLBLO_CALG(x) 	_MM_GETVALUE_64(x,S_TLBLO_CALG,M_TLBLO_CALG)

/* PABITS = 40 on sb1 */
#define S_TLBLO_PFNMASK		6
#define M_TLBLO_PFNMASK		_MM_MAKEMASK_64(28,S_TLBLO_PFNMASK)
#define V_TLBLO_PFNMASK(x) 	_MM_MAKEVALUE_64(x,S_TLBLO_PFNMASK)
#define G_TLBLO_PFNMASK(x) 	_MM_GETVALUE_64(x,S_TLBLO_PFNMASK,M_TLBLO_PFNMASK)

/* support 4KB - 64MB for pass2 and beyond (14bits) */
#define S_TLB_PGMSK             13
#define M_TLB_PGMSK		_MM_MAKEMASK(14,S_TLB_PGMSK)
#define V_TLB_PGMSK(x) 	        _MM_MAKEVALUE(x,S_TLB_PGMSK)
#define G_TLB_PGMSK(x) 	        _MM_GETVALUE(x,S_TLB_PGMSK,M_TLB_PGMSK)

#define K_CALG_COH_EXCL1_NOL2	0
#define K_CALG_COH_SHRL1_NOL2	1
#define K_CALG_UNCACHED		2
#define K_CALG_NONCOHERENT	3
#define K_CALG_COH_EXCL		4
#define K_CALG_COH_SHAREABLE	5
#define K_CALG_NOTUSED		6
#define K_CALG_UNCACHED_ACCEL	7



#endif /* _SB_MIPS_H */