sbmips.h

一个很好的嵌入式linux平台下的bootloader

#define _cp0_set_reg_u64(name, num, sel) \
  _cp0_set_reg (name, (num), (sel), unsigned long long, "d")
#else
#define _cp0_get_reg_u64(name, num, sel)
#define _cp0_set_reg_u64(name, num, sel)
#endif

/* CP0 register 0: index. */
_cp0_get_reg_s32 (index, C0_INDEX, 0)
_cp0_set_reg_s32 (index, C0_INDEX, 0)

/* CP0 register 1: random. */
_cp0_get_reg_u32 (random, C0_RANDOM, 0)

/* CP0 register 2: entrylo0. */
_cp0_get_reg_u64 (entrylo0, C0_ENTRYLO0, 0)
_cp0_set_reg_u64 (entrylo0, C0_ENTRYLO0, 0)

/* CP0 register 3: entrylo1. */
_cp0_get_reg_u64 (entrylo1, C0_ENTRYLO1, 0)
_cp0_set_reg_u64 (entrylo1, C0_ENTRYLO1, 0)

/* CP0 register 4: context. */
_cp0_get_reg_u64 (context, C0_CONTEXT, 0)
_cp0_set_reg_u64 (context, C0_CONTEXT, 0)

/* CP0 register 5: pagemask. */
_cp0_get_reg_u32 (pagemask, C0_PAGEMASK, 0)
_cp0_set_reg_u32 (pagemask, C0_PAGEMASK, 0)

/* CP0 register 6: wired. */
_cp0_get_reg_u32 (wired, C0_WIRED, 0)
_cp0_set_reg_u32 (wired, C0_WIRED, 0)

/* CP0 register 7: reserved. */

/* CP0 register 8: badvaddr. */
_cp0_get_reg_u64 (badvaddr, C0_BADVADDR, 0)

/* CP0 register 9: count. */
_cp0_get_reg_u32 (count, C0_COUNT, 0)
_cp0_set_reg_u32 (count, C0_COUNT, 0)

/* CP0 register 10: entryhi. */
_cp0_get_reg_u64 (entryhi, C0_ENTRYHI, 0)
_cp0_set_reg_u64 (entryhi, C0_ENTRYHI, 0)

/* CP0 register 11: compare. */
_cp0_get_reg_u32 (compare, C0_COMPARE, 0)
_cp0_set_reg_u32 (compare, C0_COMPARE, 0)

/* CP0 register 12: status. */
_cp0_get_reg_u32 (status, C0_STATUS, 0)
_cp0_set_reg_u32 (status, C0_STATUS, 0)

/* CP0 register 13: cause. */
_cp0_get_reg_u32 (cause, C0_CAUSE, 0)
_cp0_set_reg_u32 (cause, C0_CAUSE, 0)

/* CP0 register 14: epc. */
_cp0_get_reg_u64 (epc, C0_EPC, 0)
_cp0_set_reg_u64 (epc, C0_EPC, 0)

/* CP0 register 15: prid. */
_cp0_get_reg_u32 (prid, C0_PRID, 0)

/* CP0 register 16: config. */
_cp0_get_reg_u32 (config, C0_CONFIG, 0)
_cp0_set_reg_u32 (config, C0_CONFIG, 0)

/* CP0 register 16 sel 1: config1. */
_cp0_get_reg_u32 (config1, C0_CONFIG, 1)

/* CP0 register 16 sel 2: config2. */
_cp0_get_reg_u32 (config2, C0_CONFIG, 2)

/* CP0 register 16 sel 3: config3. */
_cp0_get_reg_u32 (config3, C0_CONFIG, 3)

/* CP0 register 17: lladdr. */
_cp0_get_reg_u64 (lladdr, C0_LLADDR, 0)

/* CP0 register 18: watchlo. */
_cp0_get_reg_u64 (watchlo, C0_WATCHLO, 0)
_cp0_set_reg_u64 (watchlo, C0_WATCHLO, 0)

/* CP0 register 18 sel 1: watchlo1. */
_cp0_get_reg_u64 (watchlo1, C0_WATCHLO, 1)
_cp0_set_reg_u64 (watchlo1, C0_WATCHLO, 1)

/* CP0 register 19: watchhi. */
_cp0_get_reg_u32 (watchhi, C0_WATCHHI, 0)
_cp0_set_reg_u32 (watchhi, C0_WATCHHI, 0)

/* CP0 register 19 sel 1: watchhi1. */
_cp0_get_reg_u32 (watchhi1, C0_WATCHHI, 1)
_cp0_set_reg_u32 (watchhi1, C0_WATCHHI, 1)

/* CP0 register 20: xcontext. */
_cp0_get_reg_u64 (xcontext, C0_XCONTEXT, 0)
_cp0_set_reg_u64 (xcontext, C0_XCONTEXT, 0)

/* CP0 register 21: reserved. */

/* CP0 register 22: Performance Trace Register (SB-1).  */
_cp0_get_reg_u64 (ptr, C0_PTR, 0)

/* CP0 register 23: debug. */
_cp0_get_reg_u32 (debug, C0_DEBUG, 0)
_cp0_set_reg_u32 (debug, C0_DEBUG, 0)
/* CP0 register 23 sel 3: edebug. */
_cp0_get_reg_u32 (edebug, C0_DEBUG, 3)
_cp0_set_reg_u32 (edebug, C0_DEBUG, 3)

/* CP0 register 24: depc. */
_cp0_get_reg_u64 (depc, C0_DEPC, 0)
_cp0_set_reg_u64 (depc, C0_DEPC, 0)

/* CP0 register 25: perfcnt. */
_cp0_get_reg_u32 (perfcnt, C0_PERFCNT, 0)
_cp0_set_reg_u32 (perfcnt, C0_PERFCNT, 0)

/* CP0 register 25 sel 1: perfcnt1. */
_cp0_get_reg_u32 (perfcnt1, C0_PERFCNT, 1)
_cp0_set_reg_u32 (perfcnt1, C0_PERFCNT, 1)

/* CP0 register 25 sel 2: perfcnt2. */
_cp0_get_reg_u32 (perfcnt2, C0_PERFCNT, 2)
_cp0_set_reg_u32 (perfcnt2, C0_PERFCNT, 2)

/* CP0 register 25 sel 3: perfcnt3. */
_cp0_get_reg_u32 (perfcnt3, C0_PERFCNT, 3)
_cp0_set_reg_u32 (perfcnt3, C0_PERFCNT, 3)

/* CP0 register 25 sel 4: perfcnt4. */
_cp0_get_reg_u32 (perfcnt4, C0_PERFCNT, 4)
_cp0_set_reg_u32 (perfcnt4, C0_PERFCNT, 4)

/* CP0 register 25 sel 5: perfcnt5. */
_cp0_get_reg_u32 (perfcnt5, C0_PERFCNT, 5)
_cp0_set_reg_u32 (perfcnt5, C0_PERFCNT, 5)

/* CP0 register 25 sel 6: perfcnt6. */
_cp0_get_reg_u32 (perfcnt6, C0_PERFCNT, 6)
_cp0_set_reg_u32 (perfcnt6, C0_PERFCNT, 6)

/* CP0 register 25 sel 7: perfcnt7. */
_cp0_get_reg_u32 (perfcnt7, C0_PERFCNT, 7)
_cp0_set_reg_u32 (perfcnt7, C0_PERFCNT, 7)

/* CP0 register 26: errctl. */
_cp0_get_reg_u32 (errctl, C0_ERRCTL, 0)
_cp0_get_reg_u32 (buserr_pa, C0_ERRCTL, 1)

/* CP0 register 27: cacheerr_i. */
_cp0_get_reg_u32 (cacheerr_i, C0_CERR, 0)

/* CP0 register 27 sel 1: cacheerr_d. */
_cp0_get_reg_u32 (cacheerr_d, C0_CERR, 1)

/* CP0 register 27 sel 3: cacheerr_d_pa. */
_cp0_get_reg_u32 (cacheerr_d_pa, C0_CERR, 3)

/* CP0 register 28: taglo_i. */
_cp0_get_reg_u64 (taglo_i, C0_TAGLO, 0)
_cp0_set_reg_u64 (taglo_i, C0_TAGLO, 0)

/* CP0 register 28 sel 1: datalo_i. */
_cp0_get_reg_u64 (datalo_i, C0_TAGLO, 1)

/* CP0 register 28 sel 2: taglo_d. */
_cp0_get_reg_u64 (taglo_d, C0_TAGLO, 2)
_cp0_set_reg_u64 (taglo_d, C0_TAGLO, 2)

/* CP0 register 28 sel 3: datalo_d. */
_cp0_get_reg_u64 (datalo_d, C0_TAGLO, 3)

/* CP0 register 29: taghi_i. */
_cp0_get_reg_u64 (taghi_i, C0_TAGHI, 0)
_cp0_set_reg_u64 (taghi_i, C0_TAGHI, 0)

/* CP0 register 29 sel 1: datahi_i. */
_cp0_get_reg_u64 (datahi_i, C0_TAGHI, 1)

/* CP0 register 29 sel 2: taghi_d. */
_cp0_get_reg_u64 (taghi_d, C0_TAGHI, 2)
_cp0_set_reg_u64 (taghi_d, C0_TAGHI, 2)

/* CP0 register 29 sel 3: datahi_d. */
_cp0_get_reg_u64 (datahi_d, C0_TAGHI, 3)

/* CP0 register 30: errorepc. */
_cp0_get_reg_u64 (errorepc, C0_ERROREPC, 0)
_cp0_set_reg_u64 (errorepc, C0_ERROREPC, 0)

/* CP0 register 31: desave. */
_cp0_get_reg_u64 (desave, C0_DESAVE, 0)
_cp0_set_reg_u64 (desave, C0_DESAVE, 0)

#endif /* __LANGUAGE_ASSEMBLY */

/*  *********************************************************************
    *  CP1 (floating point) control registers
    ********************************************************************* */

#define FPA_IRR		0		/* CP1: Implementation/Revision */
#define FPA_CSR		31		/* CP1: Control/Status */

/*  *********************************************************************
    *  Macros for generating assembly language routines
    ********************************************************************* */

#if defined(__ASSEMBLER__)

/* global leaf function (does not call other functions) */
#define LEAF(name)		\
  	.globl	name;		\
  	.ent	name;		\
name:

/* global alternate entry to (local or global) leaf function */
#define XLEAF(name)		\
  	.globl	name;		\
  	.aent	name;		\
name:

/* end of a global function */
#define END(name)		\
  	.size	name,.-name;	\
  	.end	name

/* local leaf function (does not call other functions) */
#define SLEAF(name)		\
  	.ent	name;		\
name:

/* local alternate entry to (local or global) leaf function */
#define SXLEAF(name)		\
  	.aent	name;		\
name:

/* end of a local function */
#define SEND(name)		\
  	END(name)

/* define & export a symbol */
#define EXPORT(name)		\
  	.globl name;		\
name:

/* import a symbol */
#define	IMPORT(name, size)	\
	.extern	name,size

/* define a zero-fill common block (BSS if not overridden) with a global name */
#define COMM(name,size)		\
	.comm	name,size

/* define a zero-fill common block (BSS if not overridden) with a local name */
#define LCOMM(name,size)		\
  	.lcomm	name,size

#endif


/* Floating-Point Control register bits */
#define CSR_C		0x00800000
#define CSR_EXC		0x0003f000
#define CSR_EE		0x00020000
#define CSR_EV		0x00010000
#define CSR_EZ		0x00008000
#define CSR_EO		0x00004000
#define CSR_EU		0x00002000
#define CSR_EI		0x00001000
#define CSR_TV		0x00000800
#define CSR_TZ		0x00000400
#define CSR_TO		0x00000200
#define CSR_TU		0x00000100
#define CSR_TI		0x00000080
#define CSR_SV		0x00000040
#define CSR_SZ		0x00000020
#define CSR_SO		0x00000010
#define CSR_SU		0x00000008
#define CSR_SI		0x00000004
#define CSR_RM		0x00000003

/* Status Register */

#define S_SR_CUMASK	28				/* coprocessor usable bits */
#define M_SR_CUMASK	_MM_MAKEMASK(4,S_SR_CUMASK)
#define G_SR_CUMASK(x)	_MM_GETVALUE(x,S_SR_CUMASK,M_SR_CUMASK)

#define M_SR_CU3	_MM_MAKEMASK1(31)	/* coprocessor 3 usable */
#define M_SR_CU2	_MM_MAKEMASK1(30)	/* coprocessor 2 usable */
#define M_SR_CU1	_MM_MAKEMASK1(29)	/* coprocessor 1 usable */
#define M_SR_CU0	_MM_MAKEMASK1(28)	/* coprocessor 0 usable */

#define S_SR_RP		27			/* reduced power mode */
#define M_SR_RP		_MM_MAKEMASK1(27)	/* reduced power mode */
#define G_SR_RP(x)	_MM_GETVALUE(x,S_SR_RP,M_SR_RP)

#define S_SR_FR		26			/* fpu regs any data */
#define M_SR_FR		_MM_MAKEMASK1(26)	/* fpu regs any data */
#define G_SR_FR(x)	_MM_GETVALUE(x,S_SR_FR,M_SR_FR)

#define S_SR_RE		25			/* reverse endian */
#define M_SR_RE		_MM_MAKEMASK1(25)	/* reverse endian */
#define G_SR_RE(x)	_MM_GETVALUE(x,S_SR_RE,M_SR_RE)

#define S_SR_MX		24			/* MDMX */
#define M_SR_MX		_MM_MAKEMASK1(24)	/* MDMX */
#define G_SR_MX(x)	_MM_GETVALUE(x,S_SR_MX,M_SR_MX)

#define S_SR_PX		23			/* 64-bit ops in user mode */
#define M_SR_PX		_MM_MAKEMASK1(23)	/* 64-bit ops in user mode */
#define G_SR_PX(x)	_MM_GETVALUE(x,S_SR_PX,M_SR_PX)

#define S_SR_BEV	22			/* boot exception vectors */
#define M_SR_BEV	_MM_MAKEMASK1(22)	/* boot exception vectors */
#define G_SR_BEV(x)	_MM_GETVALUE(x,S_SR_BEV,M_SR_BEV)

#define S_SR_TS		21			/* TLB is shut down */
#define M_SR_TS		_MM_MAKEMASK1(21)	/* TLB is shut down */
#define G_SR_TS(x)	_MM_GETVALUE(x,S_SR_TS,M_SR_TS)

#define S_SR_SR		20			/* soft reset */
#define M_SR_SR		_MM_MAKEMASK1(20)	/* soft reset */
#define G_SR_SR(x)	_MM_GETVALUE(x,S_SR_SR,M_SR_SR)

#define S_SR_NMI	19			/* nonmaskable interrupt */
#define M_SR_NMI	_MM_MAKEMASK1(19)	/* nonmaskable interrupt */
#define G_SR_NMI(x)	_MM_GETVALUE(x,S_SR_NMI,M_SR_NMI)

#define S_SR_IMASK	8			/* all interrupt mask bits */
#define M_SR_IMASK	_MM_MAKEMASK(8,8)	/* all interrupt mask bits */
#define G_SR_IMASK(x)	_MM_GETVALUE(x,S_SR_IMASK,M_SR_IMASK)

#define M_SR_IBIT8	_MM_MAKEMASK1(15)	/* individual bits */
#define M_SR_IBIT7	_MM_MAKEMASK1(14)
#define M_SR_IBIT6	_MM_MAKEMASK1(13)
#define M_SR_IBIT5	_MM_MAKEMASK1(12)
#define M_SR_IBIT4	_MM_MAKEMASK1(11)
#define M_SR_IBIT3	_MM_MAKEMASK1(10)
#define M_SR_IBIT2	_MM_MAKEMASK1(9)
#define M_SR_IBIT1	_MM_MAKEMASK1(8)

#define M_SR_IMASK8	0			/* masks for nested int levels */
#define M_SR_IMASK7	_MM_MAKEMASK(1,15)
#define M_SR_IMASK6	_MM_MAKEMASK(2,14)
#define M_SR_IMASK5	_MM_MAKEMASK(3,13)
#define M_SR_IMASK4	_MM_MAKEMASK(4,12)
#define M_SR_IMASK3	_MM_MAKEMASK(5,11)
#define M_SR_IMASK2	_MM_MAKEMASK(6,10)
#define M_SR_IMASK1	_MM_MAKEMASK(7,9)
#define M_SR_IMASK0	_MM_MAKEMASK(8,8)

#define S_SR_KX		7			/* 64-bit access for kernel */
#define M_SR_KX		_MM_MAKEMASK1(7)	/* 64-bit access for kernel */
#define G_SR_KX(x)	_MM_GETVALUE(x,S_SR_KX,M_SR_KX)

#define S_SR_SX		6			/* .. for supervisor */
#define M_SR_SX		_MM_MAKEMASK1(6)	/* .. for supervisor */
#define G_SR_SX(x)	_MM_GETVALUE(x,S_SR_SX,M_SR_SX)

#define S_SR_UX		5			/* .. for user */
#define M_SR_UX		_MM_MAKEMASK1(5)	/* .. for user */
#define G_SR_UX(x)	_MM_GETVALUE(x,S_SR_UX,M_SR_UX)

#define S_SR_KSU	3			/* base operating mode mode */
#define M_SR_KSU	_MM_MAKEMASK(2,S_SR_KSU)