sbmips.h

一个很好的嵌入式linux平台下的bootloader

/*  *********************************************************************
    *  SB1250 Board Support Package
    *  
    *  MIPS64 CPU definitions			File: sbmips.h
    * 
    *  This module contains constants and macros specific to the
    *  SB1 MIPS64 core.
    *  
    *********************************************************************  
    *
    *  Copyright 2000,2001,2002,2003
    *  Broadcom Corporation. All rights reserved.
    *  
    *  This software is furnished under license and may be used and 
    *  copied only in accordance with the following terms and 
    *  conditions.  Subject to these conditions, you may download, 
    *  copy, install, use, modify and distribute modified or unmodified 
    *  copies of this software in source and/or binary form.  No title 
    *  or ownership is transferred hereby.
    *  
    *  1) Any source code used, modified or distributed must reproduce 
    *     and retain this copyright notice and list of conditions 
    *     as they appear in the source file.
    *  
    *  2) No right is granted to use any trade name, trademark, or 
    *     logo of Broadcom Corporation.  The "Broadcom Corporation" 
    *     name may not be used to endorse or promote products derived 
    *     from this software without the prior written permission of 
    *     Broadcom Corporation.
    *  
    *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
    *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
    *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
    *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 
    *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 
    *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
    *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 
    *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
    *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
    *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 
    *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 
    *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 
    *     THE POSSIBILITY OF SUCH DAMAGE.
    ********************************************************************* */

#ifndef _SB_MIPS_H
#define _SB_MIPS_H

/*  *********************************************************************
    *  Configure language
    ********************************************************************* */

#if defined(__ASSEMBLER__)
#define _ATYPE_
#define _ATYPE32_
#define _ATYPE64_
#define _MM_MAKE64(x) (x)
#define _MM_MAKE32(x) (x)
#else
#define _ATYPE_		(__SIZE_TYPE__)
#define _ATYPE32_	(int)
#define _ATYPE64_	(long long)
#define _MM_MAKE64(x) ((uint64_t)(x))
#define _MM_MAKE32(x) ((uint32_t)(x))
#endif


/*  *********************************************************************
    *  Bitfield macros
    ********************************************************************* */

/*
 * Make a mask for 1 bit at position 'n'
 */

#define _MM_MAKEMASK1(n) (1 << (n))
#define _MM_MAKEMASK1_64(n) (_MM_MAKE64(1) << _MM_MAKE64(n))

/*
 * Make a mask for 'v' bits at position 'n'
 */

#define _MM_MAKEMASK(v,n) (((1<<(v))-1) << (n))
#define _MM_MAKEMASK_64(v,n) (_MM_MAKE64((_MM_MAKE64(1)<<(v))-1) << _MM_MAKE64(n))

/*
 * Make a value at 'v' at bit position 'n'
 */

#define _MM_MAKEVALUE(v,n) ((v) << (n))
#define _MM_MAKEVALUE_64(v,n) (_MM_MAKE64(v) << _MM_MAKE64(n))

/*
 * Retrieve a value from 'v' at bit position 'n' with 'm' mask bits
 */

#define _MM_GETVALUE(v,n,m) (((v) & (m)) >> (n))
#define _MM_GETVALUE_64(v,n,m) ((_MM_MAKE64(v) & _MM_MAKE64(m)) >> _MM_MAKE64(n))



/*  *********************************************************************
    *  32-bit MIPS Address Spaces
    ********************************************************************* */

#ifdef __ASSEMBLER__

#ifdef __mips64		/* If 64-bit GPRs, need to sign extend.  */
/* XXX: This is a kludge, and will only work as long as all addrs it
   XXX: is applied to should be sign extended.  */
#define _ACAST32_	0xffffffff00000000 |
#else
#define _ACAST32_
#endif /* __mips64  */
#define _ACAST64_

#else

#define _ACAST32_	_ATYPE_ _ATYPE32_	/* widen if necessary */
#define _ACAST64_		_ATYPE64_	/* do _not_ narrow */

#endif

/* 32-bit address map */
#define UBASE		0x00000000		/* user+ mapped */
#define USIZE		0x80000000
#define K0BASE 		(_ACAST32_ 0x80000000)	/* kernel unmapped cached */
#define K0SIZE 		0x20000000
#define K1BASE 		(_ACAST32_ 0xa0000000)	/* kernel unmapped uncached */
#define K1SIZE 		0x20000000
#define KSBASE 		(_ACAST32_ 0xc0000000)	/* supervisor+ mapped */
#define KSSIZE 		0x20000000
#define K3BASE 		(_ACAST32_ 0xe0000000)	/* kernel mapped */
#define K3SIZE 		0x20000000

/* 64-bit address map additions to the above (sign-extended) ranges */
#define XUBASE		(_ACAST64_ 0x0000000080000000)	/* user+ mapped */
#define XUSIZE		(_ACAST64_ 0x00000FFF80000000)
#define XSSEGBASE       (_ACAST64_ 0x4000000000000000)	/* supervisor+ mapped */
#define XSSEGSIZE	(_ACAST64_ 0x0000100000000000)
#define XKPHYSBASE      (_ACAST64_ 0x8000000000000000)	/* kernel unmapped */
#define XKPHYSSIZE	(_ACAST64_ 0x0000100000000000)
#define XKSEGBASE       (_ACAST64_ 0xC000000000000000)	/* kernel mapped */
#define XKSEGSIZE	(_ACAST64_ 0x00000FFF80000000)

#define GEN_VECT 	(_ACAST32_ 0x80000080)
#define UTLB_VECT 	(_ACAST32_ 0x80000000)

/*  *********************************************************************
    *  Address space coercion macros
    ********************************************************************* */

#define PHYS_TO_K0(pa)	(K0BASE | (pa))
#define PHYS_TO_K1(pa)	(K1BASE | (pa))
#define K0_TO_PHYS(va)	((va) & (K0SIZE-1))
#define K1_TO_PHYS(va)	((va) & (K1SIZE-1))
#define K0_TO_K1(va)	((va) | K1SIZE)
#define K1_TO_K0(va)	((va) & ~K1SIZE)

#define PHYS_TO_XK1(p) (_ACAST64_ (0xffffffffa0000000 | (p)))
#define XK1_TO_PHYS(p) ((p) & (K1SIZE-1))
#define PHYS_TO_XKPHYS(cca,p) (_SB_MAKEMASK1(63) | (_SB_MAKE64(cca) << 59) | (p))
#define PHYS_TO_XKSEG_UNCACHED(p)  PHYS_TO_XKPHYS(K_CALG_UNCACHED,(p))
#define PHYS_TO_XKSEG_CACHED(p)    PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p))
#define XKPHYS_TO_PHYS(p) ((p) & _SB_MAKEMASK(0,59))


#if !defined(__ASSEMBLER__)
#define mips_wbflush()  __asm__ __volatile__ ("sync" : : : "memory")
#define	ISK0SEG(va)	((va) >= K0BASE && (va) <= (K0BASE + K0SIZE - 1))
#define	ISK1SEG(va)	((va) >= K1BASE && (va) <= (K1BASE + K1SIZE - 1))
#endif

/*  *********************************************************************
    *  Register aliases
    ********************************************************************* */

#if defined(__ASSEMBLER__)
#define zero		$0
#define	AT		$1		/* assembler temporaries */
#define	v0		$2		/* value holders */
#define	v1		$3
#define	a0		$4		/* arguments */
#define	a1		$5
#define	a2		$6
#define	a3		$7
#define	t0		$8		/* temporaries */
#define	t1		$9
#define	t2		$10
#define	t3		$11
#define	t4		$12
#define	t5		$13
#define	t6		$14
#define	t7		$15
#define ta0		$12
#define ta1		$13
#define ta2		$14
#define ta3		$15
#define	s0		$16		/* saved registers */
#define	s1		$17
#define	s2		$18
#define	s3		$19
#define	s4		$20
#define	s5		$21
#define	s6		$22
#define	s7		$23
#define	t8		$24		/* temporaries */
#define	t9		$25
#define	k0		$26		/* kernel registers */
#define	k1		$27
#define	gp		$28		/* global pointer */
#define	sp		$29		/* stack pointer */
#define	s8		$30		/* saved register */
#define	fp		$30		/* frame pointer */
#define	ra		$31		/* return address */
#endif

/*  *********************************************************************
    *  CP0 Registers 
    ********************************************************************* */

#if defined(__ASSEMBLER__)
#define C0_INX		$0		/* CP0: TLB Index */
#define C0_RAND		$1		/* CP0: TLB Random */
#define C0_TLBLO0	$2		/* CP0: TLB EntryLo0 */
#define C0_TLBLO	C0_TLBLO0	/* CP0: TLB EntryLo0 */
#define C0_TLBLO1	$3		/* CP0: TLB EntryLo1 */
#define C0_CTEXT	$4		/* CP0: Context */
#define C0_PGMASK	$5		/* CP0: TLB PageMask */
#define C0_WIRED	$6		/* CP0: TLB Wired */
#define C0_BADVADDR	$8		/* CP0: Bad Virtual Address */
#define C0_COUNT 	$9		/* CP0: Count */
#define C0_TLBHI	$10		/* CP0: TLB EntryHi */
#define C0_COMPARE	$11		/* CP0: Compare */
#define C0_SR		$12		/* CP0: Processor Status */
#define C0_CAUSE	$13		/* CP0: Exception Cause */
#define C0_EPC		$14		/* CP0: Exception PC */
#define C0_PRID		$15		/* CP0: Processor Revision Indentifier */
#define C0_CONFIG	$16		/* CP0: Config */
#define C0_LLADDR	$17		/* CP0: LLAddr */
#define C0_WATCHLO	$18		/* CP0: WatchpointLo */
#define C0_WATCHHI	$19		/* CP0: WatchpointHi */
#define C0_XCTEXT	$20		/* CP0: XContext */
#define C0_PTR		$22		/* CP0: Performance Trace Reg (SB-1) */
#define C0_DEBUG   	$23		/* CP0: debug */
#define C0_DEPC    	$24		/* CP0: depc */
#define C0_PERFCONT	$25		/* CP0: Performance counters */
#define C0_ERRCTL	$26		/* CP0: Error control */
#define C0_BUSERR_DPA	$26,1		/* CP0: Bus error physical address */
#define C0_CERR		$27		/* CP0: cache error */
#define C0_CERR_I	$27		/* CP0: cache error */
#define C0_CERR_D	$27,1		/* CP0: Dcache error */
#define C0_CERR_DPA	$27,3		/* CP0: Dcache error physical address */
#define C0_TAGLO	$28		/* CP0: TagLo */
#define C0_TAGHI	$29		/* CP0: TagHi */
#define C0_ERREPC	$30		/* CP0: ErrorEPC */
#define C0_DESAVE	$31		/* CP0: JTAG debug exception
					   save register */

#else

#define C0_INX		0		/* CP0: TLB Index */
#define C0_RAND		1		/* CP0: TLB Random */
#define C0_TLBLO0	2		/* CP0: TLB EntryLo0 */
#define C0_TLBLO	C0_TLBLO0	/* CP0: TLB EntryLo0 */
#define C0_TLBLO1	3		/* CP0: TLB EntryLo1 */
#define C0_CTEXT	4		/* CP0: Context */
#define C0_PGMASK	5		/* CP0: TLB PageMask */
#define C0_WIRED	6		/* CP0: TLB Wired */
#define C0_BADVADDR	8		/* CP0: Bad Virtual Address */
#define C0_COUNT 	9		/* CP0: Count */
#define C0_TLBHI	10		/* CP0: TLB EntryHi */
#define C0_COMPARE	11		/* CP0: Compare */
#define C0_SR		12		/* CP0: Processor Status */
#define C0_CAUSE	13		/* CP0: Exception Cause */
#define C0_EPC		14		/* CP0: Exception PC */
#define C0_PRID		15		/* CP0: Processor Revision Indentifier */
#define C0_CONFIG	16		/* CP0: Config */
#define C0_LLADDR	17		/* CP0: LLAddr */
#define C0_WATCHLO	18		/* CP0: WatchpointLo */
#define C0_WATCHHI	19		/* CP0: WatchpointHi */
#define C0_XCTEXT	20		/* CP0: XContext */
#define C0_PTR		22		/* CP0: Performance Trace Reg (SB-1) */
#define C0_DEBUG   	23		/* CP0: debug */
#define C0_DEPC    	24		/* CP0: depc */
#define C0_PERFCONT	25		/* CP0: Performance counters */
#define C0_ERRCTL	26		/* CP0: Error control */
#define C0_CERR		27		/* CP0: Icache error */
#define C0_TAGLO	28		/* CP0: TagLo */
#define C0_TAGHI	29		/* CP0: TagHi */
#define C0_ERREPC	30		/* CP0: ErrorEPC */
#define C0_DESAVE	31		/* CP0: JTAG debug exception
					   save register */

#endif

/* Aliases to match MIPS manuals.  */
#define C0_INDEX        C0_INX
#define C0_RANDOM       C0_RAND
#define C0_ENTRYLO0     C0_TLBLO0
#define C0_ENTRYLO1     C0_TLBLO1
#define C0_CONTEXT      C0_CTEXT
#define C0_PAGEMASK     C0_PGMASK
#define C0_ENTRYHI      C0_TLBHI
#define C0_STATUS       C0_SR
#define C0_XCONTEXT     C0_XCTEXT
#define C0_PERFCNT      C0_PERFCONT
#define C0_ERROREPC     C0_ERREPC

#ifndef __LANGUAGE_ASSEMBLY

/* Functions to get/set all CP0 registers via inline asms.
   Note that the functions which access 64-bit CP0 register are
   only provided if __mips64 is defined (i.e., if compiling with
   "-mips3", "-mips4", or "-mips64".

   The functions are of the form:
     cp0_get_<name>
     cp0_set_<name> 
   where <name> is the register name as it appears in MIPS
   architecture manuals.

   For example, the functions
     cp0_get_index
     cp0_set_index
   get and set the CP0 Index register.  */

#define	_cp0_get_reg(name, num, sel, type, d)                         \
  static inline type						      \
  cp0_get_ ## name (void)					      \
  {								      \
    type val;							      \
    __asm__ __volatile__ (".set push;"                                \
                          ".set mips64;"                              \
                          d "mfc0 %0, $%1, %2;"                       \
			  ".set pop;"                                 \
			  : "=r"(val) : "i"(num), "i"(sel));          \
    return val;							      \
  }

#define	_cp0_set_reg(name, num, sel, type, d)                         \
  static inline void						      \
  cp0_set_ ## name (type val)					      \
  {								      \
    __asm__ __volatile__ (".set push;"                                \
                          ".set mips64;"                              \
                          d "mtc0 %0, $%1, %2;"                       \
                          ".set pop;"           		      \
                          : : "r"(val), "i"(num), "i"(sel));          \
  }

/* Get and set 32-bit CP0 registers which are treated as unsigned values.  */
#define _cp0_get_reg_u32(name, num, sel) \
  _cp0_get_reg (name, (num), (sel), unsigned int, "")
#define _cp0_set_reg_u32(name, num, sel) \
  _cp0_set_reg (name, (num), (sel), unsigned int, "")

/* Get and set 32-bit CP0 registers which are treated as signed values
   so the high bit can be tested easily.  */
#define _cp0_get_reg_s32(name, num, sel) \
  _cp0_get_reg (name, (num), (sel), int, "")
#define _cp0_set_reg_s32(name, num, sel) \
  _cp0_set_reg (name, (num), (sel), int, "")

#if defined(__mips64)
/* Get and set 64-bit CP0 registers which are treated as unsigned values.
   Note that these functions are only provided if compiling for with
   64-bit GPRs.  */
#define _cp0_get_reg_u64(name, num, sel) \
  _cp0_get_reg (name, (num), (sel), unsigned long long, "d")