📄 bcm1480_pci.h
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#define M_BCM1480_PHB_MAP_ENABLE _SB_MAKEMASK1_32(0)#define M_BCM1480_PHB_MAP_L2CA _SB_MAKEMASK1_32(2)#define M_BCM1480_PHB_MAP_ENDIAN _SB_MAKEMASK1_32(3)#define S_BCM1480_PHB_MAP_ADDR 12#define M_BCM1480_PHB_MAP_ADDR _SB_MAKEMASK_32(20,S_BCM1480_PHB_MAP_ADDR)#define V_BCM1480_PHB_MAP_ADDR(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_MAP_ADDR)#define G_BCM1480_PHB_MAP_ADDR(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_MAP_ADDR,M_BCM1480_PHB_MAP_ADDR)/* * PHB Additional Status and Command Register (Table 118) */#define M_BCM1480_PHB_ASTCMD_HOTPLUG_EN _SB_MAKEMASK1_32(0)#define M_BCM1480_PHB_ASTCMD_SERR_DET _SB_MAKEMASK1_32(1)#define M_BCM1480_PHB_ASTCMD_TRDY_ERR _SB_MAKEMASK1_32(2)#define M_BCM1480_PHB_ASTCMD_RETRY_ERR _SB_MAKEMASK1_32(3)#define M_BCM1480_PHB_ASTCMD_TRDY_INT_EN _SB_MAKEMASK1_32(4)#define M_BCM1480_PHB_ASTCMD_RETRY_INT_EN _SB_MAKEMASK1_32(5)#define M_BCM1480_PHB_ASTCMD_COMPL_TO_ERR _SB_MAKEMASK1_32(6)#define M_BCM1480_PHB_ASTCMD_COMPL_TO_INT_EN _SB_MAKEMASK1_32(7)#define M_BCM1480_PHB_ASTCMD_64B_DEVICE_SET _SB_MAKEMASK1_32(16)#define M_BCM1480_PHB_ASTCMD_133MHZ_CAP_SET _SB_MAKEMASK1_32(17)#define V_BCM1480_PHB_ASTCMD_DEFAULT (M_BCM1480_PHB_ASTCMD_64B_DEVICE_SET | \ M_BCM1480_PHB_ASTCMD_133MHZ_CAP_SET)/* * PHB INTA Control Register (Table 119) */#define M_BCM1480_PHB_SIGNAL_INTA _SB_MAKEMASK1_32(0)/* * PHB External Configuratation Disable Register (Table 120) */#define M_BCM1480_PHB_EXT_CONFIG_DIS _SB_MAKEMASK1_32(0)/* * PHB Timeout Register (Table 121) */#define S_BCM1480_PHB_TIMEOUT_TRDY 0#define M_BCM1480_PHB_TIMEOUT_TRDY _SB_MAKEMASK_32(8,S_BCM1480_PHB_TIMEOUT_TRDY)#define V_BCM1480_PHB_TIMEOUT_TRDY(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_TIMEOUT_TRDY)#define G_BCM1480_PHB_TIMEOUT_TRDY(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_TIMEOUT_TRDY,M_BCM1480_PHB_TIMEOUT_TRDY)#define S_BCM1480_PHB_TIMEOUT_RETRY 8#define M_BCM1480_PHB_TIMEOUT_RETRY _SB_MAKEMASK_32(8,S_BCM1480_PHB_TIMEOUT_RETRY)#define V_BCM1480_PHB_TIMEOUT_RETRY(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_TIMEOUT_RETRY)#define G_BCM1480_PHB_TIMEOUT_RETRY(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_TIMEOUT_RETRY,M_BCM1480_PHB_TIMEOUT_RETRY)#define S_BCM1480_PHB_TIMEOUT_COMPL 16#define M_BCM1480_PHB_TIMEOUT_COMPL _SB_MAKEMASK_32(4,S_BCM1480_PHB_TIMEOUT_COMPL)#define V_BCM1480_PHB_TIMEOUT_COMPL(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_TIMEOUT_COMPL)#define G_BCM1480_PHB_TIMEOUT_COMPL(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_TIMEOUT_COMPL,M_BCM1480_PHB_TIMEOUT_COMPL)#define S_BCM1480_PHB_TIMEOUT_INB_RD_PREF 20#define M_BCM1480_PHB_TIMEOUT_INB_RD_PREF _SB_MAKEMASK_32(4,S_BCM1480_PHB_TIMEOUT_INB_RD_PREF)#define V_BCM1480_PHB_TIMEOUT_INB_RD_PREF(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_TIMEOUT_INB_RD_PREF)#define G_BCM1480_PHB_TIMEOUT_INB_RD_PREF(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_TIMEOUT_INB_RD_PREF,M_BCM1480_PHB_TIMEOUT_INB_RD_PREF)#define M_BCM1480_PHB_TIMEOUT_INB_RD_OUTB_WR _SB_MAKEMASK1_32(24)#define M_BCM1480_PHB_TIMEOUT_INB_RD_OUTB_RD _SB_MAKEMASK1_32(25)#define M_BCM1480_PHB_TIMEOUT_INB_RD_INB_WR _SB_MAKEMASK1_32(25)#define S_BCM1480_PHB_TIMEOUT_OUTB_FWD_PROG 28#define M_BCM1480_PHB_TIMEOUT_OUTB_FWD_PROG _SB_MAKEMASK_32(4,S_BCM1480_PHB_TIMEOUT_OUTB_FWD_PROG)#define V_BCM1480_PHB_TIMEOUT_OUTB_FWD_PROG(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_TIMEOUT_OUTB_FWD_PROG)#define G_BCM1480_PHB_TIMEOUT_OUTB_FWD_PROG(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_TIMEOUT_OUTB_FWD_PROG,M_BCM1480_PHB_TIMEOUT_OUTB_FWD_PROG)#define V_BCM1480_PHB_TIMEOUT_DEFAULT (V_BCM1480_PHB_TIMEOUT_TRDY(0x80) | \ V_BCM1480_PHB_TIMEOUT_RETRY(0x80) | \ V_BCM1480_PHB_TIMEOUT_COMPL(0xA))/* * PHB Transaction Control Register (Table 122) */#define S_BCM1480_PHB_XACT_WR_COMBINE_TMR 0#define M_BCM1480_PHB_XACT_WR_COMBINE_TMR _SB_MAKEMASK_32(8,S_BCM1480_PHB_XACT_WR_COMBINE_TMR)#define V_BCM1480_PHB_XACT_WR_COMBINE_TMR(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_XACT_WR_COMBINE_TMR)#define G_BCM1480_PHB_XACT_WR_COMBINE_TMR(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_XACT_WR_COMBINE_TMR,M_BCM1480_PHB_XACT_WR_COMBINE_TMR)#define S_BCM1480_PHB_XACT_OUTB_NP_ORDER 8#define M_BCM1480_PHB_XACT_OUTB_NP_ORDER _SB_MAKEMASK_32(2,S_BCM1480_PHB_XACT_OUTB_NP_ORDER)#define V_BCM1480_PHB_XACT_OUTB_NP_ORDER(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_XACT_OUTB_NP_ORDER)#define G_BCM1480_PHB_XACT_OUTB_NP_ORDER(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_XACT_OUTB_NP_ORDER,M_BCM1480_PHB_XACT_OUTB_NP_ORDER)#define M_BCM1480_PHB_XACT_SET_WR_RLX_ORDER _SB_MAKEMASK1_32(10)#define M_BCM1480_PHB_XACT_SET_RSP_RLX_ORDER _SB_MAKEMASK1_32(11)#define M_BCM1480_PHB_XACT_SET_WR_NO_SNOOP _SB_MAKEMASK1_32(12)#define M_BCM1480_PHB_XACT_SET_RD_NO_SNOOP _SB_MAKEMASK1_32(13)#define M_BCM1480_PHB_XACT_SET_OUTB_RD_PREF_DIS _SB_MAKEMASK1_32(14)#define M_BCM1480_PHB_XACT_SET_OUTB_RSP_WR_ORD_DIS _SB_MAKEMASK1_32(15)#define S_BCM1480_PHB_XACT_INB_RD_MAX_PREF 20#define M_BCM1480_PHB_XACT_INB_RD_MAX_PREF _SB_MAKEMASK_32(3,S_BCM1480_PHB_XACT_INB_RD_MAX_PREF)#define V_BCM1480_PHB_XACT_INB_RD_MAX_PREF(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_XACT_INB_RD_MAX_PREF)#define G_BCM1480_PHB_XACT_INB_RD_MAX_PREF(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_XACT_INB_RD_MAX_PREF,M_BCM1480_PHB_XACT_INB_RD_MAX_PREF)#define S_BCM1480_PHB_XACT_INB_RD_LN_MAX_PREF 24#define M_BCM1480_PHB_XACT_INB_RD_LN_MAX_PREF _SB_MAKEMASK_32(3,S_BCM1480_PHB_XACT_INB_RD_LN_MAX_PREF)#define V_BCM1480_PHB_XACT_INB_RD_LN_MAX_PREF(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_XACT_INB_RD_LN_MAX_PREF)#define G_BCM1480_PHB_XACT_INB_RD_LN_MAX_PREF(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_XACT_INB_RD_LN_MAX_PREF,M_BCM1480_PHB_XACT_INB_RD_LN_MAX_PREF)#define S_BCM1480_PHB_XACT_INB_RD_MUL_MAX_PREF 28#define M_BCM1480_PHB_XACT_INB_RD_MUL_MAX_PREF _SB_MAKEMASK_32(3,S_BCM1480_PHB_XACT_INB_RD_MUL_MAX_PREF)#define V_BCM1480_PHB_XACT_INB_RD_MUL_MAX_PREF(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_XACT_INB_RD_MUL_MAX_PREF)#define G_BCM1480_PHB_XACT_INB_RD_MUL_MAX_PREF(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_XACT_INB_RD_MUL_MAX_PREF,M_BCM1480_PHB_XACT_INB_RD_MUL_MAX_PREF)#define K_BCM1480_PHB_PREF_256B 0x0#define K_BCM1480_PHB_PREF_32B 0x1#define K_BCM1480_PHB_PREF_64B 0x2#define K_BCM1480_PHB_PREF_96B 0x3#define K_BCM1480_PHB_PREF_128B 0x4 /* also 0x5 */#define K_BCM1480_PHB_PREF_192B 0x6 /* also 0x7 */#define V_BCM1480_PHB_XACT_DEFAULT (V_BCM1480_PHB_XACT_WR_COMBINE_TMR(0x20) | \ V_BCM1480_PHB_XACT_OUTB_NP_ORDER(0x1) | \ V_BCM1480_PHB_XACT_INB_RD_MAX_PREF(0x1) | \ V_BCM1480_PHB_XACT_INB_RD_LN_MAX_PREF(0x1) | \ V_BCM1480_PHB_XACT_INB_RD_MUL_MAX_PREF(0x4))/* * PHB Test and Debug Register (Table 123) */#define M_BCM1480_PHB_TEST_LOOPBACK _SB_MAKEMASK1_32(0)#define M_BCM1480_PHB_TEST_32BIT_MODE _SB_MAKEMASK1_32(1)#define M_BCM1480_PHB_TEST_QUICK_TEST _SB_MAKEMASK1_32(2)/* * PHB Outbound Map Table Entries (Lower, Upper) (Tables 124 and 125) */#define M_BCM1480_PHB_OMAP_L_ENABLE _SB_MAKEMASK1_32(0)#define S_BCM1480_PHB_OMAP_L_ADDR 20#define M_BCM1480_PHB_OMAP_L_ADDR _SB_MAKEMASK_32(12,S_BCM1480_PHB_OMAP_L_ADDR)#define V_BCM1480_PHB_OMAP_L_ADDR(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_OMAP_L_ADDR)#define G_BCM1480_PHB_OMAP_L_ADDR(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_OMAP_L_ADDR,M_BCM1480_PHB_OMAP_L_ADDR)#define S_BCM1480_PHB_OMAP_U_ADDR 0#define M_BCM1480_PHB_OMAP_U_ADDR _SB_MAKEMASK_32(32,S_BCM1480_PHB_OMAP_U_ADDR)#define V_BCM1480_PHB_OMAP_U_ADDR(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_OMAP_U_ADDR)#define G_BCM1480_PHB_OMAP_U_ADDR(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_OMAP_U_ADDR,M_BCM1480_PHB_OMAP_U_ADDR)/* * PHB Target Done Register (Table 129) */#define S_BCM1480_PHB_TGT_DONE_COUNTER 0#define M_BCM1480_PHB_TGT_DONE_COUNTER _SB_MAKEMASK_32(8,S_BCM1480_PHB_TGT_DONE_COUNTER)#define V_BCM1480_PHB_TGT_DONE_COUNTER(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_TGT_DONE_COUNTER)#define G_BCM1480_PHB_TGT_DONE_COUNTER(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_TGT_DONE_COUNTER,M_BCM1480_PHB_TGT_DONE_COUNTER)#endif /* _BCM1480_PCI_H */⌨️ 快捷键说明
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