diag_l2cache.s

一个很好的嵌入式linux平台下的bootloader

#define R_ECC_NEXT_WAY   s3			
#define R_ECC_BLOCK      s1		
#define R_ECC_WADDR      t5			
#define R_ECC_RADDR      t5
			
#define R_ECC_SCRATCH0   t6			
#define R_ECC_SCRATCH1   t7			
#define R_ECC_SCRATCH2   t8			
#define R_ECC_SCRATCH3   t9			
#define R_ECC_SCRATCH4   s6			
#define R_ECC_SCRATCH5   s7			

/*
#define	DATA_FOR_ECC_PATT0 0x0000	
#define	DATA_FOR_ECC_PATT1 0x0020	
#define	DATA_FOR_ECC_PATT2 0x1032	
#define	DATA_FOR_ECC_PATT3 0x0017	
#define	DATA_FOR_ECC_PATT4 0x1822	

#define	DATA_FOR_ECC_INVPATT0 0x0036	
#define	DATA_FOR_ECC_INVPATT1 0x0016	
#define	DATA_FOR_ECC_INVPATT2 0x1004	
#define	DATA_FOR_ECC_INVPATT3 0x0021	
#define	DATA_FOR_ECC_INVPATT4 0x1814	
*/
#define       DATA_FOR_ECC_PATT0 0x0000
#define       DATA_FOR_ECC_PATT1 0x00ba
#define       DATA_FOR_ECC_PATT2 0x0438
#define       DATA_FOR_ECC_PATT3 0x05be
#define       DATA_FOR_ECC_PATT4 0x0099
 
#define       DATA_FOR_ECC_INVPATT0 0x059c
#define       DATA_FOR_ECC_INVPATT1 0x0526
#define       DATA_FOR_ECC_INVPATT2 0x01a4
#define       DATA_FOR_ECC_INVPATT3 0x0022
#define       DATA_FOR_ECC_INVPATT4 0x0505

#define	ECC_WRITE_PAT(addr, pattern0, pattern1, pattern2, pattern3)\
	dli	R_ECC_SCRATCH2, 4; \
	/*dli	R_ECC_SCRATCH0, 0x00400000;*/ \
	/*nor	R_ECC_SCRATCH1, R_ECC_SCRATCH0, $0;*/ \
1:	sd	pattern0, 0(addr); \
	sd	zero, 8(addr); \
	sd	zero, 16(addr); \
	sd	zero, 24(addr); \
	cache	L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(addr); \
	/*or 	addr, R_ECC_SCRATCH0, addr;*/ \
	/*sd	pattern0, 0(addr);*/ \
	/*sd	zero, 8(addr);*/ \
	/*sd	zero, 16(addr);*/ \
	/*sd	zero, 24(addr);*/ \
	/*cache	L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(addr);*/ \
	/*and 	addr, addr, R_ECC_SCRATCH1;*/ \
	move 	R_ECC_SCRATCH3, pattern0; 	\
	move 	pattern0, pattern1;	\
	move 	pattern1, pattern2;	\
	move 	pattern2, pattern3;	\
	move 	pattern3, R_ECC_SCRATCH3; 	\
	addi 	R_ECC_SCRATCH2, R_ECC_SCRATCH2, -1; \
	bne	R_ECC_SCRATCH2, zero, 1b;   \
	daddu 	addr, addr, R_BG_NEXT_WAY; \
	li      R_ECC_SCRATCH0, -4*2*65536; \
        dadd	addr, addr, R_ECC_SCRATCH0
		
#define ECC_CHECK_PAT(addr,pattern0,pattern1,pattern2,pattern3,fail)		\
	dli	R_ECC_SCRATCH4, XKPHYS_UNC; \
	dli	R_ECC_SCRATCH5, SCD_BW_BASE; \
	or	R_ECC_SCRATCH4, R_ECC_SCRATCH4, R_ECC_SCRATCH5; \
	li	R_ECC_SCRATCH5, 4;	\
	sd	zero, BUS_L2_ERRORS(R_ECC_SCRATCH4); \
	sync;	\
1:	ld	R_ECC_SCRATCH0, 0(addr);	\
	ld	R_ECC_SCRATCH1, 8(addr);	\
        sne     R_ECC_SCRATCH0, R_ECC_SCRATCH0, pattern0;     \
        or      R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH0; \
	ld	R_ECC_SCRATCH2, 16(addr);\
        sne     R_ECC_SCRATCH1, R_ECC_SCRATCH1, zero;     \
        or      R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH1; \
	ld	R_ECC_SCRATCH3, 24(addr);\
        sne     R_ECC_SCRATCH2, R_ECC_SCRATCH2, zero;     \
        or      R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH2; \
	ld	R_ECC_SCRATCH0, BUS_L2_ERRORS(R_ECC_SCRATCH4); \
        sne     R_ECC_SCRATCH3, R_ECC_SCRATCH3, zero;     \
        or      R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH3; \
	li	R_ECC_SCRATCH2, 0xffff;	\
	and	R_ECC_SCRATCH0, R_ECC_SCRATCH2, R_ECC_SCRATCH0;	\
        sne     R_ECC_SCRATCH0, R_ECC_SCRATCH0, zero;     \
        or      R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH0; \
	move 	R_ECC_SCRATCH3, pattern0; 	\
	move 	pattern0, pattern1;	\
	move 	pattern1, pattern2;	\
	move 	pattern2, pattern3;	\
	move 	pattern3, R_ECC_SCRATCH3; 	\
	addi 	R_BG_SCRATCH5, R_BG_SCRATCH5, -1; \
	bne	R_BG_SCRATCH5, zero, 1b;   \
	daddu 	addr, addr, R_ECC_NEXT_WAY; \
	li      R_ECC_SCRATCH0, -4*2*65536; \
        dadd	addr, addr, R_ECC_SCRATCH0

#define ECC_CHECK_PAT1(addr,pattern0,pattern1,pattern2,pattern3,fail)		\
	dli	R_ECC_SCRATCH4, XKPHYS_UNC; \
	dli	R_ECC_SCRATCH5, SCD_BW_BASE; \
	or	R_ECC_SCRATCH4, R_ECC_SCRATCH4, R_ECC_SCRATCH5; \
	li	R_ECC_SCRATCH5, 4;	\
1:	sd	zero, BUS_L2_ERRORS(R_ECC_SCRATCH4); \
	ld	R_ECC_SCRATCH0, 0(addr);	\
	cache	L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(addr); \
	ld	R_ECC_SCRATCH0, 0(addr);	\
	ld	R_ECC_SCRATCH1, 8(addr);	\
        sne     R_ECC_SCRATCH0, R_ECC_SCRATCH0, pattern0;     \
        or      R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH0; \
	ld	R_ECC_SCRATCH2, 16(addr);\
        sne     R_ECC_SCRATCH1, R_ECC_SCRATCH1, zero;     \
        or      R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH1; \
	ld	R_ECC_SCRATCH3, 24(addr);\
        sne     R_ECC_SCRATCH2, R_ECC_SCRATCH2, zero;     \
        or      R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH2; \
	ld	R_ECC_SCRATCH0, BUS_L2_ERRORS(R_ECC_SCRATCH4); \
        sne     R_ECC_SCRATCH3, R_ECC_SCRATCH3, zero;     \
        or      R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH3; \
        sne     R_ECC_SCRATCH0, R_ECC_SCRATCH0, zero;     \
        or      R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH0; \
	move 	R_ECC_SCRATCH3, pattern0; 	\
	move 	pattern0, pattern1;	\
	move 	pattern1, pattern2;	\
	move 	pattern2, pattern3;	\
	move 	pattern3, R_ECC_SCRATCH3; 	\
	addi 	R_BG_SCRATCH5, R_BG_SCRATCH5, -1; \
	bne	R_BG_SCRATCH5, zero, 1b;   \
	daddu 	addr, addr, R_ECC_NEXT_WAY; \
	li      R_ECC_SCRATCH0, -4*2*65536; \
        dadd	addr, addr, R_ECC_SCRATCH0

#ifdef DATA_TEST
#ifdef DATA_ECC_TEST 
l2dtest_data_ecc:
		
	/*li 	R_ECC_BLOCK, START_BLK*/
	sll	R_ECC_BLOCK, k0, 2
	li	R_ECC_NEXT_WAY,0x20000
ecc_next_block:
#ifdef USE_LEDS
	addi	R_BG_SCRATCH2, R_BG_BLOCK, '0'
	or 	R_BG_SCRATCH2, R_BG_SCRATCH2, ('E' << 8)
	SET_LEDS_HI(R_BG_SCRATCH2, R_BG_SCRATCH0, R_BG_SCRATCH1)
#endif
	
	move	R_ECC_PATT_IND, $0
	dli 	R_ECC_PAT0_0, DATA_FOR_ECC_PATT0
	dli 	R_ECC_PAT0_1, DATA_FOR_ECC_PATT0
	dli 	R_ECC_PAT0_2, DATA_FOR_ECC_PATT0
	dli 	R_ECC_PAT0_3, DATA_FOR_ECC_PATT0
	dli 	R_ECC_PAT1_0, DATA_FOR_ECC_INVPATT0
	dli 	R_ECC_PAT1_1, DATA_FOR_ECC_INVPATT0
	dli 	R_ECC_PAT1_2, DATA_FOR_ECC_INVPATT0
	dli 	R_ECC_PAT1_3, DATA_FOR_ECC_INVPATT0

ecc_next_pattern:
#ifdef USE_LEDS
	addi	R_BG_SCRATCH2, R_ECC_PATT_IND, '0'
	or 	R_BG_SCRATCH2, R_BG_SCRATCH2, ('P' << 8)
	SET_LEDS_LO(R_BG_SCRATCH2, R_BG_SCRATCH0, R_BG_SCRATCH1)
#endif

	dli	R_ECC_WADDR, XKPHYS_C_COH_EXC	/* uncached accelerated */
	dli	R_ECC_SCRATCH0, L2_RAM_BASE_ADDR	/* mgmt mode */
	or	R_ECC_WADDR,R_ECC_WADDR,R_BG_SCRATCH0
	sll	R_ECC_SCRATCH0, R_ECC_BLOCK, L2_BLOCK_SHIFT /* block number */
	or	R_ECC_WADDR, R_ECC_WADDR, R_ECC_SCRATCH0

	
	.set	noreorder
	move 	R_ECC_LINE, zero
ecc_init_next_line:
	ECC_WRITE_PAT(R_ECC_WADDR,R_ECC_PAT0_0,R_ECC_PAT0_1,R_ECC_PAT0_2,R_ECC_PAT0_3)
	li      R_ECC_SCRATCH0, (32)
        dadd	R_ECC_WADDR, R_ECC_WADDR, R_ECC_SCRATCH0	/* next line */

        slt     R_ECC_SCRATCH0,R_ECC_LINE,L2_LINES_PER_BLOCK-1
	bne	R_ECC_SCRATCH0, $0, ecc_init_next_line
	add	R_ECC_LINE, R_ECC_LINE,1
	
	dli	R_ECC_RADDR, XKPHYS_C_COH_EXC
	dli	R_ECC_SCRATCH0, L2_RAM_BASE_ADDR
	or	R_ECC_RADDR, R_ECC_RADDR, R_WRBC_SCRATCH0
	sll	R_ECC_SCRATCH1, R_ECC_BLOCK, L2_BLOCK_SHIFT
	or	R_ECC_RADDR, R_ECC_RADDR, R_ECC_SCRATCH1
	li	R_ECC_NEXT_WAY, 0x20000

	move 	R_ECC_LINE, zero
ecc_march1:
	move	R_PASS_FAIL, zero
	ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT0_0,R_ECC_PAT0_1,R_ECC_PAT0_2,R_ECC_PAT0_3,ecc_err)
	ECC_WRITE_PAT(R_ECC_WADDR,R_ECC_PAT1_0,R_ECC_PAT1_1,R_ECC_PAT1_2,R_ECC_PAT1_3)
	ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT1_0,R_ECC_PAT1_1,R_ECC_PAT1_2,R_ECC_PAT1_3,ecc_err)
	BG_INVAL_L1(R_BG_WADDR) 
	SET_ERR_TABLE(R_PASS_FAIL, R_ECC_LINE)
	daddiu	R_ECC_RADDR, R_ECC_RADDR, 0x20 

        slt     R_ECC_SCRATCH0,R_ECC_LINE,L2_LINES_PER_BLOCK-1
	bne	R_ECC_SCRATCH0, $0, ecc_march1
	add	R_ECC_LINE, R_ECC_LINE,1
	
	dli	R_ECC_RADDR, XKPHYS_C_COH_EXC
	dli	R_ECC_SCRATCH0, L2_RAM_BASE_ADDR
	or	R_ECC_RADDR, R_ECC_RADDR, R_WRBC_SCRATCH0
	sll	R_ECC_SCRATCH1, R_ECC_BLOCK, L2_BLOCK_SHIFT
	or	R_ECC_RADDR, R_ECC_RADDR, R_ECC_SCRATCH1
	li	R_ECC_NEXT_WAY, 0x20000

	move 	R_ECC_LINE, zero
ecc_march2:
	move	R_PASS_FAIL, zero
	ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT1_0,R_ECC_PAT1_1,R_ECC_PAT1_2,R_ECC_PAT1_3,ecc_err)
	ECC_WRITE_PAT(R_ECC_WADDR,R_ECC_PAT0_0,R_ECC_PAT0_1,R_ECC_PAT0_2,R_ECC_PAT0_3)
	ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT0_0,R_ECC_PAT0_1,R_ECC_PAT0_2,R_ECC_PAT0_3,ecc_err)
	BG_INVAL_L1(R_BG_WADDR) 
	SET_ERR_TABLE(R_PASS_FAIL, R_ECC_LINE)
	daddiu	R_ECC_RADDR, R_ECC_RADDR, 0x20 

        slt     R_ECC_SCRATCH0,R_ECC_LINE,L2_LINES_PER_BLOCK-1
	bne	R_ECC_SCRATCH0, $0, ecc_march2
	add	R_ECC_LINE, R_ECC_LINE,1
	
	dli	R_ECC_RADDR, XKPHYS_C_COH_EXC
	dli	R_ECC_SCRATCH0, L2_RAM_BASE_ADDR
	or	R_ECC_RADDR, R_ECC_RADDR, R_ECC_SCRATCH0
        addi    R_ECC_SCRATCH0, R_ECC_BLOCK, 1
#ifdef TEST_ALL_LINES
	sll	R_ECC_SCRATCH1, R_ECC_SCRATCH0, L2_BLOCK_SHIFT
#else 
	sll	R_ECC_SCRATCH1, R_ECC_BLOCK, L2_BLOCK_SHIFT
#endif
	or	R_ECC_RADDR, R_ECC_RADDR, R_ECC_SCRATCH1
#ifdef TEST_ALL_LINES
	daddiu  R_ECC_RADDR, R_ECC_RADDR, -32 
#else 
	daddiu  R_ECC_RADDR, R_ECC_RADDR, L2_LINES_PER_BLOCK*32-32
#endif
	li 	R_ECC_LINE,L2_LINES_PER_BLOCK-1
ecc_march3:
	move	R_PASS_FAIL, zero
	ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT0_0,R_ECC_PAT0_1,R_ECC_PAT0_2,R_ECC_PAT0_3,ecc_err)
	ECC_WRITE_PAT(R_ECC_WADDR,R_ECC_PAT1_0,R_ECC_PAT1_1,R_ECC_PAT1_2,R_ECC_PAT1_3)
	ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT1_0,R_ECC_PAT1_1,R_ECC_PAT1_2,R_ECC_PAT1_3,ecc_err)
	BG_INVAL_L1(R_BG_WADDR) 
	SET_ERR_TABLE(R_PASS_FAIL, R_ECC_LINE)
	daddiu	R_ECC_RADDR, R_ECC_RADDR, -32 

	bne	R_ECC_LINE,$0, ecc_march3
	add	R_ECC_LINE,R_ECC_LINE,-1

	dli	R_ECC_RADDR, XKPHYS_C_COH_EXC
	dli	R_ECC_SCRATCH0, L2_RAM_BASE_ADDR
	or	R_ECC_RADDR, R_ECC_RADDR, R_ECC_SCRATCH0
        addi    R_ECC_SCRATCH0, R_ECC_BLOCK, 1
#ifdef TEST_ALL_LINES
	sll	R_ECC_SCRATCH1, R_ECC_SCRATCH0, L2_BLOCK_SHIFT
#else 
	sll	R_ECC_SCRATCH1, R_ECC_BLOCK, L2_BLOCK_SHIFT
#endif
	or	R_ECC_RADDR, R_ECC_RADDR, R_ECC_SCRATCH1
#ifdef TEST_ALL_LINES
	daddiu  R_ECC_RADDR, R_ECC_RADDR, -32 
#else 
	daddiu  R_ECC_RADDR, R_ECC_RADDR, L2_LINES_PER_BLOCK*32-32
#endif
	li 	R_ECC_LINE,L2_LINES_PER_BLOCK-1
ecc_march4:
	move	R_PASS_FAIL, zero
	ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT1_0,R_ECC_PAT1_1,R_ECC_PAT1_2,R_ECC_PAT1_3,ecc_err)
	ECC_WRITE_PAT(R_ECC_WADDR,R_ECC_PAT0_0,R_ECC_PAT0_1,R_ECC_PAT0_2,R_ECC_PAT0_3)
	ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT0_0,R_ECC_PAT0_1,R_ECC_PAT0_2,R_ECC_PAT0_3,ecc_err)
	BG_INVAL_L1(R_BG_WADDR) 
	SET_ERR_TABLE(R_PASS_FAIL, R_ECC_LINE)
	daddiu	R_ECC_RADDR, R_ECC_RADDR, -32 

	bne	R_ECC_LINE,$0, ecc_march4
	add	R_ECC_LINE,R_ECC_LINE,-1

	addi	R_ECC_PATT_IND, R_ECC_PATT_IND, 1
	li 	R_ECC_SCRATCH0, 1
	bne	R_ECC_SCRATCH0, R_ECC_PATT_IND, 2f
	nop
	dli 	R_ECC_PAT0_0, DATA_FOR_ECC_INVPATT0
	dli 	R_ECC_PAT0_1, DATA_FOR_ECC_PATT0
	dli 	R_ECC_PAT0_2, DATA_FOR_ECC_INVPATT0
	dli 	R_ECC_PAT0_3, DATA_FOR_ECC_PATT0
	dli 	R_ECC_PAT1_0, DATA_FOR_ECC_PATT0
	dli 	R_ECC_PAT1_1, DATA_FOR_ECC_INVPATT0
	dli 	R_ECC_PAT1_2, DATA_FOR_ECC_PATT0
	dli 	R_ECC_PAT1_3, DATA_FOR_ECC_INVPATT0
	b	ecc_next_pattern
2:	
	li 	R_ECC_SCRATCH0, 2
	bne	R_ECC_SCRATCH0, R_ECC_PATT_IND, 3f
	nop
	dli 	R_ECC_PAT0_0, DATA_FOR_ECC_INVPATT0
	dli 	R_ECC_PAT0_1, DATA_FOR_ECC_INVPATT0
	dli 	R_ECC_PAT0_2, DATA_FOR_ECC_PATT0
	dli 	R_ECC_PAT0_3, DATA_FOR_ECC_PATT0
	dli 	R_ECC_PAT1_0, DATA_FOR_ECC_PATT0
	dli 	R_ECC_PAT1_1, DATA_FOR_ECC_PATT0
	dli 	R_ECC_PAT1_2, DATA_FOR_ECC_INVPATT0
	dli 	R_ECC_PAT1_3, DATA_FOR_ECC_INVPATT0
	b	ecc_next_pattern
	nop
3:	
	li 	R_ECC_SCRATCH0, 3
	bne	R_ECC_SCRATCH0, R_ECC_PATT_IND, 4f
	nop
	dli 	R_ECC_PAT0_0, DATA_FOR_ECC_PATT1
	dli 	R_ECC_PAT0_1, DATA_FOR_ECC_PATT1
	dli 	R_ECC_PAT0_2, DATA_FOR_ECC_PATT1
	dli 	R_ECC_PAT0_3, DATA_FOR_ECC_PATT1
	dli 	R_ECC_PAT1_0, DATA_FOR_ECC_INVPATT1
	dli 	R_ECC_PAT1_1, DATA_FOR_ECC_INVPATT1
	dli 	R_ECC_PAT1_2, DATA_FOR_ECC_INVPATT1
	dli 	R_ECC_PAT1_3, DATA_FOR_ECC_INVPATT1
	b	ecc_next_pattern
	nop
4:	
	li 	R_ECC_SCRATCH0, 4
	bne	R_ECC_SCRATCH0, R_ECC_PATT_IND, 5f
	nop
	dli 	R_ECC_PAT0_0, DATA_FOR_ECC_PATT2
	dli 	R_ECC_PAT0_1, DATA_FOR_ECC_PATT2
	dli 	R_ECC_PAT0_2, DATA_FOR_ECC_PATT2
	dli 	R_ECC_PAT0_3, DATA_FOR_ECC_PATT2
	dli 	R_ECC_PAT1_0, DATA_FOR_ECC_INVPATT2
	dli 	R_ECC_PAT1_1, DATA_FOR_ECC_INVPATT2
	dli 	R_ECC_PAT1_2, DATA_FOR_ECC_INVPATT2
	dli 	R_ECC_PAT1_3, DATA_FOR_ECC_INVPATT2
	b	ecc_next_pattern
	nop
5:		
	li 	R_ECC_SCRATCH0, 5
	bne	R_ECC_SCRATCH0, R_ECC_PATT_IND, 6f
	nop
	dli 	R_ECC_PAT0_0, DATA_FOR_ECC_PATT3
	dli 	R_ECC_PAT0_1, DATA_FOR_ECC_PATT3
	dli 	R_ECC_PAT0_2, DATA_FOR_ECC_PATT3
	dli 	R_ECC_PAT0_3, DATA_FOR_ECC_PATT3
	dli 	R_ECC_PAT1_0, DATA_FOR_ECC_INVPATT3
	dli 	R_ECC_PAT1_1, DATA_FOR_ECC_INVPATT3
	dli 	R_ECC_PAT1_2, DATA_FOR_ECC_INVPATT3
	dli 	R_ECC_PAT1_3, DATA_FOR_ECC_INVPATT3
	b	ecc_next_pattern
	nop
6:		
	li 	R_ECC_SCRATCH0, 6
	bne	R_ECC_SCRATCH0, R_ECC_PATT_IND, 7f
	nop
	dli 	R_ECC_PAT0_0, DATA_FOR_ECC_PATT4
	dli 	R_ECC_PAT0_1, DATA_FOR_ECC_PATT4
	dli 	R_ECC_PAT0_2, DATA_FOR_ECC_PATT4
	dli 	R_ECC_PAT0_3, DATA_FOR_ECC_PATT4
	dli 	R_ECC_PAT1_0, DATA_FOR_ECC_INVPATT4
	dli 	R_ECC_PAT1_1, DATA_FOR_ECC_INVPATT4
	dli 	R_ECC_PAT1_2, DATA_FOR_ECC_INVPATT4
	dli 	R_ECC_PAT1_3, DATA_FOR_ECC_INVPATT4
	b	ecc_next_pattern
	nop
7:		

	li	R_BG_SCRATCH0, 2
1:
	dli	R_BG_SCRATCH1, 2 
2:
	daddiu	R_BG_SCRATCH1, R_BG_SCRATCH1, -1
	bne 	R_BG_SCRATCH1, $0, 2b 
	nop
	daddiu	R_BG_SCRATCH0, R_BG_SCRATCH0, -1
	bne 	R_BG_SCRATCH0, $0, 1b
	nop

	dli	R_ECC_RADDR, XKPHYS_C_COH_EXC
	dli	R_ECC_SCRATCH0, L2_RAM_BASE_ADDR
	or	R_ECC_RADDR, R_ECC_RADDR, R_WRBC_SCRATCH0
	sll	R_ECC_SCRATCH1, R_ECC_BLOCK, L2_BLOCK_SHIFT
	or	R_ECC_RADDR, R_ECC_RADDR, R_ECC_SCRATCH1
	li	R_ECC_NEXT_WAY, 0x20000

	move 	R_ECC_LINE,zero
ecc_march5:
	move	R_PASS_FAIL, zero
	ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT0_0,R_ECC_PAT0_1,R_ECC_PAT0_2,R_ECC_PAT0_3,ecc_err)
	ECC_WRITE_PAT(R_ECC_WADDR,R_ECC_PAT1_0,R_ECC_PAT1_1,R_ECC_PAT1_2,R_ECC_PAT1_3)
	SET_ERR_TABLE(R_PASS_FAIL, R_ECC_LINE)
	daddiu	R_ECC_RADDR, R_ECC_RADDR, 0x20 

        slt     R_ECC_SCRATCH0,R_ECC_LINE,L2_LINES_PER_BLOCK-1
	bne	R_ECC_SCRATCH0, $0, ecc_march5
	add	R_ECC_LINE, R_ECC_LINE,1
	
	dli	R_ECC_RADDR, XKPHYS_C_COH_EXC
	dli	R_ECC_SCRATCH0, L2_RAM_BASE_ADDR
	or	R_ECC_RADDR, R_ECC_RADDR, R_WRBC_SCRATCH0
	sll	R_ECC_SCRATCH1, R_ECC_BLOCK, L2_BLOCK_SHIFT
	or	R_ECC_RADDR, R_ECC_RADDR, R_ECC_SCRATCH1
	li	R_ECC_NEXT_WAY, 0x20000

	li	R_BG_SCRATCH0, 2
1:
	dli	R_BG_SCRATCH1, 2 
2:
	daddiu	R_BG_SCRATCH1, R_BG_SCRATCH1, -1
	bne 	R_BG_SCRATCH1, $0, 2b 
	nop
	daddiu	R_BG_SCRATCH0, R_BG_SCRATCH0, -1
	bne 	R_BG_SCRATCH0, $0, 1b
	nop

	move 	R_ECC_LINE,zero
ecc_march6:
	move	R_PASS_FAIL, zero
	ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT1_0,R_ECC_PAT1_1,R_ECC_PAT1_2,R_ECC_PAT1_3,ecc_err)
	SET_ERR_TABLE(R_PASS_FAIL, R_ECC_LINE)
	daddiu	R_ECC_RADDR, R_ECC_RADDR, 0x20 

        slt     R_ECC_SCRATCH0,R_ECC_LINE,L2_LINES_PER_BLOCK-1
	bne	R_ECC_SCRATCH0, $0, ecc_march6
	add	R_ECC_LINE, R_ECC_LINE,1
	
        /* if error, put test block info into s0 and return */
	or 	R_BG_SCRATCH0, R_ERR_TABLE_0, R_ERR_TABLE_1
	or	R_BG_SCRATCH0, R_BG_SCRATCH0, R_ERR_TABLE_2
	or	R_BG_SCRATCH0, R_BG_SCRATCH0, R_ERR_TABLE_3
	beq	R_BG_SCRATCH0, zero, 1f