📄 diag_l2cache.s
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bne R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_1 dli R_BG_PAT0_0, DATA_PATTERN1_0 # data_pattern = pattern[0] dli R_BG_PAT0_1, DATA_PATTERN1_1 dli R_BG_PAT0_2, DATA_PATTERN1_2 dli R_BG_PAT0_3, DATA_PATTERN1_3 dli R_INV_0, PATTERN1_INV0 dli R_INV_1, PATTERN1_INV1 j test_0 noppattern_ne_1: li R_BG_SCRATCH0, 2 bne R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_2 dli R_BG_PAT0_0, DATA_PATTERN2_0 # data_pattern = pattern[0] dli R_BG_PAT0_1, DATA_PATTERN2_1 dli R_BG_PAT0_2, DATA_PATTERN2_2 dli R_BG_PAT0_3, DATA_PATTERN2_3 dli R_INV_0, PATTERN2_INV0 dli R_INV_1, PATTERN2_INV1 j test_0 noppattern_ne_2: li R_BG_SCRATCH0, 3 bne R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_3 dli R_BG_PAT0_0, DATA_PATTERN3_0 # data_pattern = pattern[0] dli R_BG_PAT0_1, DATA_PATTERN3_1 dli R_BG_PAT0_2, DATA_PATTERN3_2 dli R_BG_PAT0_3, DATA_PATTERN3_3 dli R_INV_0, PATTERN3_INV0 dli R_INV_1, PATTERN3_INV1 j test_0 noppattern_ne_3: li R_BG_SCRATCH0, 4 bne R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_4 dli R_BG_PAT0_0, DATA_PATTERN4_0 # data_pattern = pattern[0] dli R_BG_PAT0_1, DATA_PATTERN4_1 dli R_BG_PAT0_2, DATA_PATTERN4_2 dli R_BG_PAT0_3, DATA_PATTERN4_3 dli R_INV_0, PATTERN4_INV0 dli R_INV_1, PATTERN4_INV1 j test_0 noppattern_ne_4: li R_BG_SCRATCH0, 5 bne R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_5 dli R_BG_PAT0_0, DATA_PATTERN5_0 # data_pattern = pattern[0] dli R_BG_PAT0_1, DATA_PATTERN5_1 dli R_BG_PAT0_2, DATA_PATTERN5_2 dli R_BG_PAT0_3, DATA_PATTERN5_3 dli R_INV_0, PATTERN5_INV0 dli R_INV_1, PATTERN5_INV1 j test_0 noppattern_ne_5: li R_BG_SCRATCH0, 6 bne R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_6 dli R_BG_PAT0_0, DATA_PATTERN6_0 # data_pattern = pattern[0] dli R_BG_PAT0_1, DATA_PATTERN6_1 dli R_BG_PAT0_2, DATA_PATTERN6_2 dli R_BG_PAT0_3, DATA_PATTERN6_3 dli R_INV_0, PATTERN6_INV0 dli R_INV_1, PATTERN6_INV1 j test_0 noppattern_ne_6: li R_BG_SCRATCH0, 7 bne R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_7 dli R_BG_PAT0_0, DATA_PATTERN7_0 # data_pattern = pattern[0] dli R_BG_PAT0_1, DATA_PATTERN7_1 dli R_BG_PAT0_2, DATA_PATTERN7_2 dli R_BG_PAT0_3, DATA_PATTERN7_3 dli R_INV_0, PATTERN7_INV0 dli R_INV_1, PATTERN7_INV1 j test_0 noppattern_ne_7: li R_BG_SCRATCH0, 8 bne R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_8 dli R_BG_PAT0_0, DATA_PATTERN8_0 # data_pattern = pattern[0] dli R_BG_PAT0_1, DATA_PATTERN8_1 dli R_BG_PAT0_2, DATA_PATTERN8_2 dli R_BG_PAT0_3, DATA_PATTERN8_3 dli R_INV_0, PATTERN8_INV0 dli R_INV_1, PATTERN8_INV1 j test_0 noppattern_ne_8: li R_BG_SCRATCH0, 9 bne R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_9 dli R_BG_PAT0_0, DATA_PATTERN9_0 # data_pattern = pattern[0] dli R_BG_PAT0_1, DATA_PATTERN9_1 dli R_BG_PAT0_2, DATA_PATTERN9_2 dli R_BG_PAT0_3, DATA_PATTERN9_3 dli R_INV_0, PATTERN9_INV0 dli R_INV_1, PATTERN9_INV1 j test_0 noppattern_ne_9: dli R_BG_PAT0_0, DATA_PATTERNa_0 # data_pattern = pattern[0] dli R_BG_PAT0_1, DATA_PATTERNa_1 dli R_BG_PAT0_2, DATA_PATTERNa_2 dli R_BG_PAT0_3, DATA_PATTERNa_3 dli R_INV_0, PATTERNa_INV0 dli R_INV_1, PATTERNa_INV1 j test_0 nop test_0: dli R_BG_WADDR, XKPHYS_C_COH_EXC /* uncached accelerated */ dli R_BG_SCRATCH0, L2_RAM_BASE_ADDR /* mgmt mode */ or R_BG_WADDR,R_BG_WADDR,R_BG_SCRATCH0 sll R_BG_SCRATCH0, R_BG_BLOCK, L2_BLOCK_SHIFT /* block number */ or R_BG_WADDR, R_BG_WADDR, R_BG_SCRATCH0 .set noreorder move R_BG_LINE, zerobg_init_next_line: /*BG_WRITE_PAT0(R_BG_WADDR) */ BG_WRITE_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) /* for (line = 0; line < max_lines_per_block; line++) */ .set noreorder li R_BG_SCRATCH0, (32) dadd R_BG_WADDR, R_BG_WADDR, R_BG_SCRATCH0 /* next line */ slt R_BG_SCRATCH0,R_BG_LINE,L2_LINES_PER_BLOCK-1 bne R_BG_SCRATCH0,$0, bg_init_next_line add R_BG_LINE,R_BG_LINE,1 /* march element 1 */ dli R_WRBC_RADDR, XKPHYS_C_COH_EXC dli R_WRBC_SCRATCH0, L2_RAM_BASE_ADDR or R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH0 /* form address for block to be read/written */ sll R_WRBC_SCRATCH1, R_WRBC_RBLK, L2_BLOCK_SHIFT or R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH1 li R_WRBC_NEXT_WAY, 0x20000 /* way = 0; */ /* for (line = 0; line < lines_per_block; line++) {*/ move R_BG_LINE, zeromarch1_w0: move R_PASS_FAIL, zero BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3) BG_WRITE_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) BG_INVAL_L1(R_BG_WADDR) INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3) SET_ERR_TABLE(R_PASS_FAIL, R_WRBC_LINE) daddiu R_WRBC_RADDR, R_WRBC_RADDR, 0x20 slt R_BG_SCRATCH0,R_BG_LINE,L2_LINES_PER_BLOCK-1 bne R_BG_SCRATCH0,$0,march1_w0 add R_BG_LINE,R_BG_LINE,1/* march element 2 */ dli R_WRBC_RADDR, XKPHYS_C_COH_EXC dli R_WRBC_SCRATCH0, L2_RAM_BASE_ADDR or R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH0 /* form address for block to be read/written */ sll R_WRBC_SCRATCH1, R_WRBC_RBLK, L2_BLOCK_SHIFT or R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH1 li R_WRBC_NEXT_WAY, 0x20000 /* way = 0; */ /* for (line = 0; line < lines_per_block; line++) {*/ move R_BG_LINE,zeromarch2_w0: move R_PASS_FAIL, zero INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3) BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3) BG_WRITE_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) BG_INVAL_L1(R_BG_WADDR) SET_ERR_TABLE(R_PASS_FAIL, R_WRBC_LINE) daddiu R_WRBC_RADDR, R_WRBC_RADDR, 0x20 slt R_BG_SCRATCH0,R_BG_LINE,L2_LINES_PER_BLOCK-1 bne R_BG_SCRATCH0,$0,march2_w0 add R_BG_LINE,R_BG_LINE,1/* march element 3 */ dli R_WRBC_RADDR, XKPHYS_C_COH_EXC dli R_WRBC_SCRATCH0, L2_RAM_BASE_ADDR or R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH0 /* form address for block to be read/written */ addi R_WRBC_SCRATCH0, R_WRBC_RBLK, 1#ifdef TEST_ALL_LINES sll R_WRBC_SCRATCH1, R_WRBC_SCRATCH0, L2_BLOCK_SHIFT#else sll R_WRBC_SCRATCH1, R_WRBC_RBLK, L2_BLOCK_SHIFT#endif or R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH1#ifdef TEST_ALL_LINES daddiu R_WRBC_RADDR, R_WRBC_RADDR, -32 #else daddiu R_WRBC_RADDR, R_WRBC_RADDR, L2_LINES_PER_BLOCK*32-32#endif li R_WRBC_NEXT_WAY, 0x20000 /* way = 0; */ /* for (line = 0; line < lines_per_block; line++) {*/ li R_WRBC_LINE,L2_LINES_PER_BLOCK-1march3_w0: move R_PASS_FAIL, zero BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3) BG_WRITE_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) BG_INVAL_L1(R_BG_WADDR) INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3) SET_ERR_TABLE(R_PASS_FAIL, R_WRBC_LINE) daddiu R_WRBC_RADDR, R_WRBC_RADDR, -32 bne R_WRBC_LINE,$0, march3_w0 add R_WRBC_LINE,R_WRBC_LINE,-1/* march element 4 */ dli R_WRBC_RADDR, XKPHYS_C_COH_EXC dli R_WRBC_SCRATCH0, L2_RAM_BASE_ADDR or R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH0 /* form address for block to be read/written */ addi R_WRBC_SCRATCH0, R_WRBC_RBLK, 1#ifdef TEST_ALL_LINES sll R_WRBC_SCRATCH1, R_WRBC_SCRATCH0, L2_BLOCK_SHIFT#else sll R_WRBC_SCRATCH1, R_WRBC_RBLK, L2_BLOCK_SHIFT#endif or R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH1#ifdef TEST_ALL_LINES daddiu R_WRBC_RADDR, R_WRBC_RADDR, -32 #else daddiu R_WRBC_RADDR, R_WRBC_RADDR, L2_LINES_PER_BLOCK*32-32#endif li R_WRBC_NEXT_WAY, 0x20000 /* way = 0; */ /* for (line = 0; line < lines_per_block; line++) {*/ li R_WRBC_LINE,L2_LINES_PER_BLOCK-1march4_w0: move R_PASS_FAIL, zero INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3) BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3) BG_WRITE_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) BG_INVAL_L1(R_BG_WADDR) SET_ERR_TABLE(R_PASS_FAIL, R_WRBC_LINE) daddiu R_WRBC_RADDR, R_WRBC_RADDR, -32 bne R_WRBC_LINE,$0, march4_w0 add R_WRBC_LINE,R_WRBC_LINE,-1/* bne R_BG_PAT0_0, $0, 0f nop dli R_BG_PAT0_0, 0x5555555555555555 move R_BG_PAT0_1, R_BG_PAT0_0 move R_BG_PAT0_2, R_BG_PAT0_0 move R_BG_PAT0_3, R_BG_PAT0_0 b bg_next_patt nop0: beq R_BG_PAT0_2, $0, 3f nop bne R_BG_PAT0_3, $0, 4f nop move R_BG_PAT0_1, R_BG_PAT0_0 move R_BG_PAT0_2, R_BG_PAT0_3 b bg_next_patt4: dli R_BG_SCRATCH2, 0 move R_BG_SCRATCH0, R_BG_PAT0_01: dsrl R_BG_SCRATCH0, R_BG_SCRATCH0, 1 and R_BG_SCRATCH1, R_BG_SCRATCH0, 1 addi R_BG_SCRATCH2, R_BG_SCRATCH2, 1 bne R_BG_SCRATCH1, $0, 1b nop dsll R_BG_SCRATCH2, R_BG_SCRATCH2, 1 bne R_BG_SCRATCH2, 0x40, 6f dli R_BG_PAT0_0, -1 move R_BG_PAT0_1, $0 move R_BG_PAT0_2, R_BG_PAT0_0 move R_BG_PAT0_3, $0 b bg_next_patt 6: dli R_BG_SCRATCH3, 1 dsll R_BG_SCRATCH3, R_BG_SCRATCH3, R_BG_SCRATCH2 daddiu R_BG_SCRATCH3, R_BG_SCRATCH3, -1 dsll R_BG_SCRATCH2, R_BG_SCRATCH2, 1 move R_BG_PAT0_0, R_BG_SCRATCH3 beq R_BG_SCRATCH2, 0x40, 5f2: dsll R_BG_SCRATCH3, R_BG_SCRATCH3, R_BG_SCRATCH2 or R_BG_PAT0_0, R_BG_PAT0_0, R_BG_SCRATCH3 bne R_BG_SCRATCH3, $0, 2b nop5: move R_BG_PAT0_1, R_BG_PAT0_0 move R_BG_PAT0_2, R_BG_PAT0_0 move R_BG_PAT0_3, R_BG_PAT0_0 b bg_next_patt nop3:*/ addu R_PATTERN_IND, R_PATTERN_IND, 1 slt R_BG_SCRATCH0, R_PATTERN_IND, MAX_PATTERN bne R_BG_SCRATCH0, $0, bg_next_patt li R_BG_SCRATCH0, 21: dli R_BG_SCRATCH1, 2 2: daddiu R_BG_SCRATCH1, R_BG_SCRATCH1, -1 bne R_BG_SCRATCH1, $0, 2b nop daddiu R_BG_SCRATCH0, R_BG_SCRATCH0, -1 bne R_BG_SCRATCH0, $0, 1b nop/* march element 5 */ dli R_WRBC_RADDR, XKPHYS_C_COH_EXC dli R_WRBC_SCRATCH0, L2_RAM_BASE_ADDR or R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH0 /* form address for block to be read/written */ sll R_WRBC_SCRATCH1, R_WRBC_RBLK, L2_BLOCK_SHIFT or R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH1 li R_WRBC_NEXT_WAY, 0x20000 move R_WRBC_LINE,zeromarch5_w0: move R_PASS_FAIL, zero BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3) BG_WRITE_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3) SET_ERR_TABLE(R_PASS_FAIL, R_WRBC_LINE) daddiu R_WRBC_RADDR, R_WRBC_RADDR, 32 slt R_BG_SCRATCH0,R_BG_LINE,L2_LINES_PER_BLOCK-1 bne R_BG_SCRATCH0,$0,march5_w0 add R_BG_LINE,R_BG_LINE,1 li R_BG_SCRATCH0, 21: dli R_BG_SCRATCH1, 2 2: daddiu R_BG_SCRATCH1, R_BG_SCRATCH1, -1 bne R_BG_SCRATCH1, $0, 2b nop daddiu R_BG_SCRATCH0, R_BG_SCRATCH0, -1 bne R_BG_SCRATCH0, $0, 1b nop/* march element 6 */ dli R_WRBC_RADDR, XKPHYS_C_COH_EXC dli R_WRBC_SCRATCH0, L2_RAM_BASE_ADDR or R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH0 /* form address for block to be read/written */ sll R_WRBC_SCRATCH1, R_WRBC_RBLK, L2_BLOCK_SHIFT or R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH1 li R_WRBC_NEXT_WAY, 0x20000 move R_WRBC_LINE,zeromarch6_w0: move R_PASS_FAIL, zero INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3) BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1) INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3) SET_ERR_TABLE(R_PASS_FAIL, R_WRBC_LINE) daddiu R_WRBC_RADDR, R_WRBC_RADDR, 32 slt R_BG_SCRATCH0,R_BG_LINE,L2_LINES_PER_BLOCK-1 bne R_BG_SCRATCH0,$0,march6_w0 add R_BG_LINE,R_BG_LINE,1 /* if error, put test block info into s0 and return */ or R_BG_SCRATCH0, R_ERR_TABLE_0, R_ERR_TABLE_1 or R_BG_SCRATCH0, R_BG_SCRATCH0, R_ERR_TABLE_2 or R_BG_SCRATCH0, R_BG_SCRATCH0, R_ERR_TABLE_3 beq R_BG_SCRATCH0, zero, 1f nop move s0, R_BG_BLOCK or s0, s0, 1 << 8 jr ra nop1: addu R_BG_BLOCK,R_BG_BLOCK,1 /*slt R_BG_SCRATCH0, R_BG_BLOCK, (L2_BLOCKS_PER_ROW * L2_BLOCK_ROWS)*/ addi R_BG_SCRATCH1, k0, 1 sll R_BG_SCRATCH1, R_BG_SCRATCH1, 2 /*slt R_BG_SCRATCH0, R_BG_BLOCK, (START_BLK + TOTAL_BLKS)*/ slt R_BG_SCRATCH0, R_BG_BLOCK, R_BG_SCRATCH1 bne R_BG_SCRATCH0,$0, bg_next_block nop .set noreorder jr ra nopbg_err: li v0, 1 jr ra nop#endif#define SCD_BW_BASE 0x0010020880#define L2_BASE 0x0010040000#define L2_READ_TAG 0x18#define L2_ECC_TAG 0x38#define BUS_ERR_STATUS 0x00#define BUS_L2_ERRORS 0x40#define R_ECC_PAT0_0 a0 #define R_ECC_PAT0_1 a1 #define R_ECC_PAT0_2 a2 #define R_ECC_PAT0_3 a3 #define R_ECC_PAT1_0 t0 #define R_ECC_PAT1_1 t1 #define R_ECC_PAT1_2 t2 #define R_ECC_PAT1_3 t3 #define R_ECC_PATT_IND s0#define R_ECC_LINE s2 ⌨️ 快捷键说明
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