el3c90xend.h

3C90X驱动源码

#define EL_MEDIAOPT_MII		0x0040	/* MII */
#define EL_MEDIAOPT_VCO		0x0100	/* 1st gen chip only */

#define EL_MEDIAOPT_10FL	0x0100	/* 3x905B only, on-chip */
#define EL_MEDIAOPT_MASK	0x01FF

/* window 4 (diagnostics) */

#define EL_W4_UPPERBYTESOK	0x0D
#define EL_W4_BADSSD		0x0C
#define EL_W4_MEDIA_STATUS	0x0A
#define EL_W4_PHY_MGMT		0x08
#define EL_W4_NET_DIAG		0x06
#define EL_W4_FIFO_DIAG		0x04
#define EL_W4_VCO_DIAG		0x02

#define EL_W4_CTRLR_STAT	0x08
#define EL_W4_TX_DIAG		0x00

#define EL_MII_CLK		0x01
#define EL_MII_DATA		0x02
#define EL_MII_DIR		0x04

#define EL_MEDIA_SQE		0x0008
#define EL_MEDIA_10TP		0x00C0
#define EL_MEDIA_LNK		0x0080
#define EL_MEDIA_LNKBEAT	0x0800

#define EL_MEDIASTAT_CRCSTRIP	0x0004
#define EL_MEDIASTAT_SQEENB	0x0008
#define EL_MEDIASTAT_COLDET	0x0010
#define EL_MEDIASTAT_CARRIER	0x0020
#define EL_MEDIASTAT_JABGUARD	0x0040
#define EL_MEDIASTAT_LINKBEAT	0x0080
#define EL_MEDIASTAT_JABDETECT	0x0200
#define EL_MEDIASTAT_POLREVERS	0x0400
#define EL_MEDIASTAT_LINKDETECT	0x0800
#define EL_MEDIASTAT_TXINPROG	0x1000
#define EL_MEDIASTAT_DCENB	0x4000
#define EL_MEDIASTAT_AUIDIS	0x8000

#define EL_NETDIAG_TEST_LOWVOLT		0x0001
#define EL_NETDIAG_ASIC_REVMASK		(0x0002|0x0004|0x0008|0x0010|0x0020)
#define EL_NETDIAG_UPPER_BYTES_ENABLE	0x0040
#define EL_NETDIAG_STATS_ENABLED	0x0080
#define EL_NETDIAG_TX_FATALERR		0x0100
#define EL_NETDIAG_TRANSMITTING		0x0200
#define EL_NETDIAG_RX_ENABLED		0x0400
#define EL_NETDIAG_TX_ENABLED		0x0800
#define EL_NETDIAG_FIFO_LOOPBACK	0x1000
#define EL_NETDIAG_MAC_LOOPBACK		0x2000
#define EL_NETDIAG_ENDEC_LOOPBACK	0x4000
#define EL_NETDIAG_EXTERNAL_LOOP	0x8000

/* window 5 */

#define EL_W5_STAT_ENB		0x0C
#define EL_W5_INTR_ENB		0x0A
#define EL_W5_RECLAIM_THRESH	0x09	/* 3c905B only */
#define EL_W5_RX_FILTER		0x08
#define EL_W5_RX_EARLYTHRESH	0x06
#define EL_W5_TX_AVAILTHRESH	0x02
#define EL_W5_TX_STARTTHRESH	0x00

/* RX filter bits */
#define EL_RXFILTER_INDIVIDUAL	0x01
#define EL_RXFILTER_ALLMULTI	0x02
#define EL_RXFILTER_BROADCAST	0x04
#define EL_RXFILTER_ALLFRAMES	0x08
#define EL_RXFILTER_MULTIHASH	0x10 /* 3c905B only */

/* window 6 (stats) */
#define EL_W6_TX_BYTES_OK	0x0C
#define EL_W6_RX_BYTES_OK	0x0A
#define EL_W6_UPPER_FRAMES_OK	0x09
#define EL_W6_DEFERRED		0x08
#define EL_W6_RX_OK		0x07
#define EL_W6_TX_OK		0x06
#define EL_W6_RX_OVERRUN	0x05
#define EL_W6_COL_LATE		0x04
#define EL_W6_COL_SINGLE	0x03
#define EL_W6_COL_MULTIPLE	0x02
#define EL_W6_SQE_ERRORS	0x01
#define EL_W6_CARRIER_LOST	0x00

/* window 7 (bus master control) */
#define EL_W7_BM_ADDR		0x00
#define EL_W7_BM_LEN		0x06
#define EL_W7_BM_STATUS		0x0B
#define EL_W7_BM_TIMEr		0x0A

/* bus master control registers */

#define EL_BM_PKTSTAT		0x20
#define EL_BM_DOWNLISTPTR	0x24
#define EL_BM_FRAGADDR		0x28
#define EL_BM_FRAGLEN		0x2C
#define EL_BM_TXFREETHRESH	0x2F
#define EL_BM_UPPKTSTAT		0x30
#define EL_BM_UPLISTPTR		0x38

#define EL_LAST_FRAG		0x80000000

/* descriptor registers and defines */    

#define EL_MAXFRAGS		63
#define EL_MIN_FRAMELEN		60

#define EL_RXSTAT_LENMASK	0x00001FFF	/* bits 0 to 12 length mask */
#define EL_RXSTAT_UP_ERROR	0x00004000
#define EL_RXSTAT_UP_CMPLT	0x00008000
#define EL_RXSTAT_UP_OVERRUN	0x00010000
#define EL_RXSTAT_RUNT		0x00020000
#define EL_RXSTAT_ALIGN		0x00040000
#define EL_RXSTAT_CRC		0x00080000
#define EL_RXSTAT_OVERSIZE	0x00100000
#define EL_RXSTAT_DRIBBLE	0x00800000
#define EL_RXSTAT_UP_OFLOW	0x01000000
#define EL_RXSTAT_IPCKERR	0x02000000	/* 3c905B only */
#define EL_RXSTAT_TCPCKERR	0x04000000	/* 3c905B only */
#define EL_RXSTAT_UDPCKERR	0x08000000	/* 3c905B only */
#define EL_RXSTAT_BUFEN		0x10000000	/* 3c905B only */
#define EL_RXSTAT_IPCKOK	0x20000000	/* 3c905B only */
#define EL_RXSTAT_TCPCOK	0x40000000	/* 3c905B only */
#define EL_RXSTAT_UDPCKOK	0x80000000	/* 3c905B only */

#define EL_TXSTAT_LENMASK	0x00001FFF	/* bits 0 to 12 length mask */
#define EL_TXSTAT_CRCDIS	0x00002000
#define EL_TXSTAT_TX_INTR	0x00008000
#define EL_TXSTAT_DL_COMPLETE	0x00010000
#define EL_TXSTAT_IPCKSUM	0x02000000	/* 3c905B only */
#define EL_TXSTAT_TCPCKSUM	0x04000000	/* 3c905B only */
#define EL_TXSTAT_UDPCKSUM	0x08000000	/* 3c905B only */
#define EL_TXSTAT_DL_INTR	0x80000000

#define EL_CAPABILITY_BM	0x20

/* MII constants */
    
#define EL_MII_STARTDELIM	0x01
#define EL_MII_READOP		0x02
#define EL_MII_WRITEOP		0x01
#define EL_MII_TURNAROUND	0x02

/*
 * The 3C905B adapters implement a few features that we want to
 * take advantage of, namely the multicast hash filter. With older
 * chips, you only have the option of turning on reception of all
 * multicast frames.
 */
    
#define EL_TYPE_905B	1
#define EL_TYPE_90X	2
#define EL_TIMEOUT		1000

/* General constants . 3Com PCI vendor ID */

#define	TC_VENDORID		0x10B7

/* 3Com chip device IDs.*/
            
#define	TC_DEVICEID_BOOMERANG_10BT		0x9000
#define TC_DEVICEID_BOOMERANG_10BT_COMBO	0x9001
#define TC_DEVICEID_BOOMERANG_10_100BT		0x9050
#define TC_DEVICEID_BOOMERANG_100BT4		0x9051
#define TC_DEVICEID_CYCLONE_10BT		0x9004
#define TC_DEVICEID_CYCLONE_10BT_COMBO		0x9005
#define TC_DEVICEID_CYCLONE_10_100BT		0x9055
#define TC_DEVICEID_CYCLONE_10_100BT4		0x9056
#define TC_DEVICEID_CYCLONE_10_100FX		0x905A
#define TC_DEVICEID_CYCLONE_10_100BT_SERV	0x9800

/*
 * Texas Instruments PHY identifiers
 *
 * The ThunderLAN manual has a curious and confusing error in it.
 * In chapter 7, which describes PHYs, it says that TI PHYs have
 * the following ID codes, where xx denotes a revision:
 *
 * 0x4000501xx			internal 10baseT PHY
 * 0x4000502xx			TNETE211 100VG-AnyLan PMI
 *
 * The problem here is that these are not valid 32-bit hex numbers:
 * there's one digit too many. My guess is that they mean the internal
 * 10baseT PHY is 0x4000501x and the TNETE211 is 0x4000502x since these
 * are the only numbers that make sense.
 */
#define TI_PHY_VENDORID		0x4000
#define TI_PHY_10BT		0x501F
#define TI_PHY_100VGPMI		0x502F

/*
 * These ID values are for the NS DP83840A 10/100 PHY
 */
#define NS_PHY_VENDORID		0x2000
#define NS_PHY_83840A		0x5C0F

/*
 * Level 1 10/100 PHY
 */
#define LEVEL1_PHY_VENDORID	0x7810
#define LEVEL1_PHY_LXT970	0x000F

/*
 * Intel 82555 10/100 PHY
 */
#define INTEL_PHY_VENDORID	0x0A28
#define INTEL_PHY_82555		0x015F

/*
 * SEEQ 80220 10/100 PHY
 */
#define SEEQ_PHY_VENDORID	0x0016
#define SEEQ_PHY_80220		0xF83F


/*
 * PCI low memory base and low I/O base register, and
 * other PCI registers. Note: some are only available on
 * the 3c905B, in particular those that related to power management.
 */

#define EL_PCI_VENDOR_ID	0x00
#define EL_PCI_DEVICE_ID	0x02
#define EL_PCI_COMMAND		0x04
#define EL_PCI_STATUS		0x06
#define EL_PCI_CLASSCODE	0x09
#define EL_PCI_LATENCY_TIMER	0x0D
#define EL_PCI_HEADER_TYPE	0x0E
#define EL_PCI_LOIO		0x10
#define EL_PCI_LOMEM		0x14
#define EL_PCI_BIOSROM		0x30
#define EL_PCI_INTLINE		0x3C
#define EL_PCI_INTPIN		0x3D
#define EL_PCI_MINGNT		0x3E
#define EL_PCI_MINLAT		0x0F
#define EL_PCI_RESETOPT		0x48
#define EL_PCI_EEPROM_DATA	0x4C

/* 3c905B-only registers */
#define EL_PCI_CAPID		0xDC /* 8 bits */
#define EL_PCI_NEXTPTR		0xDD /* 8 bits */
#define EL_PCI_PWRMGMTCAP	0xDE /* 16 bits */
#define EL_PCI_PWRMGMTCTRL	0xE0 /* 16 bits */

#define EL_PSTATE_MASK		0x0003
#define EL_PSTATE_D0		0x0000
#define EL_PSTATE_D1		0x0002
#define EL_PSTATE_D2		0x0002
#define EL_PSTATE_D3		0x0003
#define EL_PME_EN		0x0010
#define EL_PME_STATUS		0x8000

#define PHY_UNKNOWN		6

#define EL_PHYADDR_MIN		0x00
#define EL_PHYADDR_MAX		0x1F

#define EL_PHY_GENCTL		0x00
#define EL_PHY_GENSTS		0x01
#define EL_PHY_VENID		0x02
#define EL_PHY_DEVID		0x03
#define EL_PHY_ANAR		0x04
#define EL_PHY_LPAR		0x05
#define EL_PHY_ANEXP		0x06

#define PHY_ANAR_NEXTPAGE	0x8000
#define PHY_ANAR_RSVD0		0x4000
#define PHY_ANAR_TLRFLT		0x2000
#define PHY_ANAR_RSVD1		0x1000
#define PHY_ANAR_RSVD2		0x0800
#define PHY_ANAR_RSVD3		0x0400
#define PHY_ANAR_100BT4		0x0200
#define PHY_ANAR_100BTXFULL	0x0100
#define PHY_ANAR_100BTXHALF	0x0080
#define PHY_ANAR_10BTFULL	0x0040
#define PHY_ANAR_10BTHALF	0x0020
#define PHY_ANAR_PROTO4		0x0010
#define PHY_ANAR_PROTO3		0x0008
#define PHY_ANAR_PROTO2		0x0004
#define PHY_ANAR_PROTO1		0x0002
#define PHY_ANAR_PROTO0		0x0001

/*
 * These are the register definitions for the PHY (physical layer
 * interface chip).
 */

/*
 * PHY BMCR Basic Mode Control Register
 */

#define PHY_BMCR		0x00
#define PHY_BMCR_RESET		0x8000
#define PHY_BMCR_LOOPBK		0x4000
#define PHY_BMCR_SPEEDSEL	0x2000
#define PHY_BMCR_AUTONEGENBL	0x1000
#define PHY_BMCR_RSVD0		0x0800	/* write as zero */
#define PHY_BMCR_ISOLATE	0x0400
#define PHY_BMCR_AUTONEGRSTR	0x0200
#define PHY_BMCR_DUPLEX		0x0100
#define PHY_BMCR_COLLTEST	0x0080
#define PHY_BMCR_RSVD1		0x0040	/* write as zero, don't care */
#define PHY_BMCR_RSVD2		0x0020	/* write as zero, don't care */
#define PHY_BMCR_RSVD3		0x0010	/* write as zero, don't care */
#define PHY_BMCR_RSVD4		0x0008	/* write as zero, don't care */
#define PHY_BMCR_RSVD5		0x0004	/* write as zero, don't care */
#define PHY_BMCR_RSVD6		0x0002	/* write as zero, don't care */
#define PHY_BMCR_RSVD7		0x0001	/* write as zero, don't care */

/*
 * RESET: 1 == software reset, 0 == normal operation
 * Resets status and control registers to default values.
 * Relatches all hardware config values.
 *
 * LOOPBK: 1 == loopback operation enabled, 0 == normal operation
 *
 * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
 * Link speed is selected byt his bit or if auto-negotiation if bit
 * 12 (AUTONEGENBL) is set (in which case the value of this register
 * is ignored).
 *
 * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
 * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
 * determine speed and mode. Should be cleared and then set if PHY configured
 * for no autoneg on startup.
 *
 * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
 *
 * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
 *
 * DUPLEX: 1 == full duplex mode, 0 == half duplex mode
 *
 * COLLTEST: 1 == collision test enabled, 0 == normal operation
 */

/* 
 * PHY, BMSR Basic Mode Status Register