el3c90xend.h

3C90X驱动源码

/* el3c90xEnd.h - 3Com EtherLink PCI XL END network interface header*/ 

/* Copyright 1999 Wind River Systems, Inc. */

/*
modification history
--------------------
01a,11jan99,mtl	 written by teamF1 Inc.
*/

#ifndef __INCel3c90xEndh
#define __INCel3c90xEndh

#ifdef __cplusplus
extern "C" {
#endif
    
#ifndef _ASMLANGUAGE

#if FALSE
#define DRV_DEBUG	/* temporary should be taken out */
#endif    
    
#ifdef	DRV_DEBUG
#include "logLib.h"
#define DRV_DEBUG_OFF		0x0000
#define DRV_DEBUG_RX		0x0001
#define	DRV_DEBUG_TX		0x0002
#define DRV_DEBUG_INT		0x0004
#define	DRV_DEBUG_POLL		(DRV_DEBUG_POLL_RX | DRV_DEBUG_POLL_TX)
#define	DRV_DEBUG_POLL_RX	0x0008
#define	DRV_DEBUG_POLL_TX	0x0010
#define	DRV_DEBUG_LOAD		0x0020
#define	DRV_DEBUG_LOAD2		0x0040
#define	DRV_DEBUG_IOCTL		0x0080
#define	DRV_DEBUG_RESET		0x0100
#define	DRV_DEBUG_MCAST		0x0200
#define	DRV_DEBUG_CSR		0x0400
#define DRV_DEBUG_RX_PKT        0x0800
#define DRV_DEBUG_POLL_REDIR	0x10000
#define	DRV_DEBUG_LOG_NVRAM	0x20000
#define DRV_DEBUG_ALL           0xfffff
#endif /* DRV_DEBUG */
    

/* configuration items */

#define EL3C90X_DEV_NAME 	"elPci"	/* device name */
#define EL3C90X_DEV_NAME_LEN 	6	
#define EA_SIZE         	6       /* one Ethernet address */
#define EH_SIZE         	14      /* ethernet header size */
#define EL3C90X_BUFSIZ		1536  	/* aligned packet size */
#define EL_MIN_FBUF    		4     	/* Minsize of first buffer in chain */
#define EL_UPD_CNT		16	/* number of upload descriptors */
#define EL_DND_CNT		16	/* number of download descriptors */

/* Definitions for the drvCtrl specific flags field */

#define EL_MEM_ALLOC_FLAG       0x01	/* allocating memory flag */
#define EL_POLLING              0x02	/* polling flag */
#define EL_MODE_MEM_IO_MAP	0x04	/* dev registers mem mapped */
#define EL_PROMISCUOUS_FLAG     0x08	/* set the promiscuous mode */


/* eeprom defines */

#define EL_EE_WAIT		162	/* 162 usec */
#define EL_EE_RETRY_CNT		100	/* retry count */    
#define EL_EE_READ		0x0080	/* read, 5 bit address */
#define EL_EE_WRITE		0x0040	/* write, 5 bit address */
#define EL_EE_ERASE		0x00c0	/* erase, 5 bit address */
#define EL_EE_EWEN		0x0030	/* erase, no data needed */
#define EL_EE_BUSY		0x8000

/* eeprom contents */
    
#define EL_EE_EADDR0		0x00	/* station address, first word */
#define EL_EE_EADDR1		0x01	/* station address, next word, */
#define EL_EE_EADDR2		0x02	/* station address, last word */
#define EL_EE_PRODID		0x03	/* product ID code */
#define EL_EE_MDATA_DATE	0x04	/* manufacturing data, date */
#define EL_EE_MDATA_DIV		0x05	/* manufacturing data, division */
#define EL_EE_MDATA_PCODE	0x06	/* manufacturing data, product code */
#define EL_EE_MFG_ID		0x07
#define EL_EE_PCI_PARM		0x08
#define EL_EE_ROM_ONFO		0x09
#define EL_EE_OEM_ADR0		0x0A
#define	EL_EE_OEM_ADR1		0x0B
#define EL_EE_OEM_ADR2		0x0C
#define EL_EE_SOFTINFO1		0x0D
#define EL_EE_COMPAT		0x0E
#define EL_EE_SOFTINFO2		0x0F
#define EL_EE_CAPS		0x10	/* capabilities word */
#define EL_EE_RSVD0		0x11
#define EL_EE_ICFG_0		0x12
#define EL_EE_ICFG_1		0x13
#define EL_EE_RSVD1		0x14
#define EL_EE_SOFTINFO3		0x15
#define EL_EE_RSVD_2		0x16
    

/* Bits in the capabilities word */

#define EL_CAPS_PNP		0x0001
#define EL_CAPS_FULL_DUPLEX	0x0002
#define EL_CAPS_LARGE_PKTS	0x0004
#define EL_CAPS_SLAVE_DMA	0x0008
#define EL_CAPS_SECOND_DMA	0x0010
#define EL_CAPS_FULL_BM		0x0020
#define EL_CAPS_FRAG_BM		0x0040
#define EL_CAPS_CRC_PASSTHRU	0x0080
#define EL_CAPS_TXDONE		0x0100
#define EL_CAPS_NO_TXLENGTH	0x0200
#define EL_CAPS_RX_REPEAT	0x0400
#define EL_CAPS_SNOOPING	0x0800
#define EL_CAPS_100MBPS		0x1000
#define EL_CAPS_PWRMGMT		0x2000

	
/* Register layouts. */

#define EL_COMMAND		0x0E
#define EL_STATUS		0x0E

#define EL_TX_STATUS		0x1B
#define EL_TX_FREE		0x1C
#define EL_DMACTL		0x20
#define EL_DOWNLIST_PTR		0x24
#define EL_TX_FREETHRESH	0x2F
#define EL_UPLIST_PTR		0x38
#define EL_UPLIST_STATUS	0x30

#define EL_PKTSTAT_UP_STALLED	0x00002000
#define EL_PKTSTAT_UP_ERROR	0x00004000
#define EL_PKTSTAT_UP_CMPLT	0x00008000

#define EL_DMACTL_DN_CMPLT_REQ	0x00000002
#define EL_DMACTL_DOWN_STALLED	0x00000004
#define EL_DMACTL_UP_CMPLT	0x00000008
#define EL_DMACTL_DOWN_CMPLT	0x00000010
#define EL_DMACTL_UP_RX_EARLY	0x00000020
#define EL_DMACTL_ARM_COUNTDOWN	0x00000040
#define EL_DMACTL_DOWN_INPROG	0x00000080
#define EL_DMACTL_COUNTER_SPEED	0x00000100
#define EL_DMACTL_DOWNDOWN_MODE	0x00000200
#define EL_DMACTL_TARGET_ABORT	0x40000000
#define EL_DMACTL_MASTER_ABORT	0x80000000

/*
 * Command codes. Some command codes require that we wait for
 * the CMD_BUSY flag to clear. Those codes are marked as 'mustwait.'
 */

#define EL_CMD_RESET		0x0000	/* mustwait */
#define EL_CMD_WINSEL		0x0800
#define EL_CMD_COAX_START	0x1000
#define EL_CMD_RX_DISABLE	0x1800
#define EL_CMD_RX_ENABLE	0x2000
#define EL_CMD_RX_RESET		0x2800	/* mustwait */
#define EL_CMD_UP_STALL		0x3000	/* mustwait */
#define EL_CMD_UP_UNSTALL	0x3001
#define EL_CMD_DOWN_STALL	0x3002	/* mustwait */
#define EL_CMD_DOWN_UNSTALL	0x3003
#define EL_CMD_RX_DISCARD	0x4000
#define EL_CMD_TX_ENABLE	0x4800
#define EL_CMD_TX_DISABLE	0x5000
#define EL_CMD_TX_RESET		0x5800	/* mustwait */
#define EL_CMD_INTR_FAKE	0x6000
#define EL_CMD_INTR_ACK		0x6800
#define EL_CMD_INTR_ENB		0x7000
#define EL_CMD_STAT_ENB		0x7800
#define EL_CMD_RX_SET_FILT	0x8000
#define EL_CMD_RX_SET_THRESH	0x8800
#define EL_CMD_TX_SET_THRESH	0x9000
#define EL_CMD_TX_SET_START	0x9800
#define EL_CMD_DMA_UP		0xA000
#define EL_CMD_DMA_STOP		0xA001
#define EL_CMD_STATS_ENABLE	0xA800
#define EL_CMD_STATS_DISABLE	0xB000
#define EL_CMD_COAX_STOP	0xB800

#define EL_CMD_SET_TX_RECLAIM	0xC000 /* 3c905B only */
#define EL_CMD_RX_SET_HASH	0xC800 /* 3c905B only */

#define EL_HASH_SET		0x0400
#define EL_HASHFILT_SIZE	256

/*
 * status codes
 * Note that bits 15 to 13 indicate the currently visible register window
 * which may be anything from 0 to 7.
 */

#define EL_STAT_INTLATCH	0x0001	/* 0 */
#define EL_STAT_ADFAIL		0x0002	/* 1 */
#define EL_STAT_TX_COMPLETE	0x0004	/* 2 */
#define EL_STAT_TX_AVAIL	0x0008	/* 3 first generation */
#define EL_STAT_RX_COMPLETE	0x0010  /* 4 */
#define EL_STAT_RX_EARLY	0x0020	/* 5 */
#define EL_STAT_INTREQ		0x0040  /* 6 */
#define EL_STAT_STATSOFLOW	0x0080  /* 7 */
#define EL_STAT_DMADONE		0x0100	/* 8 first generation */
#define EL_STAT_LINKSTAT	0x0100	/* 8 3c509B */
#define EL_STAT_DOWN_COMPLETE	0x0200	/* 9 */
#define EL_STAT_UP_COMPLETE	0x0400	/* 10 */
#define EL_STAT_DMABUSY		0x0800	/* 11 first generation */
#define EL_STAT_CMDBUSY		0x1000  /* 12 */

/* interrupts we normally want enabled. */

#define EL_INTRS							\
	(EL_STAT_UP_COMPLETE|EL_STAT_STATSOFLOW|EL_STAT_ADFAIL|		\
	 EL_STAT_DOWN_COMPLETE|EL_STAT_TX_COMPLETE|EL_STAT_INTLATCH)

#define EL_WIN_0    		0
#define EL_WIN_1    		1
#define EL_WIN_2    		2
#define EL_WIN_3    		3
#define EL_WIN_4    		4
#define EL_WIN_5    		5
#define EL_WIN_6    		6
#define EL_WIN_7    		7
    
/* window 0 registers */

#define EL_W0_EE_DATA		0x0C
#define EL_W0_EE_CMD		0x0A
#define EL_W0_RSRC_CFG		0x08
#define EL_W0_ADDR_CFG		0x06
#define EL_W0_CFG_CTRL		0x04
#define EL_W0_PROD_ID		0x02
#define EL_W0_MFG_ID		0x00

/* window 1 */

#define EL_W1_TX_FIFO		0x10
#define EL_W1_FREE_TX		0x0C
#define EL_W1_TX_STATUS		0x0B
#define EL_W1_TX_TIMER		0x0A
#define EL_W1_RX_STATUS		0x08
#define EL_W1_RX_FIFO		0x00

/* RX status codes */

#define EL_RXSTATUS_OVERRUN	0x01
#define EL_RXSTATUS_RUNT	0x02
#define EL_RXSTATUS_ALIGN	0x04
#define EL_RXSTATUS_CRC		0x08
#define EL_RXSTATUS_OVERSIZE	0x10
#define EL_RXSTATUS_DRIBBLE	0x20

/* TX status codes */

#define EL_TXSTATUS_RECLAIM	0x02 	/* 3c905B only */
#define EL_TXSTATUS_OVERFLOW	0x04
#define EL_TXSTATUS_MAXCOLS	0x08
#define EL_TXSTATUS_UNDERRUN	0x10
#define EL_TXSTATUS_JABBER	0x20
#define EL_TXSTATUS_INTREQ	0x40
#define EL_TXSTATUS_COMPLETE	0x80

/* window 2 */

#define EL_W2_RESET_OPTIONS	0x0C	/* 3c905B only */
#define EL_W2_STATION_MASK_HI	0x0A
#define EL_W2_STATION_MASK_MID	0x08
#define EL_W2_STATION_MASK_LO	0x06
#define EL_W2_STATION_ADDR_HI	0x04
#define EL_W2_STATION_ADDR_MID	0x02
#define EL_W2_STATION_ADDR_LO	0x00

#define EL_RESETOPT_FEATUREMASK	(0x0001 | 0x0002 | 0x004)
#define EL_RESETOPT_D3RESETDIS	0x0008
#define EL_RESETOPT_DISADVFD	0x0010
#define EL_RESETOPT_DISADV100	0x0020
#define EL_RESETOPT_DISAUTONEG	0x0040
#define EL_RESETOPT_DEBUGMODE	0x0080
#define EL_RESETOPT_FASTAUTO	0x0100
#define EL_RESETOPT_FASTEE	0x0200
#define EL_RESETOPT_FORCEDCONF	0x0400
#define EL_RESETOPT_TESTPDTPDR	0x0800
#define EL_RESETOPT_TEST100TX	0x1000
#define EL_RESETOPT_TEST100RX	0x2000

/* window 3 (fifo management) */

#define EL_W3_INTERNAL_CFG	0x00
#define EL_W3_RESET_OPT		0x08
#define EL_W3_FREE_TX		0x0C
#define EL_W3_FREE_RX		0x0A
#define EL_W3_MAC_CTRL		0x06

#define EL_ICFG_CONNECTOR_MASK	0x00F00000
#define EL_ICFG_CONNECTOR_BITS	20

#define EL_ICFG_RAMSIZE_MASK	0x00000007
#define EL_ICFG_RAMWIDTH	0x00000008
#define EL_ICFG_ROMSIZE_MASK	(0x00000040 | 0x00000080)
#define EL_ICFG_DISABLE_BASSD	0x00000100
#define EL_ICFG_RAMLOC		0x00000200
#define EL_ICFG_RAMPART		(0x00010000 | 0x00020000)
#define EL_ICFG_XCVRSEL		(0x00100000 | 0x00200000 | 0x00400000)
#define EL_ICFG_AUTOSEL		0x01000000

#define EL_XCVR_10BT		0x00
#define EL_XCVR_AUI		0x01
#define EL_XCVR_RSVD_0		0x02
#define EL_XCVR_COAX		0x03
#define EL_XCVR_100BTX		0x04
#define EL_XCVR_100BFX		0x05
#define EL_XCVR_MII		0x06
#define EL_XCVR_RSVD_1		0x07
#define EL_XCVR_AUTO		0x08	/* 3c905B only */

#define EL_MACCTRL_DEFER_EXT_END	0x0001
#define EL_MACCTRL_DEFER_0		0x0002
#define EL_MACCTRL_DEFER_1		0x0004
#define EL_MACCTRL_DEFER_2		0x0008
#define EL_MACCTRL_DEFER_3		0x0010
#define EL_MACCTRL_DUPLEX		0x0020
#define EL_MACCTRL_ALLOW_LARGE_PACK	0x0040
#define EL_MACCTRL_EXTEND_AFTER_COL	0x0080 (3c905B only)
#define EL_MACCTRL_FLOW_CONTROL_ENB	0x0100 (3c905B only)
#define EL_MACCTRL_VLT_END		0x0200 (3c905B only)

/*
 * The 'reset options' register contains power-on reset values
 * loaded from the EEPROM. This includes the supported media
 * types on the card. It is also known as the media options register.
 */
#define EL_W3_MEDIA_OPT		0x08

#define EL_MEDIAOPT_BT4		0x0001	/* MII */
#define EL_MEDIAOPT_BTX		0x0002	/* on-chip */
#define EL_MEDIAOPT_BFX		0x0004	/* on-chip */
#define EL_MEDIAOPT_BT		0x0008	/* on-chip */
#define EL_MEDIAOPT_BNC		0x0010	/* on-chip */
#define EL_MEDIAOPT_AUI		0x0020	/* on-chip */