📄 era_alg.lst
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399 ; FOR TESTING ROUTINES
400 ;;;; B DONE ;To REMOVE COMPACTION uncomment this.
401 ;--------------------------------------------------------------------------------------------------
402 00ee 6905! LACL flashAlgoVars.PLS_CNT ;Get the number of pulses left.
403 00ef e388 BCND ERROR,EQ ;If pulse count == 0 then commence
00f0 00b0+
404 ;error handling.
405
406 ; LACC #WADDR ;COLUMN ADDRESS => WADDR REG
407 ; TBLW flashAlgoVars.ADDR
408
409 00f1 6902! LACL flashAlgoVars.READ ;Get the Data Read during compaction
410 ;verify.
411 00f2 bfd0 XOR #0FFFFh ;Invert the bitmask.
00f3 ffff
412 00f4 9002! SACL flashAlgoVars.READ ;Store the inverted bitmask.
413
414 00f5 bf80 LACC #WDATA ;Write bitmask to the WDATA register.
00f6 0003
415 00f7 a702! TBLW flashAlgoVars.READ
416
417 00f8 bf80 LACC #CTRL ;Initialize the compaction mode.
00f9 0001
418 00fa ae01! SPLK #0005,flashAlgoVars.PAD
00fb 0005
419 00fc a701! TBLW flashAlgoVars.PAD
420
421 00fd SDELAY #T_csu_cm ;Wait T_csu(CM)
1 00fd bb58 RPT #T_csu_cm
1 00fe 8b00 NOP
422
423 00ff bf80 LACC #PMPC ;Activate the compaction mode.
0100 0000
424 0101 ae01! SPLK #0005h,flashAlgoVars.PAD
0102 0005
425 0103 a701! TBLW flashAlgoVars.PAD
TMS320C24xx COFF Assembler Version 7.02 Tue Jul 29 10:56:10 2003
Copyright (c) 1987-2002 Texas Instruments Incorporated
era_alg.asm PAGE 11
426
427 0104 b78d CPW LAR AR7,#CMPCT_PULSE ;CMPCT PULSE WIDTH T_cmpct(E)
428 0105 7a8f CALL DELAY,AR7 ;Generate a delay to define
0106 0127+
429 ;the compaction pulse width.
430
431 0107 ae04! SPLK #0000h,flashAlgoVars.PAD1 ;De-activate the compaction mode.
0108 0000
432 0109 7a80 CALL CLRCMD
010a 011f+
433
434 010b SDELAY #T_ch_cm ;Wait T_ch(CM)
1 010b bb3a RPT #T_ch_cm
1 010c 8b00 NOP
435
436 010d ae04! SPLK #0001h,flashAlgoVars.PAD1 ;Clear the control registers.
010e 0001
437 010f 7a80 CALL CLRCMD
0110 011f+
438
439 0111 SDELAY #T_ch_C ;Wait in normal read mode.
1 0111 bb3a RPT #T_ch_C
1 0112 8b00 NOP
440
441
442 0113 1005! LACC flashAlgoVars.PLS_CNT ;Decrement the puse counter.
443 0114 ba01 SUB #1h
444 0115 9005! SACL flashAlgoVars.PLS_CNT
445
446 0116 7980 B CMPCTVER1 ;Resume the compaction verify routine.
0117 00c3+
447 ;--------------------------------------------------------------------------------------------------
448 0118 ae04! DONE: SPLK #6,flashAlgoVars.PAD1 ;Clear all control registers and
0119 0006
449 011a 7a80 CALL CLRCMD ;return to the caller, in ARRAY mode.
011b 011f+
450 011c ACCESS_ARRAY
1 011c af7f IN 07fh,0ff0fh
011d ff0f
451 011e ef00 RET ;PASSED CMPCTVER AND ERVER
452 ;--------------------------------------------------------------------------------------------------
453
454
455 ;--------------------------------------------------------------------------------------------------
456 ; CLRCMD
457 ;--------------------------------------------------------------------------------------------------
458 ; This routine performs the following operations
459 ; 1. Places the flash in normal read mode by writing 0000 to two control
460 ; registers PMPC,CNTL=>0000)
461 ; 2. Returns to the caller in Register Mode.
462 ;--------------------------------------------------------------------------------------------------
463 011f CLRCMD ACCESS_REGS
1 011f 0c7f OUT 07fh,0ff0fh
0120 ff0f
TMS320C24xx COFF Assembler Version 7.02 Tue Jul 29 10:56:10 2003
Copyright (c) 1987-2002 Texas Instruments Incorporated
era_alg.asm PAGE 12
464 0121 ae01! SPLK #0,flashAlgoVars.PAD
0122 0000
465 0123 1007! LACC flashAlgoVars.FL_SECST
466 0124 0b04! RPT flashAlgoVars.PAD1
467 0125 a701! TBLW flashAlgoVars.PAD
468 0126 ef00 RET
469
470
471
472 ;--------------------------------------------------------------------------------------------------
473 ; SUBROUTINE: Delay
474 ;
475 ; DESCRIPTION:
476 ; This routine executes a delay approximately
477 ; (DLOOP + 8) + AR7 * (DLOOP + 6) * 1/freq = nsec
478 ; if AR7 = 0 Delay = 108 cycles
479 ; if AR7 != 0 Delay = 108 + AR6 * 106 cycles
480 ;
481 ; A typical call to this subroutine is as follow:
482 ;
483 ; lar ar7,delay_param 1 cycles reg/#k, 2 cycles if #lk
484 ; call Delay,*,ar7 4 cycles
485 ;
486 ; minimum delay is when delay_parm=0
487 ; minimum delay = 113 cycles ( 108 + 5 )
488 ; for a cycle time of 50 nsec,
489 ; minimum delay = 5.65 usec ( 113 cycles * 50 nsec)
490 ; delay time = 5.65 usec + AR7 * 106 * 50 nsec
491 ; = 5.65 usec + AR7 * 5.3 usec
492 ;
493 ; INPUTS:
494 ; AR7 = Passed on to this routine to set delay time as required
495 ; ARP => AR7
496 ; OUTPUTS:
497 ; none
498 ;--------------------------------------------------------------------------------------------------
499 0127 DELAY
500 0127 bb64 RPT #DLOOP ;1 cycles
501 0128 8b00 NOP ;1+DLOOP = 101 CYCLES (FOR DLOOP = 100)
502 0129 7b9f BANZ DELAY,*-,ar7 ; 4/2 (True/False)
012a 0127+
503 012b ef00 RET ; 4 cycles
504 ; for delay_parm = 0
505 ; (1+101+2+4 = 108) cycles
506 ; for delay_parm != 0
507 ; 108 + AR7 * (1+101+4 = 106) cycles
508
509 012c .label EraseAlgoEndMain
510
511 ;--------------------------------------------------------------------------------------------------
512 0000 .sect "ESPL_text"
513
514 0000 SETWADDR:
515
TMS320C24xx COFF Assembler Version 7.02 Tue Jul 29 10:56:10 2003
Copyright (c) 1987-2002 Texas Instruments Incorporated
era_alg.asm PAGE 13
516 0000 .label EraseAlgoStartSpl
517
518 0000 a707! TBLW flashAlgoVars.FL_SECST
519 0001 ef00 RET
520
521 .loop 6
522 nop
523 .endloop
1 0002 8b00 nop
1 0003 8b00 nop
1 0004 8b00 nop
1 0005 8b00 nop
1 0006 8b00 nop
1 0007 8b00 nop
524 ;--------------------------------------------------------------------------------------------------
525 0008 WADDR_SET:
526 0008 a700! TBLW flashAlgoVars.ADDR
527 0009 ef00 RET
528
529 000a .label EraseAlgoEndSpl
530
No Errors, No Warnings
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