mconfig.c

atheros ar5001 5002 driver

		mSleep(100);
	}

	// set it to ofdm mode for reading the analog rev id for 11b fpga
	if (pLibDev->hwDevID == 0xf11b) {	
		REGW(devNum, 0xa200, 0);
		REGW(devNum, 0x987c, 0x19) ;
		mSleep(20);
	}

   	//read the baseband revision 
	pLibDev->bbRevID = REGR(devNum, PHY_CHIP_ID);

	//Needed so that analog revID write will work.
	if((pLibDev->hwDevID & 0xff) >= 0x0012) {
		REGW(devNum, 0x9800, 0x07);
	}
	else {
		REGW(devNum, 0x9800, 0x47);
	}

	//read the analog revIDs
    	REGW(devNum, (PHY_BASE+(0x34<<2)), 0x00001c16);
    	for (i=0; i<8; i++) {   
     	   REGW(devNum, (PHY_BASE+(0x20<<2)), 0x00010000);
    	}
    	pLibDev->aRevID = (REGR(devNum, PHY_BASE + (256<<2)) >> 24) & 0xff;   
    	pLibDev->aRevID = reverseBits(pLibDev->aRevID, 8);


	if ((0x0012 == pLibDev->hwDevID) || (0xff12 == pLibDev->hwDevID)
		||(pLibDev->hwDevID == 0x0013) || (pLibDev->hwDevID == 0xff13) && (pLibDev->aRevID & 0xf < 3)) {
		// Only the 2 mac of freedom has A/B 
		#ifdef FREEDOM_AP
			if (pLibDev->devMap.DEV_REG_ADDRESS == AR531X_WLAN1) 
		#endif
		{	
			//read the beanie rev ID
			REGW(devNum, 0x9800, 0x00004007);
			mSleep(2);
			REGW(devNum, (PHY_BASE+(0x34<<2)), 0x00001c16);
			for (i=0; i<8; i++) {   
				REGW(devNum, (PHY_BASE+(0x20<<2)), 0x00010000);
			}
			pLibDev->aBeanieRevID = (REGR(devNum, PHY_BASE + (256<<2)) >> 24) & 0xff;   
			pLibDev->aBeanieRevID = reverseBits(pLibDev->aBeanieRevID, 8);
			REGW(devNum, 0x9800, 0x07);
		}
	}

    // load config data, if return value = 0 return from resetDevice
    if (!loadCfgData(devNum, freq)) return;


	// program the pll 
	ar5kInitData[pLibDev->ar5kInitIndex].pMacAPI->pllProgram(devNum, turbo);
        
	// Put baseband into base/TURBO mode 
	if(turbo == TURBO_ENABLE) {
		pLibDev->turbo = turbo;  

		REGW(devNum, PHY_FRAME_CONTROL, REGR(devNum, PHY_FRAME_CONTROL) | PHY_FC_TURBO_MODE);

		//check the turbo bit is set
		for (i = 0; i < 10; i++) {
			if (REGR(devNum, PHY_FRAME_CONTROL) & PHY_FC_TURBO_MODE) {
				break;
			}
			mSleep(1);
		}

		// Reset the baseband 
		ar5kInitData[pLibDev->ar5kInitIndex].pMacAPI->hwReset(devNum, BB_RESET);

		if(i == 10) {
			mError(devNum, EIO, "Device Number %d:ResetDevice: Unable to put the device into tubo mode\n", devNum);
			return;
		}

	}
	else {
		// Base mode
		REGW(devNum, PHY_FRAME_CONTROL, REGR(devNum, PHY_FRAME_CONTROL) & ~PHY_FC_TURBO_MODE);
		//put these back, in case they were written for 11g turbo
	}


	/* New section to handle mode switching */
	if(ar5kInitData[pLibDev->ar5kInitIndex].cfgVersion < 2) {
		switch(pLibDev->mode) {
		case MODE_11A:	//11a
			if ((pLibDev->swDevID == 0xe011) || (pLibDev->swDevID == 0xf11b)||(pLibDev->swDevID == 0x0012)) {
				changeField(devNum, "bb_enable_xpaa", 1);
				changeField(devNum, "bb_enable_xpab", 0);
				changeField(devNum, "rf_b_B_mode", 0);
			}
			break;

		case MODE_11G: //11g
			if ((pLibDev->swDevID == 0xe011) || (pLibDev->swDevID == 0xf11b)||(pLibDev->swDevID == 0x0012)) {
				changeField(devNum, "bb_enable_xpaa", 0);
				changeField(devNum, "bb_enable_xpab", 1);
				changeField(devNum, "rf_b_B_mode", 1);
			}

			break;

		case MODE_11B: //11b

			break;
		}
	}
	else {
		//Do the new handling from the ini files
		switch(pLibDev->mode) {
		case MODE_11A:	//11a
			if(pLibDev->turbo != TURBO_ENABLE) {	//11a base
				pValue = &(pLibDev->pModeArray->value11a);
			}
			else {			//11a turbo
				pValue = &(pLibDev->pModeArray->value11aTurbo);
			}

			break;

		case MODE_11G: //11g
		case MODE_11O: //ofdm@2.4
			if((pLibDev->turbo != TURBO_ENABLE) || (ar5kInitData[pLibDev->ar5kInitIndex].cfgVersion < 3)) {	//11g base
				pValue = &(pLibDev->pModeArray->value11g);
			}
			else {
				pValue = &(pLibDev->pModeArray->value11gTurbo);
			}
			break;

		case MODE_11B: //11b
			pValue = &(pLibDev->pModeArray->value11b);
			break;
		} //end switch

		//do all the mode change fields
		for(i = 0; i < pLibDev->sizeModeArray; i++) {
//			changeField(devNum, pLibDev->regArray[pLibDev->pModeArray[i].indexToMainArray].fieldName, 
//				*pValue);
			updateField(devNum, &pLibDev->regArray[pLibDev->pModeArray[i].indexToMainArray], 
				*pValue, 0);
			//increment value pointer by size of an array element
			pValue = (A_UINT32 *)((A_CHAR *)pValue + sizeof(MODE_INFO));
		}
	}

	//workaround needed for first rev of Oahu
	if(pLibDev->macRev == 0x40) {
		changeField(devNum, "mc_disable_dynamic_clock", 1);
	}


	//see if need to perform any tx threshold adjusting
	if(pLibDev->adjustTxThresh) {
		getField(devNum, "mc_trig_level", &newThreshold, &newThresholdTurbo);
		if((pLibDev->turbo == TURBO_ENABLE) && (ar5kInitData[pLibDev->ar5kInitIndex].cfgVersion < 2)) {
			newThreshold = newThresholdTurbo * 2;
		}
		else {
			newThreshold = newThreshold * 2;
		}
		if (newThreshold > 0x3f) {
			newThreshold = 0x3f;
		}
		changeField(devNum, "mc_trig_level", newThreshold);
		pLibDev->adjustTxThresh  = 0;
	}

	if((pLibDev->swDevID & 0xff) >= 0x13) {
		if(pLibDev->libCfgParams.enableXR) {
			changeField(devNum, "bb_enable_xr", 1);
		}
		else {
			changeField(devNum, "bb_enable_xr", 0);
		}
	}

	
// phyonly reset. Used in the emulation board
#if defined(SPIRIT_AP) || defined(FREEDOM_AP)
#ifdef EMULATION
	REGW(devNum,0x9928,0);
	mSleep(10);
	REGW(devNum,0x9928,1);
#endif
#endif


#ifdef FREEDOM_AP
//	changeField(devNum, "rf_ovr", 1);
//	changeField(devNum, "rf_gain_I", 0x10);
#endif
	// Setup Values from EEPROM - only touches EEPROM the first time
	//FJC: 06/09/03 moved reading eeprom to here, since it reads the EAR
	if (pLibDev->eePromLoad) {
		if(pLibDev->swDevID >= 0x0012) {
			REGW(devNum, 0x6010, REGR(devNum, 0x6010) | 0x3);
		}
		if(!setupEEPromMap(devNum)) {
			mError(devNum, EIO, "Error: unable to load EEPROM\n");
			return;
		}
		if(pLibDev->p16kEepHeader->majorVersion >= 4) {
			earHere = ar5212IsEarEngaged(devNum, pLibDev->pEarHead, freq);
		}
	}

	//do a check for EAR changes to rf registers
    if (earHere) {
        ar5212EarModify(devNum, pLibDev->pEarHead, EAR_LC_RF_WRITE, freq, &modifier);
    }
	/* Initialize chips with values from register file */
	for(i = 0; i < pLibDev->sizePciValuesArray; i++ ) {
#if defined(SPIRIT_AP) || defined(FREEDOM_AP)
#ifdef EMULATION
	    if (pLibDev->pciValuesArray[i].offset == 0x9928) continue;
#endif
#endif
		/*if dealing with a version 2 config file, 
		  then all values are found in the base array */
		if((pLibDev->turbo == TURBO_ENABLE) && (ar5kInitData[pLibDev->ar5kInitIndex].cfgVersion < 2)) {
				REGW(devNum, pLibDev->pciValuesArray[i].offset, pLibDev->pciValuesArray[i].turboValue);
		}
		else {
			REGW(devNum, pLibDev->pciValuesArray[i].offset, pLibDev->pciValuesArray[i].baseValue);
		}
	}

	
	if((turbo == TURBO_ENABLE) && (ar5kInitData[pLibDev->ar5kInitIndex].cfgVersion < 3)) {
		//quick enable to venice 11g turbo.  Force minimum fields in here
		//version 3 config files have a 11g turbo column
		if(((pLibDev->swDevID & 0xff) >= 0x0013) && ((pLibDev->mode == MODE_11G)||(pLibDev->mode == MODE_11O))) {
			changeRegValueField(devNum, "bb_short20", 1);
			changeRegValueField(devNum, "rf_turbo", 1);
			changeRegValueField(devNum, "bb_turbo", 1);
			changeRegValueField(devNum, "mc_turbo_mode", 1);
			changeRegValueField(devNum, "bb_dyn_ofdm_cck_mode", 0);
			changeRegValueField(devNum, "bb_agc_settling", 0x25);
			changeRegValueField(devNum, "mc_sifs_dcu", 480);
			changeRegValueField(devNum, "mc_slot_dcu", 480);
			changeRegValueField(devNum, "mc_eifs_dcu", 4480);
			changeRegValueField(devNum, "mc_usec_duration", 80);
			changeRegValueField(devNum, "mc_sifs_duration_usec", 6);
			changeRegValueField(devNum, "mc_cts_timeout", 0x12c0);
			changeRegValueField(devNum, "mc_ack_timeout", 0x12c0);
			changeRegValueField(devNum, "mc_usec", 79);
		}
	}

	if(((pLibDev->swDevID & 0xff) >= 0x0013) && (pLibDev->mode == MODE_11O)) {
		changeRegValueField(devNum, "bb_dyn_ofdm_cck_mode", 0);
	}

/* Remove this after moving this value to config file  */


#ifdef FREEDOM_AP
/*
	REGW(devNum,0x9848,0x0018d410);
	REGW(devNum,0x996c, 0x1301); // sigma-delta control
	REGW(devNum, 0x982c, 0x0002effe);
*/
#endif



	/* delta_slope_coeff_exp and delta_slope_coeff_man for venice */
	if ((pLibDev->swDevID & 0x00ff) >= 0x0013) {
		double fclk,coeff;
		A_UINT32 coeffExp,coeffMan;
		A_UINT32 deltaSlopeCoeffMan, deltaSlopeCoeffExp;
		A_UINT32 progCoeff;

		switch (pLibDev->mode) {
			case MODE_11A:
				if(pLibDev->swDevID == 0xf013) {
					fclk = 16.0;
				}
				else {
					fclk = 40;
				}
				progCoeff = 1;
				break;
			case MODE_11G:
			case MODE_11O:
				if(pLibDev->swDevID == 0xf013) {
					fclk = (16.0 * 10.0) / 11.0;
				}
				else {
					fclk = 40;
				}
				progCoeff = 1;
				break;
			default:
				fclk = 0;
				progCoeff = 0;
				break;
		}
		if (progCoeff) {
			coeff = (2.5 * fclk) / ((double)freq);
			coeffExp = 14 -  (int)(floor(log10(coeff)/log10(2)));
			coeffMan = (int)(floor((coeff*(pow(2,coeffExp))) + 0.5));
			deltaSlopeCoeffExp = coeffExp - 16;
			deltaSlopeCoeffMan = coeffMan;
			REGW(devNum, 0x9814, (REGR(devNum,0x9814) & 0x00001fff) | 
								 (deltaSlopeCoeffExp << 13) |
								      (deltaSlopeCoeffMan << 17));


		}
	}

	//Disable all the mac queue clocks
	if((pLibDev->swDevID != 0x0007) && (pLibDev->swDevID != 0x0010)) {
		disable5211QueueClocks(devNum);
	}
	
	
// Byteswap Tx and Rx descriptors for Big Endian systems
#ifdef BIG_ENDIAN
	REGW(devNum, F2_CFG, F2_CFG_SWTD | F2_CFG_SWRD);
#endif


#ifdef HEADER_LOAD_SCHEME
	else if (pLibDev->eePromHeaderLoad) {
		setupEEPromHeaderMap(devNum);
	}
#endif //HEADER_LOAD_SCHEME

    // Setup the macAddr in the chip
	memcpy(pLibDev->macAddr.octets, mac, WLAN_MAC_ADDR_SIZE);
#ifndef BIG_ENDIAN
	REGW(devNum, F2_STA_ID0, pLibDev->macAddr.st.word);
	temp1 = REGR(devNum, F2_STA_ID1); 
	temp2 = (temp1 & 0xffff0000) | F2_STA_ID1_AD_HOC | pLibDev->macAddr.st.half | F2_STA_ID1_DESC_ANT;
	REGW(devNum, F2_STA_ID1, temp2); 
#else
	{
		A_UINT32 addr;
		
		addr = swap_l(pLibDev->macAddr.st.word);
		REGW(devNum, F2_STA_ID0, addr);
		addr = (A_UINT32)swap_s(pLibDev->macAddr.st.half);
		REGW(devNum, F2_STA_ID1, (REGR(devNum, F2_STA_ID1) & 0xffff0000) | F2_STA_ID1_AD_HOC |
				addr | F2_STA_ID1_DESC_ANT);
	}
#endif

	// then our BSSID
	memcpy(pLibDev->bssAddr.octets, bss, WLAN_MAC_ADDR_SIZE);
#ifndef BIG_ENDIAN
	REGW(devNum, F2_BSS_ID0, pLibDev->bssAddr.st.word);
	REGW(devNum, F2_BSS_ID1, pLibDev->bssAddr.st.half);
#else
	{
		A_UINT32 addr;

		addr = swap_l(pLibDev->bssAddr.st.word);		
		REGW(devNum, F2_BSS_ID0, addr);
		addr = (A_UINT32)swap_s(pLibDev->bssAddr.st.half);
		REGW(devNum, F2_BSS_ID1, addr);
	}
#endif


	REGW(devNum, F2_BCR, F2_BCR_STAMODE);
	REGR(devNum, F2_BSR); // cleared on read


	// enable activity leds and clock run enable
	REGW(devNum, F2_PCICFG, F2_PCICFG_CLKRUNEN | F2_PCICFG_LED_ACT);

	// Set the RX Disable to stop even packets outside of RX_FILTER (ProbeRequest)
	// Note that scripts must turn off RX Disable to receive packets inc. ACKs.
//	REGW(devNum, F2_DIAG_SW, F2_DIAG_RX_DIS);
	ar5kInitData[pLibDev->ar5kInitIndex].pMacAPI->disableRx(devNum);

	// Writing to F2_BEACON will start timers. Hence it should be the last
	// register to be written.
	REGW(devNum, F2_BEACON, F2_BEACON_RESET_TSF | 0xffff);

    // Setup board specific options
    if (pLibDev->eePromLoad) {
		assert(pLibDev->eepData.eepromChecked);
		if((((pLibDev->eepData.version >> 12) & 0xF) == 1) ||
			(((pLibDev->eepData.version >> 12) & 0xF) == 2)){
			REGW(devNum, PHY_BASE+(10<<2), (REGR(devNum, PHY_BASE+(10<<2)) & 0xFFFF00FF) |
				(pLibDev->eepData.xlnaOn << 8));
			REGW(devNum, PHY_BASE+(13<<2), (pLibDev->eepData.xpaOff << 24) |
				(pLibDev->eepData.xpaOff << 16) | (pLibDev->eepData.xpaOn << 8) |
				pLibDev->eepData.xpaOn);
			REGW(devNum, PHY_BASE+(17<<2), (REGR(devNum, PHY_BASE+(17<<2)) & 0xFFFFC07F) |
				((pLibDev->eepData.antenna >> 1) & 0x3F80));
			REGW(devNum, PHY_BASE+(18<<2), (REGR(devNum, PHY_BASE+(18<<2)) & 0xFFFC0FFF) |
				((pLibDev->eepData.antenna << 10) & 0x3F000));
			REGW(devNum, PHY_BASE+(25<<2), (REGR(devNum, PHY_BASE+(25<<2)) & 0xFFF80FFF) |
				((pLibDev->eepData.thresh62 << 12) & 0x7F000));
			REGW(devNum, PHY_BASE+(68<<2), (REGR(devNum, PHY_BASE+(68<<2)) & 0xFFFFFFFC) |
				(pLibDev->eepData.antenna & 0x3));
		}
	}

	// Setup the transmit power values for cards since 0x0[0-2]05
	pLibDev->freqForResetDevice = freq;
	initializeTransmitPower(devNum, freq, 0, NULL);
	setChannel(devNum, freq);
	
    //check for any EAR modifications needed before PHY_ACTIVATE
	if (earHere) {
        ar5212EarModify(devNum, pLibDev->pEarHead, EAR_LC_PHY_ENABLE, freq, &modifier);
    }

	// activate D2
	REGW(devNum, PHY_ACTIVE, PHY_ACTIVE_EN);
	mSleep(3);

	if( (pLibDev->swDevID == 0xf11b) && (pLibDev->mode == MODE_11B)) {
		REGW(devNum, 0xd87c,0x19);
		mSleep(4);
	}
	if( (pLibDev->swDevID == 0xf11b) && ((pLibDev->mode == MODE_11B) || (pLibDev->mode == MODE_11G))) {
		REGW(devNum, 0xd808,0x502); 
		mSleep(2);
	}

	//enableCal flag should have the bits set for CAL
	// calibrate it and poll the bit going to 0 for completion
	if (enableCal) {
		REGW(devNum, PHY_AGC_CONTROL,
			REGR(devNum, PHY_AGC_CONTROL) | enableCal);