dk_cmds.h

atheros ar5001 5002 driver

// dk_cmds.h - contains definitions for dk commands 

// Copyright (c) 2000 Atheros Communications, Inc., All Rights Reserved 

#ident	"ACI $Id: //depot/sw/branches/ART_V45/sw/src/dk/mdk/common/include/dk_cmds.h#1 $, $Header: //depot/sw/branches/ART_V45/sw/src/dk/mdk/common/include/dk_cmds.h#1 $"

// modification history
// --------------------
// 00jan02 	sharmat		created (copied from windows client)

// DESCRIPTION
// -----------
// Contains the definitions for all of the commands sent between dk_master and dk_client.

#ifndef	 __INCdk_cmdsh
#define	 __INCdk_cmdsh

#include "wlantype.h"
#include  "athreg.h"
#include  "manlib.h"
#ifndef _MLD
#include "event.h"
#else
#ifdef JUNGO
#include "mld.h"
#endif
#ifdef ANWI
#include "mld_anwi.h"
#endif
#ifdef LINUX 
#include "mld_linux.h"
#endif
#endif // _MLD

// Error codes for commands sent back to dk_perl 
#define CMD_OK 0x0
#define COMMS_ERR_BAD_LENGTH 0x1
#define BAD_LENGTH_MSG "Length of command received from dk_perl does not match expected length for CmdID\n"
#define COMMS_ERR_DEV_INIT_FAIL 0x2
#define DEV_INIT_FAIL_MSG "There was a failure in dk_c, somewhere in deviceInit() function\n"
#define	COMMS_ERR_INDEX_TOO_LARGE 0x3
#define INDEX_TOO_LARGE_MSG "Not able to create any more devInfo structures in dk_c. Too many F2's in system?\n"
#define COMMS_ERR_BAD_OFFSET 0x4
#define BAD_OFFSET_MSG "An invalid offset was given for a register access\n"
#define COMMS_ERR_REGS_NOT_MAPPED 0x5
#define REGS_NOT_MAPPED_MSG "F2 registers have not been mapped in dk_c\n"
#define COMMS_ERR_NO_F2_TO_SELECT 0x6
#define NO_F2_TO_SELECT_MSG "Error in dk_c, incorrect F2 number specified in select_hw cmd\n"
#define COMMS_ERR_BAD_CFG_SIZE 0x7
#define BAD_CFG_SIZE_MSG "Illegal PCI config access size sent to dk_c, must be 8, 16 or 32\n"
#define COMMS_ERR_ALLOC_FAIL 0x8
#define ALLOC_FAIL_MSG "Unable to allocate memory in dk_c\n"
#define COMMS_ERR_BAD_MEM_SIZE 0x9
#define BAD_MEM_SIZE_MSG "Illegal memory access size sent to dk_c, must be 8, 16 or 32\n"
#define COMMS_ERR_WRITE_BLOCK_FAIL 0xa
#define WRITE_BLOCK_FAIL_MSG "Failed in call to hwMemWriteBlock()\n"
#define COMMS_ERR_READ_BLOCK_FAIL 0xb
#define READ_BLOCK_FAIL_MSG "Failed in call to hwMemReadBlock()\n"
#define COMMS_ERR_REMAP_FAIL 0xc
#define REMAP_FAIL_MSG "Failed in the call to hwRemapHardware()\n"
#define COMMS_ERR_EVENT_CREATE_FAIL 0xd
#define EVENT_CREATE_FAIL_MSG "Failed in call to hwCreateEvent()\n"
#define COMMS_ERR_NO_EVENTS 0xe
#define NO_EVENTS_MSG "Triggered Q has not events to get\n"
#define COMMS_BAD_STAT_ID 0xf
#define BAD_STAT_ID_MSG "Illegal statID, use get_all_stats cmds\n"
#define COMMS_ERR_EVENT_ENABLE_FEATURE_FAIL 0x10
#define COMMS_ERR_EVENT_DISABLE_FEATURE_FAIL 0x11
#define COMMS_ERR_MDK_ERROR 0x12
#define MDK_ERROR_MSG "MDK Error: Check the mdkerrno"
// Command status 32 bits 
// Lower 16 bits gives the Error Number.
// Upper 16 bits contains some more information for that Error.
#define COMMS_ERR_MASK 0xffff
#define COMMS_ERR_SHIFT 0
#define COMMS_ERR_INFO_MASK 0xffff0000
#define COMMS_ERR_INFO_SHIFT 16
#define MAX_GENERIC_CMD_LEN		1024

#define MAX_NUM_FIELDS			100
#define MAX_PCDACS				64

#ifdef __cplusplus
extern "C" {
#endif //__cplusplus 

// command ID's for the commands 
enum COMMAND_IDS {
	INIT_F2_CMD_ID,
	SELECT_HW_CMD_ID,
	MEM_WRITE_CMD_ID,
	MEM_READ_CMD_ID,
	REG_READ_CMD_ID,
	REG_WRITE_CMD_ID,
	CFG_READ_CMD_ID,
    	CFG_WRITE_CMD_ID,
    	MEM_ALLOC_CMD_ID,
    	MEM_FREE_CMD_ID,
    	MEM_WRITE_BLOCK_CMD_ID,
    	MEM_READ_BLOCK_CMD_ID,
    	REMAP_HW_CMD_ID,
    	CREATE_EVENT_CMD_ID,
    	ANY_EVENTS_CMD_ID,
    	GET_EVENT_CMD_ID,
    	DISCONNECT_PIPE_CMD_ID,
    	CLOSE_PIPE_CMD_ID,
    	ISR_FEATURE_ENABLE_CMD_ID,
    	ISR_GET_RX_STATS_CMD_ID,
    	ISR_GET_TX_STATS_CMD_ID,
    	ISR_SINGLE_RX_STAT_CMD_ID,
    	ISR_SINGLE_TX_STAT_CMD_ID,
    	WAIT_ON_EVENT_CMD_ID,
	WAIT_ON_TIME_CMD_ID,
	ISR_FEATURE_DISABLE_CMD_ID,
	M_EEPROM_READ_CMD_ID,
	M_EEPROM_WRITE_CMD_ID,
	M_EEPROM_READ_BLOCK_CMD_ID,
	M_EEPROM_WRITE_BLOCK_CMD_ID,
	M_RESET_DEVICE_CMD_ID,
	M_GENERIC_CMD_ID,
    	M_CHECK_REGS_CMD_ID,
    	M_CHANGE_CHANNEL_CMD_ID,
    	M_CHECK_PROM_CMD_ID,
    	M_REREAD_PROM_CMD_ID,
    	M_TX_DATA_SETUP_CMD_ID,
    	M_TX_DATA_BEGIN_CMD_ID,
	M_TX_DATA_START_CMD_ID,
   	M_TX_DATA_COMPLETE_CMD_ID,
    	M_RX_DATA_SETUP_CMD_ID,
    	M_RX_DATA_BEGIN_CMD_ID,
	M_RX_DATA_START_CMD_ID,
   	M_RX_DATA_COMPLETE_CMD_ID,
	M_RX_STATS_SNAPSHOT_CMD_ID,
    	M_TXRX_DATA_BEGIN_CMD_ID,
	M_CLEANUP_TXRX_MEMORY_CMD_ID,
    	M_TX_GET_STATS_CMD_ID,
    	M_RX_GET_STATS_CMD_ID,
    	M_RX_GET_DATA_CMD_ID,
    	M_TX_CONT_BEGIN_CMD_ID,
	M_TX_CONT_FRAME_BEGIN_CMD_ID,
    	M_TX_CONT_END_CMD_ID,
    	M_SET_ANTENNA_CMD_ID,
    	M_SET_POWER_SCALE_CMD_ID,
    	M_SET_TRANSMIT_POWER_CMD_ID,
    	M_SET_SINGLE_TRANSMIT_POWER_CMD_ID,
    	M_DEV_SLEEP_CMD_ID,
    	M_CLOSE_DEVICE_CMD_ID,
	M_CHANGE_FIELD_CMD_ID,
	M_ENABLE_WEP_CMD_ID,
	M_ENABLE_PA_PRE_DIST_CMD_ID,
	M_DUMP_REGS_CMD_ID,
	M_DUMP_PCI_WRITES_CMD_ID,
	M_TEST_LIB_CMD_ID,
	M_DISPLAY_FIELD_VALUES_CMD_ID,
	M_GET_FIELD_VALUE_CMD_ID,
	M_READ_FIELD_CMD_ID,
	M_WRITE_FIELD_CMD_ID,
	M_SET_RESET_PARAMS_CMD_ID,
	M_CHANGE_MULTIPLE_FIELDS_ALL_MODES_CMD_ID,
	M_CHANGE_MULTIPLE_FIELDS_CMD_ID,
	M_GET_FIELD_FOR_MODE_CMD_ID,
	LOAD_AND_RUN_CODE_CMD_ID,
	M_FORCE_SINGLE_PCDAC_TABLE_CMD_ID,
	M_FORCE_PCDAC_TABLE_CMD_ID,
	M_FORCE_POWER_TX_MAX_CMD_ID,
	M_GET_EEPROM_STRUCT_CMD_ID,
	M_GET_DEVICE_INFO_CMD_ID,
	M_WRITE_PROD_DATA_CMD_ID,
	M_SPECIFY_SUBSYSTEM_CMD_ID,
	M_FORCE_SINGLE_POWER_TX_MAX_CMD_ID,
	M_SET_QUEUE_CMD_ID,
	M_MAP_QUEUE_CMD_ID,
	M_CLEAR_KEY_CACHE_CMD_ID,
	RUN_SCREENING_TEST_CMD_ID,
	DIAG_CMD,
	ENABLE_HW_CAL_CMD,
   	TRAM_WRITE_BLOCK_CMD_ID,
   	TRAM_READ_BLOCK_CMD_ID,
	M_GET_MAX_POWER_CMD_ID,
	M_GET_PCDAC_FOR_POWER_CMD_ID,
	M_FALSE_DETECT_BACKOFF_VALS_CMD_ID,
	M_GET_MAC_ADDR_CMD_ID,
	M_MASK_TRIGGER_SWEEP_CMD_ID,
	M_MASK_DETECT_SIGNAL_CMD_ID,
	M_MASK_SET_DEV_NUMS_CMD_ID,
	M_MASK_FORCE_MIN_CCAPWR_CMD_ID,
	M_MASK_CONFIG_CAPTURE_CMD_ID,
	AP_REG_READ_CMD_ID,
	AP_REG_WRITE_CMD_ID,
	M_SET_LIB_CONFIG_CMD_ID,
	M_GET_XPDGAIN_CMD_ID,
	M_SELECT_DEV_NUM_CMD_ID,
	M_GET_POWER_INDEX_CMD_ID,
	M_GET_ART_ANI_LEVEL_CMD_ID,
	M_SET_ART_ANI_LEVEL_CMD_ID,
};

// number of bytes that can send in a block read or write command.
// limit is impossed by the communications buffers.
#define	MAX_BLOCK_BYTES 3900
#define MAX_FIELD_SIZE 256
#define	MAX_BLOCK_DWORDS (MAX_BLOCK_BYTES / 4)
#define	MAX_BLOCK_SWORDS (MAX_BLOCK_BYTES / 2)
#define MAX_NUM_FIELDS			100

// structures for the commands 
typedef struct cmdReply {
	A_UINT32 replyCmdLen;
  	A_UINT32 replyCmdId; // command ID of command to which this is a reply 
  	A_UINT32 status; // status of the command 
  	A_UCHAR cmdBytes[4000]; // bytes of the command reply 
} CMD_REPLY;


typedef struct {
	A_UINT32 cmdLen;
  	A_UINT32 cmdID;

  	union {
    		struct memWriteCmd {
      			A_UINT32 writeAddr;
      			A_UINT32 writeValue;
      			A_UINT32 writeSize;
    		} MEM_WRITE_CMD;

    		struct memReadCmd {
      			A_UINT32 readAddr;
       			A_UINT32 readSize;
    		} MEM_READ_CMD;

    		struct initF2Cmd {
      			A_UINT32 whichF2; // which F2 in system to initialize 
    		} INIT_F2_CMD;

    		struct regReadCmd {
      			A_UINT32 readAddr; // address to read from 
    		} REG_READ_CMD;

    		struct regWriteCmd {
      			A_UINT32 writeAddr; // address to write to 
      			A_UINT32 regValue; // value to write 
    		} REG_WRITE_CMD;

    		struct selectHwCmd {
      			A_UINT32 whichF2; // which F2 in system to initialize 
    		} SELECT_HW_CMD;

    		struct cfgReadCmd {
      			A_UINT32 cfgReadAddr; // address to read from 
      			A_UINT32 readSize;  // size to read 32, 16 or 8 
    		} CFG_READ_CMD;

    		struct cfgWriteCmd {
      			A_UINT32 cfgWriteAddr; // address to write to 
      			A_UINT32 cfgValue; // value to write 
      			A_UINT32 writeSize; // size to write, 32, 16 or 8 
    		} CFG_WRITE_CMD;

    		struct memAllocCmd {
      			A_UINT32 allocSize; // num bytes to allocate 
      			A_UINT32 physAddr;  // phys address to allocate at 
    		} MEM_ALLOC_CMD;

    	 //	struct memFreeCmd {
         //	} MEM_FREE_CMD;

    		struct memReadBlockCmd {
      			A_UINT32 physAddr; // phys address to read from 
      			A_UINT32 length; // how many bytes to read
    		} MEM_READ_BLOCK_CMD;

    		struct memWriteBlockCmd {
      			A_UINT32 physAddr; // phys address to allocate at 
      			A_UINT32 length; // how many bytes to write 
      			A_UINT8 bytes[MAX_BLOCK_BYTES]; // bytes to be written 
    		} MEM_WRITE_BLOCK_CMD;

    		struct remapHwCmd {
      			A_UINT32 mapAddress; // new address to map to 
    		} REMAP_HW_CMD;

    		struct createEventCmd {
      			A_UINT32 type;
      			A_UINT32 persistent;
      			A_UINT32 param1;
      			A_UINT32 param2;
      			A_UINT32 param3;
      			EVT_HANDLE eventHandle;
    		} CREATE_EVENT_CMD;

    		struct waitEventCmd {
      			A_UINT32 eventID;
      			A_UINT32 simulationTime;
      			A_UINT32 returnValue;
    		} WAIT_EVENT_CMD;

    		struct waitTimeStruct {
      			A_UINT32 timeToWait;
    		} WAIT_ON_TIME_CMD;

    		struct isrFeatureEnableCmd {
      			A_UINT32 featureID;
      			A_UINT32 param1;
      			A_UINT32 param2;
    		} ISR_FEATURE_ENABLE_CMD;

    		struct isrFeatureDisableCmd {
      			A_UINT32 featureID;
    		} ISR_FEATURE_DISABLE_CMD;

    		struct isrGetStatsCmd {
      			A_UINT32 clearOnRead;
    		} ISR_GET_STATS_CMD;

    		struct isrSingleStatCmd {
      			A_UINT32 statID;
      			A_UINT32 clearOnRead;
    		} ISR_SINGLE_STAT_CMD;

    		struct eepromReadCmd {
      			A_UINT32 devNum;
      			A_UINT32 offset;
    		} EEPROM_READ_CMD;

    		struct eepromWriteCmd {
      			A_UINT32 devNum;
      			A_UINT32 offset;
      			A_UINT32 value;
    		} EEPROM_WRITE_CMD;

		struct eepromReadBlockCmd {
          		A_UINT32 devNum;
      			A_UINT32 startOffset;
      			A_UINT32 length; // how many eeprom words to read 
    		} EEPROM_READ_BLOCK_CMD;