syslib.c

kedin bsp for vxWorks

/* sysLib.c - KS8695P demo board system-dependent routines */



/*
modification history
--------------------
9/15/2003  Ritter Yeh  created 
*/

/*
DESCRIPTION
This library provides board-specific routines for the KS8695P
Demo Board BSP.

It #includes the following chip drivers:

    ks8695pTimer.c -    KS8695P timer driver
    ks8695pIntrCtl.c -  KS8695P interrupt controller driver
    ks8695plSio.c -	KS8695P UART driver
    pciIomapLib.c -	PCI I/O mapping support
if INCLUDE_FLASH is defined, it #includes:
    flashMem.c -        Flash memory driver
    nvRamToFlash.c -    driver to use some Flash like NVRAM
else it #includes:
    nullNvRam.c -	dummy NVRAM routines

It #includes the following BSP files:
    sysSerial.c -	serial device initialisation routines
    sysEnd.c -		END network driver support routines.
    pciIomapShow.c -	PCI Show routines

INCLUDE FILES: sysLib.h string.h intLib.h taskLib.h vxLib.h muxLib.h
	       pciIomapLib.h

*/

/* includes */

#include "vxWorks.h"
#include "config.h"

#include "sysLib.h"
#include "string.h"
#include "intLib.h"
#include "taskLib.h"
#include "vxLib.h"
#include "muxLib.h"
#include "cacheLib.h"

#include "arch/arm/mmuArmLib.h"
#include "private/vmLibP.h"
#include "dllLib.h"
#include "pciIomapLib.h"



/* imports */

IMPORT char end [];			    /* end of system, created by ld */
IMPORT VOIDFUNCPTR _func_armIntStackSplit;  /* ptr to fn to split stack */



#if !defined(INCLUDE_MMU) && \
    (defined(INCLUDE_CACHE_SUPPORT) || defined(INCLUDE_MMU_BASIC) || \
     defined(INCLUDE_MMU_FULL) || defined(INCLUDE_MMU_MPU))
#define INCLUDE_MMU
#endif



/* globals */

#if defined(INCLUDE_MMU)

/*
 * The following structure describes the various different parts of the
 * memory map to be used only during initialisation by
 * vm(Base)GlobalMapInit() when INCLUDE_MMU_BASIC/FULL are
 * defined.
 *
 * Clearly, this structure is only needed if the CPU has an MMU!
 *
 * The following are not the smallest areas that could be allocated for a
 * working system. If the amount of memory used by the page tables is
 * critical, they could be reduced.
 */

PHYS_MEM_DESC sysPhysMemDesc [] =
    {

    /* DRAM must always be the first entry */
    /* adrs and length parameters must be page-aligned (multiples of 0x1000) */
    /* DRAM - Always the first entry */
    {
    (void *) LOCAL_MEM_LOCAL_ADRS,	/* virtual address */
    (void *) LOCAL_MEM_LOCAL_ADRS,	/* physical address */
    ROUND_UP (LOCAL_MEM_SIZE, PAGE_SIZE), /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
	/*RLQ,TEMP*/
    /*VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE*/
    VM_STATE_VALID	| VM_STATE_WRITABLE_NOT	 | VM_STATE_CACHEABLE_NOT
    },

    /*
     * ROM is normally marked as uncacheable by VxWorks. We leave it like that
     * for the time being, even though this has a severe impact on execution
     * speed from ROM.
     */
    {
    (void *) ROM_BASE_ADRS,
    (void *) ROM_BASE_ADRS,
    ROUND_UP (ROM_SIZE_TOTAL, PAGE_SIZE),
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT

    },

    /* I/O and memory control registers */
    {
    (void *) REG_IO_BASE,	 
    (void *) REG_IO_BASE,
    PAGE_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },

    /*PCI-AHB Bridge Configuration registers */
    {
    (void *) (REG_IO_BASE+REG_PCI_CRCFID),
    (void *) (REG_IO_BASE+REG_PCI_CRCFID),
    PAGE_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },

    /*WAN control registers */
    {
    (void *) (REG_IO_BASE+REG_WAN_DMA_TX),	 
    (void *) (REG_IO_BASE+REG_WAN_DMA_TX),
    PAGE_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },

    /*LAN control registers */
    {
    (void *) (REG_IO_BASE+REG_LAN_DMA_TX),	 
    (void *) (REG_IO_BASE+REG_LAN_DMA_TX),
    PAGE_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },

    /*UART, Interrupt, Timer, GPIO, SWITCH, PHY control registers */
    {
    (void *) (REG_IO_BASE+REG_UART_RX_BUFFER),	 
    (void *) (REG_IO_BASE+REG_UART_RX_BUFFER),
    PAGE_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },

#ifdef INCLUDE_PCI
    {
    (void *) CPU_PCI_IO_ADRS,	/* PCI I/O space */
    (void *) CPU_PCI_IO_ADRS,
    ROUND_UP (CPU_PCI_IO_SIZE, PAGE_SIZE),
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },

    {
    (void *) CPU_PCI_MEM_ADRS,	/* PCI Mem space */
    (void *) CPU_PCI_MEM_ADRS,
    ROUND_UP (CPU_PCI_MEM_SIZE, PAGE_SIZE),
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },
  
#endif /* INCLUDE_PCI */

    };

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);


#endif /* defined(INCLUDE_MMU) */

int	sysBus	    = BUS;		/* system bus type (VME_BUS, etc) */
int	sysCpu	    = CPU;		/* system CPU type (e.g. ARMARCH4/4_T)*/
char *	sysBootLine = BOOT_LINE_ADRS; 	/* address of boot line */
char *	sysExcMsg   = EXC_MSG_ADRS;	/* catastrophic message area */
int	sysProcNum;			/* processor number of this CPU */
int	sysFlags;			/* boot flags */
char	sysBootHost [BOOT_FIELD_LEN];	/* name of host from which we booted */
char	sysBootFile [BOOT_FIELD_LEN];	/* name of file from which we booted */


/* locals */


/* defines */

/* externals */

IMPORT int  ambaIntDevInit (void);
IMPORT void sysIntStackSplit (char *, long);


/* globals */


/* forward LOCAL functions declarations */


/* forward declarations */

char *	sysPhysMemTop (void);


#if defined (INCLUDE_USB)
void sysUsbPciInit(void);
#endif

/* included source files */

#ifdef INCLUDE_FLASH
#include "mem/nvRamToFlash.c"
#include "flashMem.c"
#else
#include "mem/nullNvRam.c"
#endif
#include "vme/nullVme.c"
#include "sysSerial.c"


#include "ks8695Timer.c"
#include "ks8695IntrCtl.c"
#include "ks8695Sio.c"

#include "pciIomapLib.c"
#include "pciIomapShow.c"

#include "sysEnd.c"
#include "ks8695End.c"
#include "sysKS8695End.c"




IMPORT STATUS pciDeviceShow (int);


void pciScan (void)
{
    pciDeviceShow (0);
}



/*******************************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.
*
* NOTE
* This routine does not include all of the possible variants, and the
* inclusion of a variant in here does not mean that it is supported.
*
* RETURNS: A pointer to a string identifying the board and CPU.
*/

char *sysModel (void)
    {

    return	"MICREL KS8695P ";

    }

/*******************************************************************************
*
* sysBspRev - return the BSP version with the revision eg 1.2/<x>
*
* This function returns a pointer to a BSP version with the revision.
* e.g. 1.2/<x>. BSP_REV is concatenated to BSP_VERSION to form the
* BSP identification string.
*
* RETURNS: A pointer to the BSP version/revision string.
*/

char * sysBspRev (void)
    {
    return (BSP_VERSION BSP_REV);
    }


/*******************************************************************************
*
* sysHwInit0 - perform early BSP-specific initialisation
*
* This routine performs such BSP-specific initialisation as is necessary before
* the architecture-independent cacheLibInit can be called. It is called
* from usrInit() before cacheLibInit(), before sysHwInit() and before BSS
* has been cleared.
*
* RETURNS: N/A
*/

void sysHwInit0 (void)
    {


#ifdef INCLUDE_CACHE_SUPPORT
    /*
     * Install the appropriate cache library, no address translation
     * routines are required for this BSP, as the default memory map has
     * virtual and physical addresses the same.
     */

    cacheArm920tLibInstall (NULL, NULL);

#endif /* INCLUDE_CACHE_SUPPORT */


#if defined(INCLUDE_MMU)

    /* Install the appropriate MMU library and translation routines */

    mmuArm920tLibInstall (NULL, NULL);

#endif /* defined(INCLUDE_MMU) */


    return;
    }


#if defined(INCLUDE_PCI)
/*******************************************************************************
*
* sysKs8695pPciInit - initialize the KS8695P PCI bridge controller
*