ks8695end.h

kedin bsp for vxWorks

/* ks8695End.h - END Ethernet driver header for KS8695/P SOHO router */

/* Copyright 1998-2002 Wind River Systems, Inc. */
/* 
 *	Copyright (c) 2002-2003, Micrel Semiconductor
 *
 *	Written 2003 by LIQUN RUAN (RLQ)
 *
 *
 *	The author may be reached as [e-mail]
 *	Micrel Semiconductor
 *	1931 Fortune Dr.
 *	San Jose, CA 95131
 *
 *	This END Ethernet driver is for Micrel's KS8695/KS8695P SOHO Router Chipset.
 */

/*
modification history
--------------------
	09/18/2003, RLQ,  First created for KS8695/P SOHO Router END ethernet driver
*/

#ifndef __INCKS8695END_H
#define __INCKS8695END_H

#ifdef __cplusplus
extern "C" {
#endif

#include "end.h"
#include "cacheLib.h"
#include "netinet/if_ether.h"

/* define the various levels of debugging if the DRV_DEBUG is defined */    

#ifdef DRV_DEBUG
#    include "logLib.h"
#endif /* DRV_DEBUG */

/* board level/bus specific and architecture specific macros */

#if _BYTE_ORDER==_BIG_ENDIAN
#   define PCI_SWAP(x)  ((ks8695BusEndianess) ? (int)(x) : LONGSWAP((int)(x))) 
#else
#   define PCI_SWAP(x)  (x)
#endif

#if _BYTE_ORDER==_BIG_ENDIAN
#    define REG_SWAP(d,x)  (((d)->flags & LS_MODE_NOSWAP_MASTER) ? \
                                (int)(x) : LONGSWAP((int)(x)))
#else
#    define REG_SWAP(d,x)  (x)
#endif

/* Configuration items */
typedef struct
    {
    UINT collisions;
    UINT crcs;
    UINT aligns;
    UINT missed;
    UINT overruns;
    UINT disabled;
    UINT deferring;
    UINT underruns;
    UINT aborts;
    UINT outofwindow;
    UINT heartbeats;
    UINT badPacket;
    UINT shortPacket;
    UINT tnoerror;
    UINT rnoerror;
    UINT terror;
    UINT rerror;
    UINT overwrite;
    UINT wrapped;
    UINT interrupts;
    UINT reset;
    UINT strayint;
    UINT jabber;
} KS8695_STAT;

#define LN_RMD_OWNED(rmd)       (PCI_SWAP ((rmd)->lnRMD1) & RMD1_OWN)
#define LN_TMD_OWNED(tmd)       (PCI_SWAP ((tmd)->lnTMD1) & TMD1_OWN)

#define LN_PKT_LEN_GET(rmd)     (PCI_SWAP ((rmd)->lnRMD2) - 4)

#define	KS8695_DRV_WAN		0
#define	KS8695_DRV_LAN		1
#define	KS8695_DRV_MAX		(KS8695_DRV_LAN + 1)	

#ifdef	KS8695
#define	KS8695_DRV_HPNA		2		/* emac interface for KS8695 only */
#undef	KS8695_DRV_MAX
#define	KS8695_DRV_MAX		(KS8695_DRV_HPNA + 1)	
#endif

#define TRUE				1
#define FALSE				0

#ifndef	BOOLEAN
#define	BOOLEAN				UINT8
#endif

/* command line options defaults */
#define TXDESC_DEFAULT		32
#define TXDESC_MAX			128
#define TXDESC_MIN			32

#define RXDESC_DEFAULT		32
#define RXDESC_MAX			128
#define RXDESC_MIN			32

#define RXCHECKSUM_DEFAULT	TRUE
#define TXCHECKSUM_DEFAULT	TRUE
#define FLOWCONTROL_DEFAULT	TRUE
#define PBL_DEFAULT			32			/* 0 for unlimited, other value for (4 * x) */
	
/* Supported RX Buffer Sizes */
#define BUFFER_1568			1568		/* 0x620 */
#define BUFFER_2048			2048		/* 0x800 */
#define	BUFFER_4K			4096		/* for KS8695 jumbo frame only */

/* standard ethernet header */
#define ENET_HEADER_SIZE                14
#define MAXIMUM_ETHERNET_PACKET_SIZE	1514
#define MINIMUM_ETHERNET_PACKET_SIZE	60
#define ETH_CRC_LENGTH					4
#define ETH_LENGTH_OF_ADDRESS			6

#define KS8695_ROUNDUP(size, unit) ((unit) * (((size) + (unit) - 1) / (unit)))

#ifndef	BIT
#define BIT(x) (1L << (x))
#endif

#ifndef	REG_MISC_CONTROL

#define REG_MISC_CONTROL		0xEA08

#endif

/* DMA related register offset */
#define	REG_TXCTRL				0x0000
#define	REG_RXCTRL				0x0004
#define	REG_TXSTART				0x0008
#define	REG_RXSTART				0x000c
#define	REG_TXBASE				0x0010
#define	REG_RXBASE				0x0014
#define	REG_STATION_LOW			0x0018
#define	REG_STATION_HIGH		0x001c

#define	REG_MAC0_LOW			0x0080
#define	REG_MAC0_HIGH			0x0084
#define	REG_MAC1_LOW			0x0088
#define	REG_MAC1_HIGH			0x008c
#define	REG_MAC2_LOW			0x0090
#define	REG_MAC2_HIGH			0x0094
#define	REG_MAC3_LOW			0x0098
#define	REG_MAC3_HIGH			0x009c
#define	REG_MAC4_LOW			0x00a0
#define	REG_MAC4_HIGH			0x00a4
#define	REG_MAC5_LOW			0x00a8
#define	REG_MAC5_HIGH			0x00ac
#define	REG_MAC6_LOW			0x00b0
#define	REG_MAC6_HIGH			0x00b4
#define	REG_MAC7_LOW			0x00b8
#define	REG_MAC7_HIGH			0x00bc
#define	REG_MAC8_LOW			0x00c0
#define	REG_MAC8_HIGH			0x00c4
#define	REG_MAC9_LOW			0x00c8
#define	REG_MAC9_HIGH			0x00cc
#define	REG_MAC10_LOW			0x00d0
#define	REG_MAC10_HIGH			0x00d4
#define	REG_MAC11_LOW			0x00d8
#define	REG_MAC11_HIGH			0x00dc
#define	REG_MAC12_LOW			0x00e0
#define	REG_MAC12_HIGH			0x00e4
#define	REG_MAC13_LOW			0x00e8
#define	REG_MAC13_HIGH			0x00ec
#define	REG_MAC14_LOW			0x00f0
#define	REG_MAC14_HIGH			0x00f4
#define	REG_MAC15_LOW			0x00f8
#define	REG_MAC15_HIGH			0x00fc

/* register Bit field defines for Tx Ctrl and (some are shared with RX) */
#define	DMA_SOFTRESET			0x80000000		/* DMA soft reset (shared with RX) */
#define	DMA_UDPCHECKSUM			0x00040000		/* bit 18 (shared with RX) */
#define	DMA_TCPCHECKSUM			0x00020000		/* bit 17 (shared with RX) */
#define	DMA_IPCHECKSUM			0x00010000		/* bit 16 (shared with RX) */
#define	DMA_FLOWCTRL			0x00000200		/* bit 9 (shared with RX) */
#define	DMA_LOOPBACK			0x00000100		/* bit 8 */
#define	DMA_ERRORFRAME			0x00000008		/* bit 3 */
#define	DMA_PADDING				0x00000004		/* bit 2 */
#define	DMA_CRC					0x00000002		/* bit 1 */
#define	DMA_START				0x00000001		/* bit 0 (shared with RX) */

#define	DMA_PBLTMASK			0x3f000000		/* DMA Burst Size bit mask (shared with RX) */
#define	DMA_PBLTSHIFT			24				/* DMA Burst Size bit shift */

/* some bits for RX Ctrl register */
#define	DMA_BROADCAST			0x00000040		/* bit 6 */
#define	DMA_MULTICAST			0x00000020		/* bit 5 */
#define	DMA_UNICAST				0x00000010		/* bit 4 */
#define	DMA_PROMISCUOUS			0x00000004		/* bit 2 */

/* Addition station registers */
#define	DMA_MACENABLE			0x80000000		/* enable/disable additional MAC station address */

enum DMAID {
	DMA_WAN = 0x6000,			/* WAN DMA */
	DMA_LAN = 0x8000,			/* LAN DMA */
#ifdef	KS8695
	DMA_HPNA= 0xA000			/* HPNA DMA */
#endif
};

/* DESC and Data buffer */
#ifdef	_CACHE_ALIGN_SIZE
#define DESC_ALIGNMENT			_CACHE_ALIGN_SIZE
#else
#define DESC_ALIGNMENT			16	/* two dwords */
#endif
#define	RXDESC_LOAN_NUM			4	/* max loaning for Rx */

/* Receive Descriptor */
typedef struct
{
    volatile UINT32 RxFrameControl;
    volatile UINT32 RxDMAFragLen;
    volatile UINT32 RxDMAFragAddr;
    volatile UINT32 RxDMANextPtr;
} RXDESC, *PRXDESC;

#define DESC_OWN_BIT			0x80000000		/* shared with Tx descriptor */

/* In Linux, we use all 32 bits definitions! */
/* Bits related to RxFrameControl */
#define	RFC_FS					0x40000000		/* First Descriptor of the received frame */
#define	RFC_LS					0x20000000		/* Last Descriptor of the received frame */
#define	RFC_IPE					0x10000000		/* IP checksum generation */
#define	RFC_TCPE				0x08000000		/* TCP checksum generation */
#define	RFC_UDPE				0x04000000		/* UDP checksum generation */
#define	RFC_ES					0x02000000		/* Error Summary */
#define	RFC_MF					0x01000000		/* Multicast Frame */

#define	RFC_RE					0x00080000		/* Report on MII/GMII error */
#define	RFC_TL					0x00040000		/* Frame Too Long */
#define	RFC_RF					0x00020000		/* Runt Frame */
#define	RFC_CRC					0x00010000		/* CRC error */
#define	RFC_FT					0x00008000		/* Frame Type */

#define	RFC_SPN_MASK			0x00f00000		/* Switch engine destination port map, 20:23 */
#define	RFC_FL_MASK				0x000007ff		/* Frame Length bit mask, 0:10 */
#define	RFC_FRAMECTRL_MASK		(RFC_FS	| RFC_LS | RFC_ES | RFC_MF | RFC_RE | RFC_TL | RFC_CRC | RFC_FT | RFC_FL_MASK)

/* Bits related to RxDMAFragLen */
#define	RFC_RER					0x02000000		/* Receive End of Ring */
#define	RFC_RBS_MASK			0x000007ff		/* Receive buffer Size bit mask, 0:10 */

/* Transmit descriptor */
typedef struct
{
    volatile UINT32 TxOwnBit;
    volatile UINT32 TxFrameControl;
    volatile UINT32 TxDMAFragAddr;
    volatile UINT32 TxDMANextPtr;
} TXDESC, *PTXDESC;

/* Bits related to TxFrameControl */
#define	TFC_IC					0x80000000		/* Interrupt on completion */
#define	TFC_FS					0x40000000		/* first segment */
#define	TFC_LS					0x20000000		/* last segment */
#define	TFC_IPCKG				0x10000000		/* IP checksum generation */
#define	TFC_TCPCKG				0x08000000		/* TCP checksum generation */
#define	TFC_UDPCKG				0x04000000		/* UDP checksum generation */
#define	TFC_TER					0x02000000		/* Transmit End of Ring */

#define	TFC_SPN_MASK			0x00f00000		/* Switch engine destination port map, 20:23 */
#define	TFC_TBS_MASK			0x000007ff		/* Transmit Buffer Size Mask (0:10) */
#define	TFC_FRAMECTRL_MASK		(TFC_IC	| TFC_FS | TFC_LS | TFC_SPN_MASK | TFC_TBS_MASK)

/* Interrupt related (shared among IMR, IER, ISR, IPR, and IQR) */
#define	INT_WAN_LINK			0x80000000		/* WAN link change interrupt */
#define	INT_WAN_TX				0x40000000		/* WAN Tx complete interrupt */
#define	INT_WAN_RX				0x20000000		/* WAN Rx complete interrupt */
#define	INT_WAN_TX_UNAVIAL		0x10000000		/* WAN Tx desc unavailable interrupt */
#define	INT_WAN_RX_UNAVIAL		0x08000000		/* WAN Rx desc unavailable interrupt */
#define	INT_WAN_TX_STOPPED		0x04000000		/* WAN Tx stopped interrupt */
#define	INT_WAN_RX_STOPPED		0x02000000		/* WAN Rx stopped interrupt */

#define	INT_WAN_MASK			0x7e000000		/* not include LINK interrupt bit */

#define	INT_AMBA_BUS_ERROR		0x01000000		/* AMBA bus error interrupt */

#define	INT_HPNA_TX				0x00800000		/* HPNA Tx complete interrupt */
#define	INT_HPNA_RX				0x00400000		/* HPNA Rx complete interrupt */
#define	INT_HPNA_TX_UNAVIAL		0x00200000		/* HPNA Tx desc unavailable interrupt */
#define	INT_HPNA_RX_UNAVIAL		0x00100000		/* HPNA Rx desc unavailable interrupt */
#define	INT_HPNA_TX_STOPPED		0x00080000		/* HPNA Tx stopped interrupt */
#define	INT_HPNA_RX_STOPPED		0x00040000		/* HPNA Rx stopped interrupt */

#define	INT_HPNA_MASK			0x00fc0000

#define	INT_LAN_TX				0x00020000		/* LAN Tx complete interrupt */
#define	INT_LAN_RX				0x00010000		/* LAN Rx complete interrupt */
#define	INT_LAN_TX_UNAVIAL		0x00008000		/* LAN Tx desc unavailable interrupt */
#define	INT_LAN_RX_UNAVIAL		0x00004000		/* LAN Rx desc unavailable interrupt */
#define	INT_LAN_TX_STOPPED		0x00002000		/* LAN Tx stopped interrupt */
#define	INT_LAN_RX_STOPPED		0x00001000		/* LAN Rx stopped interrupt */

#define	INT_LAN_MASK			0x0003f000

#define	INT_DMA_MASK			0xfefff000		/* interrupt bit mask for DMA (WAN, HPNA and LAN) */

#define	INT_DMA_STOP_MASK		(INT_WAN_TX_STOPPED | INT_WAN_RX_STOPPED | INT_HPNA_TX_STOPPED | INT_HPNA_RX_STOPPED | INT_LAN_TX_STOPPED | INT_LAN_RX_STOPPED)
#define	INT_TX_BIT				BIT(5)
#define	INT_RX_BIT				BIT(4)
#define	INT_TX_UNAVAIL_BIT		BIT(3)
#define	INT_RX_UNAVAIL_BIT		BIT(2)
#define	INT_TX_STOPPED_BIT		BIT(1)
#define	INT_RX_STOPPED_BIT		BIT(0)

/* MAC address */
#define	MAC_ADDRESS_LEN			6
#define	MAC_MAX_EXTRA			16

typedef enum {
	LED_SPEED,			/* 0 */
	LED_LINK,
	LED_FD,				/* full duplex */
	LED_COLLISION,
	LED_ACTIVITY,
	LED_FD_COLLISION,	/* full duplex/collision */
	LED_LINK_ACTIVITY,	/* link/activities */
} LED_SELECTOR;

/* register Bit field for Switch control 0 */
#define	SW_CTRL0_AUTO_FAST_AGING	0x00100000	/* automic fast aging when link changed detected */
#define	SW_CTRL0_ERROR_PKT		0x00080000		/* pass all error packets */
#define	SW_CTRL0_ENABLE_PORT5	0x00040000		/* enable port 5 flow control */
#define	SW_CTRL0_ENABLE_PORTS	0x00020000		/* enable flow control for port 1 - 4 */
#define	SW_CTRL0_BUFFER_SHARE	0x00010000		/* buffer share mode */
#define	SW_CTRL0_AGING_ENABLE	0x00008000		/* aging enable */
#define	SW_CTRL0_FAST_AGING		0x00004000		/* fast aging enable */
#define	SW_CTRL0_FAST_BACKOFF	0x00002000		/* fast back off */
#define	SW_CTRL0_MISMATCH_DISCARD	0x00001000	/* VLAN mismatch discard */
#define	SW_CTRL0_NO_BCAST_STORM_PROT	0x00000800		/* no broadcast storm proection tp ,cast pkts */
#define	SW_CTRL0_PREAMBLE_MODE	0x00000400		/* back pressure mode */
#define	SW_CTRL0_FLOWCTRL_FAIR	0x00000200		/* flow control fair mode */
#define	SW_CTRL0_COLLISION_DROP	0x00000100		/* no excessive collision drop */
#define	SW_CTRL0_LEN_CHECKING	0x00000080		/* enforced max length checking */
#define	SW_CTRL0_6K_BUFFER		0x00000040		/* 6K byte buffer per port reserved for high priority pkts */
#define	SW_CTRL0_BACK_PRESSURE	0x00000020		/* back pressure enable */
#define	SW_CTRL0_SWITCH_ENABLE	0x00000001		/* enable switch bit */

/* register Bit field for Auto Regotiation */
#define	SW_AUTONEGO_COMPLETE	0x00004000		/* auto nego completed */
#define	SW_AUTONEGO_RESTART		0x00002000		/* auto nego restart */
#define	SW_AUTONEGO_ADV_PUASE	0x00001000		/* auto nego advertise PAUSE */
#define	SW_AUTONEGO_ADV_100FD	0x00000800		/* auto nego advertise 100 FD */
#define	SW_AUTONEGO_ADV_100HD	0x00000400		/* auto nego advertise 100 HD */
#define	SW_AUTONEGO_ADV_10FD	0x00000200		/* auto nego advertise 10 FD */
#define	SW_AUTONEGO_ADV_10HD	0x00000100		/* auto nego advertise 10 HD */
#define	SW_AUTONEGO_STAT_LINK	0x00000080		/* auto nego link status */
#define	SW_AUTONEGO_STAT_DUPLEX	0x00000040		/* auto nego duplex status (solved) */
#define	SW_AUTONEGO_STAT_SPEED	0x00000020		/* auto nego speed status (solved) */
#define	SW_AUTONEGO_PART_PAUSE	0x00000010		/* auto nego parterner pause */
#define	SW_AUTONEGO_PART_100FD	0x00000008		/* auto nego parterner 100 FD */
#define	SW_AUTONEGO_PART_100HD	0x00000004		/* auto nego parterner 100 HD */
#define	SW_AUTONEGO_PART_10FD	0x00000002		/* auto nego parterner 10 FD */
#define	SW_AUTONEGO_PART_10HD	0x00000001		/* auto nego parterner 10 HD */

#define	SW_AUTONEGO_ADV_MASK	0x00001f00

#define	SW_MAX_LAN_PORTS		4				/* max LAN ports */

/* bits for SNMP data register (SEMCD) */
#ifndef	CONFIG_ARCH_KS8695P
#define	SW_SNMP_DATA_VALID	0x80000000		/* counter value is valid */
#define	SW_SNMP_DATA_OVERFLOW	0x40000000		/* counter is overflow */
#else
#define	SW_SNMP_DATA_OVERFLOW	0x80000000		/* counter is overflow */
#define	SW_SNMP_DATA_VALID	0x40000000		/* counter value is valid */
#endif

enum PORTS {
	SW_PORT_1 = 0,
	SW_PORT_2,
	SW_PORT_3,
	SW_PORT_4
};

/* bits related to power management */
#define	POWER_POWERDOWN			0x00000010		/* port power down */
#define	POWER_DMDX_DISABLE		0x00000008		/* disable auto MDI/MDIX */
#define	POWER_FORCE_MDIX		0x00000004		/* if auto MDI/MDIX is disabled, force PHY into MDIX mode */