ks8695p.h

kedin bsp for vxWorks

#define KS8695_E83C			0xE83C

/* Port 1-4 and 5 Configuration Register Set 2 */
#define KS8695_SEP1C2			0xE810
#define KS8695_E810			0xE810
#define KS8695_SEP2C2			0xE81C
#define KS8695_E81C			0xE81C
#define KS8695_SEP3C2			0xE828
#define KS8695_E828			0xE828
#define KS8695_SEP4C2			0xE834
#define KS8695_E834			0xE834
#define KS8695_SEP5C2			0xE840
#define KS8695_E840			0xE840

#define	KS8695_SEPC2_VLAN_FILTER	0x10000000	/* Ingress VLAN filtering bit 28 */
#define	KS8695_SEPC2_DISCARD_NON_PVID	0x08000000	/* discard non PVID packets, bit 27 */
#define	KS8695_SEPC2_FORCE_FLOW_CTRL	0x04000000	/* force flow control, bit 26 */
#define	KS8695_SEPC2_BACK_PRESSURE_EN	0x02000000	/* back pressure enable, bit 25 */

#define	KS8695_SEPC2_TX_H_RATECTRL_MASK	0x00FFF000	/* Tx high priority rate control bit 23:12 */
#define	KS8695_SEPC2_TX_L_RATECTRL_MASK	0x00000FFF	/* Tx low priority rate control bit 11:0 */

/* Port 1-4 and 5 Configuration Register Set 3 */
#define KS8695_SEP1C3			0xE814
#define KS8695_E814			0xE814
#define KS8695_SEP2C3			0xE820
#define KS8695_E820			0xE820
#define KS8695_SEP3C3			0xE82C
#define KS8695_E82C			0xE82C
#define KS8695_SEP4C3			0xE838
#define KS8695_E838			0xE838
#define KS8695_SEP5C3			0xE844
#define KS8695_E844			0xE844

#define	KS8695_SEPC3_RX_H_RATECTRL_MASK	0xFFF00000	/* Rx high priority rate control bit 31:20 */
#define	KS8695_SEPC3_RX_L_RATECTRL_MASK	0x000FFF00	/* Rx low priority rate control bit 19:8 */
#define	KS8695_SEPC3_RX_DIF_RATECTRL_EN	0x00000080	/* Rx differential priority rate control enable bit 7 */
#define	KS8695_SEPC3_RX_L_RATECTRL_EN	0x00000040	/* Rx low priority rate control enable bit 6 */
#define	KS8695_SEPC3_RX_H_RATECTRL_EN	0x00000020	/* Rx high priority rate control enable bit 5 */
#define	KS8695_SEPC3_RX_L_RATEFLOW_EN	0x00000010	/* Rx low priority rate flow control enable bit 4 */
#define	KS8695_SEPC3_RX_H_RATEFLOW_EN	0x00000008	/* Rx high priority rate flow control enable bit 3 */
#define	KS8695_SEPC3_TX_DIF_RATECTRL_EN	0x00000004	/* Tx low priority rate control enable bit 2 */
#define	KS8695_SEPC3_TX_L_RATECTRL_EN	0x00000002	/* Tx low priority rate control enable bit 1 */
#define	KS8695_SEPC3_TX_H_RATECTRL_EN	0x00000001	/* Tx high priority rate control enable bit 0 */

/* Port auto negotiation related registers */
/* bit definition is same as KS8695 */
#define KS8695_SEP12AN			0xE848
#define KS8695_E848			0xE848
#define KS8695_SEP34AN			0xE84C
#define KS8695_E84C			0xE84C

/* backward compatible */
#undef KS8695_SWITCH_AUTO0
#undef KS8695_SWITCH_AUTO1
#define KS8695_SWITCH_AUTO0		0xE848
#define KS8695_SWITCH_AUTO1		0xE84C

/* Indirect Access Control register */
#define KS8695_SEIAC			0xE850
#define KS8695_E850			0xE850
#define KS8695_SEIADH2			0xE854
#define KS8695_E854			0xE854
#define KS8695_SEIADH1			0xE858
#define KS8695_E858			0xE858
#define KS8695_SEIADL			0xE85C
#define KS8695_E85C			0xE85C

#define	KS8695_SEIAC_READ		0x00001000	/* bit 12 */
#define	KS8695_SEIAC_WRITE		0x00000000	/* bit 12 not set*/
/* table select bit 11:10 */
#define	KS8695_SEIAC_TAB_STATIC		0x00000000
#define	KS8695_SEIAC_TAB_VLAN		0x00000400
#define	KS8695_SEIAC_TAB_DYNAMIC	0x00000800
#define	KS8695_SEIAC_TAB_MIB		0x00000C00
#define	KS8695_SEIAC_INDEX_MASK		0x000003FF	/* bit 9:0 */

/* Advanced Feature Control register */
/* bit definition is same as KS8695 */
#define KS8695_SEAFC			0xE860
#define KS8695_SEDSCPH			0xE864
#define KS8695_SEDSCPL			0xE868
#define KS8695_SEMAH			0xE86C
#define KS8695_SEMAL			0xE870

/* backward compatible */
#undef	KS8695_SWITCH_ADVANCED
#undef	KS8695_DSCP_HIGH
#undef	KS8695_DSCP_LOW
#undef	KS8695_SWITCH_MAC_HIGH
#undef	KS8695_SWITCH_MAC_LOW

#define KS8695_SWITCH_ADVANCED		0xE860
#define KS8695_DSCP_HIGH		0xE864
#define KS8695_DSCP_LOW			0xE868
#define KS8695_SWITCH_MAC_HIGH		0xE86C
#define KS8695_SWITCH_MAC_LOW		0xE870

/* LAN PHY power management related registers */
/* bit definition is same as KS8695, except new bits 30:26 */
#define KS8695_LPPM12			0xE874
#define KS8695_LPPM34			0xE878

/* new bits */
#define	KS8695_LPPM_PHY_LOOPBACK	0x4000	/* phy loopback bit 14 */
#define	KS8695_LPPM_RMT_LOOPBACK	0x2000	/* remote loopback bit 13 */
#define	KS8695_LPPM_PHY_ISOLATE		0x1000	/* phy isolate bit 12 */
#define	KS8695_LPPM_SOFT_RESET		0x0800	/* phy isolate bit 11 */
#define	KS8695_LPPM_FORCE_LINK		0x0400	/* force link isolationi bit 10 */
/* shift bit defined already */

/* backward compatible */
#undef	KS8695_LAN12_POWERMAGR
#undef	KS8695_LAN34_POWERMAGR
#define KS8695_LAN12_POWERMAGR		0xE874
#define KS8695_LAN34_POWERMAGR		0xE878

/* Digital Testing Status and Control Registers */
#define KS8695_SEDTS			0xE87C		/* Digital Testing status & control register */
#define KS8695_SEATCS			0xE880		/* Analog Testing status and control register */

/* new bits for WAN PHY Power mangement register */
#define	KS8695_WPPM_PHY_LOOPBACK	0x00004000	/* phy loopback bit 14 */
#define	KS8695_WPPM_RMT_LOOPBACK	0x00002000	/* remote loopback bit 13 */
#define	KS8695_WPPM_PHY_ISOLATION	0x00001000	/* phy isolationi bit 12 */
#define	KS8695_WPPM_FORCE_LINK		0x00000400	/* force link isolationi bit 10 */

#endif	/* KS8695 */

#define PCI_BMEM_PREFETCH      0x8
#define PCI_BMEM_PREFLMIT4	   0x00000000 
#define PCI_BMEM_PREFLMIT8	   0x10000000 
#define PCI_BMEM_PREFLMIT16	   0x20000000  	
#define PCI_CONF_DISEXT        0x10000000

#define PCI_PCI_MODE           0x00000000
#define PCI_MINIPCI_MODE       0x20000000
#define PCI_CARDBUS_MODE       0x40000000
#define PCI_ENABLE_ADDTRAN     0x80000000

#define FURE				   1
#define FALSE	               0
#define PCI_NOEXIST            0xFFFF 

#define PCI_REGINDEX_IDS       (0 << 2)  	
#define PCI_REGINDEX_STCMD     (1 << 2)
#define PCI_REGINDEX_REV       (2 << 2)
#define PCI_REGINDEX_HEAD      (3 << 2)
#define PCI_REGINDEX_BASE      (4 << 2)
#define PCI_REGINDEX_SUBIDS    (11 << 2) 
#define PCI_REGINDEX_ROMBASE   (12 << 2)
#define PCI_REGINDEX_INT       (15 << 2)

#define PCI_BRIDGE_CLASS	   0x6
#define PCI_TO_PCIBRIDGE       0x4
#define PCI_MAX_SLOT			8
#define PCI_NOTEXIST			0xFFFF
#define PCI_SUBSYSTEMID         0x86950000
#define PCI_SUBVENDORID			0x10


/* other parameters to set up FLASH/ROM/SRAM configuration registers */
#define ROM_BANK_ACCTM2     0x0
#define ROM_BANK_ACCTM3     (0x1 << 4)
#define ROM_BANK_ACCTM4     (0x2 << 4)
#define ROM_BANK_ACCTM5     (0x3 << 4)
#define ROM_BANK_ACCTM6     (0x4 << 4)
#define ROM_BANK_ACCTM7     (0x5 << 4)
#define ROM_BANK_ACCTM8     (0x6 << 4)
#define ROM_BANK_ACCTM9     (0x7 << 4)
     
#define ROM_BANK_PACTM2     0x0
#define ROM_BANK_PACTM3     (0x1 << 2)
#define ROM_BANK_PACTM4     (0x2 << 2)
#define ROM_BANK_PACTM5     (0x3 << 2)

#define ROM_BANK_PMOD0      0x0
#define ROM_BANK_PMOD1      0x1
#define ROM_BANK_PMOD2      0x2
#define ROM_BANK_PMOD3      0x3

#define ROM_GENERAL_SETTING 0x00000001 

/* SDRAM banks */
#define SDRAM_NOP_COMD      0x30000
#define SDRAM_PRECHARGE_CMD 0x10000
#define SDRAM_REFRESH_TIMER 360                               
#define SDRAM_MODE_COMD     0x20033  
#define SDRAM_RASCAS        0x0000000A

#define SDRAM_BANK_COLAB8   0x0
#define SDRAM_BANK_COLAB9   (0x1 << 8)
#define SDRAM_BANK_COLAB10  (0x2 << 8)
#define SDRAM_BANK_COLAB11  (0x3 << 8)

#define SDRAM_UNM_BANKS2    0x0
#define SDRAM_UNM_BANKS4    (0x1 << 3)

#define SDRAM_BANKS_DBW0    0x0
#define SDRAM_BANKS_DBW8    (0x1 << 1)
#define SDRAM_BANKS_DBW16   (0x2 << 1)
#define SDRAM_BANKS_DBW32   (0x3 << 1)


#define FLASH_BANK	    0x00000000
#define FLASH_BANK_SIZE     0x00400000 
#define SDRAM_BANK0_SIZE    0x01000000
#define SDRAM_BANK1_SIZE    0x01000000
#define REMAPPED_FLASH_BANK 0x02800000   /* at 40MB */
#define SDRAM_TOTAL_SIZE    0x02000000


#define SDRAM_BANK_0   FLASH_BANK_SIZE  
#define SDRAM_BANK_1   (SDRAM_BANK_0 + SDRAM_BANK0_SIZE)     
#define SDRAM_BANK_END (SDRAM_BANK_1 + SDRAM_BANK1_SIZE)

#define REMAPPED_SDRAM_BANK_0   0x0
#define REMAPPED_SDRAM_BANK_1   (REMAPPED_SDRAM_BANK_0 + SDRAM_BANK0_SIZE)  
#define REMAPPED_SDRAM_BANK_END (REMAPPED_SDRAM_BANK_1 + SDRAM_BANK1_SIZE)  

#define TMP_SDRAM_REG0 (((SDRAM_BANK_0+SDRAM_BANK0_SIZE-1)>>16)<<22)|((SDRAM_BANK_0>>16)<<12)|SDRAM_UNM_BANKS4|SDRAM_BANKS_DBW32
#define TMP_SDRAM_REG1 (((SDRAM_BANK_1+SDRAM_BANK1_SIZE-1)>>16)<<22)|((SDRAM_BANK_1>>16)<<12)|SDRAM_UNM_BANKS4|SDRAM_BANKS_DBW32

#define FLASH_ROM_START  REMAPPED_FLASH_BANK   
#define SDRAM_START      SDRAM_BANK_0 


#define RAM_LIMIT       REMAPPED_SDRAM_BANK_END  
 
#define ABT_STACK       RAM_LIMIT 
#define UNDEF_STACK     ABT_STACK - 1024 
#define SVC_STACK       UNDEF_STACK - 1024    
#define IRQ_STACK       SVC_STACK - 2048      
#define FIQ_STACK       IRQ_STACK - 4096
#define SYS_STACK       FIQ_STACK - 4096
#define USR_STACK       SYS_STACK - 4096
#define RAM_LIMIT_TMP   SDRAM_BANK_END - 2048

/* External I/O banks difintions */
#define EXT_IO_BANK_SIZE    0x00400000    /* 4MB */
#define EXT_IO_BANK_0	    0x03200000    /* 50MB */
#define EXT_IO_BANK_1	    (EXT_IO_BANK_0 + EXT_IO_BANK_SIZE)  /* 54 MB */
#define EXT_IO_BANK_2	    (EXT_IO_BANK_1 + EXT_IO_BANK_SIZE)  /* 58 MB */

#define EXT_IOBANK_CLOCK0   0x0
#define EXT_IOBANK_CLOCK1   0x1
#define EXT_IOBANK_CLOCK2   0x2
#define EXT_IOBANK_CLOCK3   0x3
#define EXT_IOBANK_CLOCK4   0x4
#define EXT_IOBANK_CLOCK5   0x5
#define EXT_IOBANK_CLOCK6   0x6
#define EXT_IOBANK_CLOCK7   0x7


#define FLASH_REG      (((FLASH_BANK+FLASH_BANK_SIZE-1)>>16)<<22)|((FLASH_BANK>>16)<<12)|ROM_BANK_PMOD0|ROM_BANK_ACCTM9
#define REM_FLASH_REG  (((REMAPPED_FLASH_BANK+FLASH_BANK_SIZE-1)>>16)<<22)|((REMAPPED_FLASH_BANK>>16)<<12)|ROM_BANK_PMOD0|ROM_BANK_ACCTM9

#define REM_SDRAM_REG0 (((REMAPPED_SDRAM_BANK_0+SDRAM_BANK0_SIZE-1)>>16)<<22)|((REMAPPED_SDRAM_BANK_0>>16)<<12)|SDRAM_UNM_BANKS4|SDRAM_BANKS_DBW32
#define REM_SDRAM_REG1 (((REMAPPED_SDRAM_BANK_1+SDRAM_BANK1_SIZE-1)>>16)<<22)|((REMAPPED_SDRAM_BANK_1>>16)<<12)|SDRAM_UNM_BANKS4|SDRAM_BANKS_DBW32


#define EXTIO_REG0  (((EXT_IO_BANK_0+EXT_IO_BANK_SIZE-1)>>16)<<22)|((EXT_IO_BANK_0>>16)<<12)|(EXT_IOBANK_CLOCK1<<3)
#define EXTIO_REG1  (((EXT_IO_BANK_1+EXT_IO_BANK_SIZE-1)>>16)<<22)|((EXT_IO_BANK_1>>16)<<12)|(EXT_IOBANK_CLOCK1<<3)
#define EXTIO_REG2  (((EXT_IO_BANK_2+EXT_IO_BANK_SIZE-1)>>16)<<22)|((EXT_IO_BANK_2>>16)<<12)|(EXT_IOBANK_CLOCK1<<3)

#define INIT_GPIO_MODE   0xFFFF
#define INIT_GPIO_DATA   0
#define INIT_GPIO_CTRL   0
#define INIT_INT         0





/* definitions for the AMBA UART */

#define N_KS8695P_UART_CHANNELS	1		/* number of KS8695P UART chans */
#define N_SIO_CHANNELS		N_KS8695P_UART_CHANNELS
#define N_UART_CHANNELS		N_KS8695P_UART_CHANNELS


#define UART_0_BASE_ADR		REG_IO_BASE	/* UART 0 base address */





#define KS8695P_REG(reg) \
	(*(volatile UINT32 *)((UINT32)REG_IO_BASE + (reg)))

#define KS8695P_REG_READ(reg, result) \
	(result) = (KS8695P_REG(reg))

#define KS8695P_REG_WRITE(reg, data) \
	(KS8695P_REG(reg)) = (data)

#define KS8695P_REG_BIT_SET(reg, data) \
	(KS8695P_REG(reg)) |= (data)

#define KS8695P_REG_BIT_CLR(reg, data) \
	(KS8695P_REG(reg)) &= ~(data)




#define KS8695P_SYSCLK   25000000		/* System bus clock */



#ifdef __cplusplus
}
#endif

#endif	/* INCks8695p */