ks8695p.h

kedin bsp for vxWorks

 * slot. This can be overridden, if we know differently.
 */

#if defined (KS8695P_ENET_FIXED_BUF_ADRS)
#define KS8695P_FEI_BUF_SIZE	0x40000
#define KS8695P_FEI_NUM_CFDS	28
#define KS8695P_FEI_NUM_RFDS	28
#else
#define KS8695P_FEI_BUF_SIZE	0x49000
#define KS8695P_FEI_NUM_CFDS	32
#define KS8695P_FEI_NUM_RFDS	32
#endif





/* MICREL_KS8695P Registers */



#define SYSTEN_BUS_CLOCK_125  0x0 
#define SYSTEN_BUS_CLOCK_100  0x1
#define SYSTEN_BUS_CLOCK_625  0x2
#define SYSTEN_BUS_CLOCK_050  0x3
#define SYSTEN_BUS_CLOCK_417  0x4
#define SYSTEN_BUS_CLOCK_333  0x5
#define SYSTEN_BUS_CLOCK_313  0x6
#define SYSTEN_BUS_CLOCK_025  0x7

/* cpu parameters */
#define MODE_USR    0x10
#define MODE_FIQ    0x11
#define MODE_IRQ    0x12
#define MODE_SVC    0x13
#define MODE_ABT    0x17
#define MODE_UNDEF  0x1B
#define MODE_SYS    0x1F  /* available on ARM Arch 4 and later  */



#define REG_IO_BASE            0x03FF0000
#define REG_SYSTEN_CONFIG      0x00
#define REG_SYSTEN_BUS_CLOCK   0x04


/* new registers specific to KS8695P */
/* PCI related */
#define	REG_PCI_CRCFID		0x2000
#define	REG_PCI_CRCFCS		0x2004
#define	REG_PCI_CRCFRV		0x2008
#define	REG_PCI_CRCFLT		0x200c
#define	REG_PCI_CRCBMA		0x2010
#define	REG_PCI_CRCBA0		0x2014

#define	REG_PCI_CRCSID		0x202c

#define	REG_PCI_CRCFIT		0x203c

/* note that PCI configuration bits are defined in pci.h already */

/* bridge configuration related registers */
#define	REG_PCI_PBCA		0x2100
#define	REG_PCI_PBCD		0x2104


/* bridge mode related registers */
#define	REG_PCI_PBM		0x2200
#define	REG_PCI_PBCS		0x2204
#define	REG_PCI_PMBA		0x2208
#define	REG_PCI_PMBAC		0x220c
#define	REG_PCI_PMBAM		0x2210
#define	REG_PCI_PMBAT		0x2214
#define	REG_PCI_PIOBA		0x2218
#define	REG_PCI_PIOBAC		0x221c
#define	REG_PCI_PIOBAM		0x2220
#define	REG_PCI_PIOBAT		0x2224


#define	PMBAC_TRANS_ENABLE	0x80000000



/*i/o control registers offset difinitions*/
#define REG_IO_CTRL0           0x4000
#define REG_IO_CTRL1           0x4004
#define REG_IO_CTRL2           0x4008
#define REG_IO_CTRL3           0x400C

/*memory control registers offset difinitions*/
#define REG_MEM_CTRL0          0x4010
#define REG_MEM_CTRL1          0x4014
#define REG_MEM_CTRL2          0x4018
#define REG_MEM_CTRL3          0x401C
#define REG_MEM_GENERAL        0x4020
#define REG_SDRAM_CTRL0        0x4030 
#define REG_SDRAM_CTRL1        0x4034
#define REG_SDRAM_GENERAL      0x4038
#define REG_SDRAM_BUFFER       0x403C
#define REG_SDRAM_REFRESH      0x4040    

/*WAN control registers offset difinitions*/
#define REG_WAN_DMA_TX         0x6000
#define REG_WAN_DMA_RX         0x6004
#define REG_WAN_DMA_TX_START   0x6008    
#define REG_WAN_DMA_RX_START   0x600C    
#define REG_WAN_TX_LIST        0x6010
#define REG_WAN_RX_LIST        0x6014
#define REG_WAN_MAC_LOW        0x6018
#define REG_WAN_MAC_HIGH       0x601C
#define REG_WAN_MAC_ELOW       0x6080
#define REG_WAN_MAC_EHIGH      0x6084

/*LAN control registers offset difinitions*/
#define REG_LAN_DMA_TX         0x8000
#define REG_LAN_DMA_RX         0x8004
#define REG_LAN_DMA_TX_START   0x8008    
#define REG_LAN_DMA_RX_START   0x800C    
#define REG_LAN_TX_LIST        0x8010
#define REG_LAN_RX_LIST        0x8014
#define REG_LAN_MAC_LOW        0x8018
#define REG_LAN_MAC_HIGH       0x801C
#define REG_LAN_MAC_ELOW       0x8080
#define REG_LAN_MAC_EHIGH      0x8084

/*UART control registers offset difinitions*/
#define REG_UART_RX_BUFFER     0xE000
#define REG_UART_TX_HOLDING    0xE004
#define REG_UART_FIFO_CTRL     0xE008
#define REG_UART_LINE_CTRL     0xE00C
#define REG_UART_MODEM_CTRL    0xE010
#define REG_UART_LINE_STATUS   0xE014
#define REG_UART_MODEM_STATUS  0xE018
#define REG_UART_DIVISOR       0xE01C
#define REG_UART_STATUS        0xE020


#define REG_URFC_URFRT_14      0x000000C0
#define REG_URFC_TX_RST        0x00000004
#define REG_URFC_RX_RST        0x00000002
#define REG_URFC_ENABLE        0x00000001

#define REG_URLC_TWO_STOP_BIT  0x00000004
#define REG_URLC_8_BIT         0x00000003


#define REG_URLS_URTE          0x00000040
#define REG_URLS_URTHRE        0x00000020
#define REG_URLS_RX_DR         0x00000001


#define UART_BAUD_RATE_256000  0x61
#define UART_BAUD_RATE_128000  0xC3
#define UART_BAUD_RATE_115200  0xD9
#define UART_BAUD_RATE_56000   0x1BE
#define UART_BAUD_RATE_38400   0x28B
#define UART_BAUD_RATE_19200   0x516
#define UART_BAUD_RATE_9600    0xA2C






/*Interrupt controlller registers offset difinitions*/
#define REG_INT_CONTL          0xE200
#define REG_INT_ENABLE         0xE204
#define REG_INT_STATUS         0xE208
#define REG_INT_WAN_PRIORITY   0xE20C
#define REG_INT_LAN_PRIORITY   0xE214
#define REG_INT_TIMER_PRIORITY 0xE218
#define REG_INT_UART_PRIORITY  0xE21C
#define REG_INT_EXT_PRIORITY   0xE220
#define REG_INT_CHAN_PRIORITY  0xE224
#define REG_INT_BUSERROR_PRO   0xE228
#define REG_INT_MASK_STATUS    0xE22C
#define REG_FIQ_PEND_PRIORITY  0xE230
#define REG_IRQ_PEND_PRIORITY  0xE234



#define REG_INT_WMLC    0x80000000 
#define REG_INT_WMT     0x40000000 
#define REG_INT_WMR     0x20000000
#define REG_INT_WMTBU   0x10000000
#define REG_INT_WMRBU   0x08000000
#define REG_INT_WMTPS   0x04000000
#define REG_INT_WMRPS   0x02000000
#define REG_INT_ABERS   0x01000000
#define REG_INT_LMTS    0x00020000
#define REG_INT_LMRS    0x00010000
#define REG_INT_LMTBU   0x00008000
#define REG_INT_LMRBU   0x00004000
#define REG_INT_LMTPS   0x00002000
#define REG_INT_LMRPS   0x00001000
#define REG_INT_UM      0x00000800
#define REG_INT_ULE     0x00000400
#define REG_INT_UR      0x00000200
#define REG_INT_UT      0x00000100
#define REG_INT_T1      0x00000080
#define REG_INT_T0      0x00000040
#define REG_INT_EXTI3   0x00000020
#define REG_INT_EXTI2   0x00000010
#define REG_INT_EXTI1   0x00000008
#define REG_INT_EXTI0   0x00000004
#define REG_INT_CCT     0x00000002
#define REG_INT_CCR     0x00000001

 
 




/*timer registers offset difinitions*/
#define REG_TIMER_CTRL         0xE400
#define REG_TIMER1             0xE404
#define REG_TIMER0             0xE408
#define REG_TIMER1_PCOUNT      0xE40C
#define REG_TIMER0_PCOUNT      0xE410



#define REG_TIMER_CTRL_TOUT1E  0x00000002
#define REG_TIMER_CTRL_TOUT0E  0x00000001






/*GPIO registers offset difinitions*/
#define REG_GPIO_MODE          0xE600
#define REG_GPIO_CTRL          0xE604
#define REG_GPIO_DATA          0xE608

/*SWITCH registers offset difinitions*/
#define REG_SWITCH_CTRL0       0xE800
#define REG_DEVICE_ID          0xEA00
#define REG_REVISION_ID        0xEA04

#define REG_WAN_CONTROL        0xEA0C
/*newly added registers*/
#define REG_WAN_POWERMAGR      0xEA10
#define REG_WAN_PHY_CONTROL    0xEA14
#define REG_WAN_PHY_STATUS     0xEA18


#define REG_SWITCH_CTRL1       0xE804
#define REG_SWITCH_CTRL2       0xE808
#define REG_SWITCH_PORT11      0xE80C
#define REG_SWITCH_PORT12      0xE810
#define REG_SWITCH_PORT13      0xE814
#define REG_SWITCH_PORT21      0xE818
#define REG_SWITCH_PORT22      0xE81C
#define REG_SWITCH_PORT23      0xE820
#define REG_SWITCH_PORT31      0xE824
#define REG_SWITCH_PORT32      0xE828
#define REG_SWITCH_PORT33      0xE82C
#define REG_SWITCH_PORT41      0xE830
#define REG_SWITCH_PORT42      0xE834
#define REG_SWITCH_PORT43      0xE838
#define REG_SWITCH_PORT51      0xE83C
#define REG_SWITCH_PORT52      0xE840
#define REG_SWITCH_PORT53      0xE844
#define REG_SWITCH_AUTO0       0xE848
#define REG_SWITCH_AUTO1       0xE84C
#define REG_SWITCH_IACR        0xE850
#define REG_SWITCH_IADH2       0xE854
#define REG_SWITCH_IADH1       0xE858
#define REG_SWITCH_IADL        0xE85C
#define REG_SWITCH_ADVANCED    0xE860
#define REG_TOS_HIGH           0xE864
#define REG_TOS_LOW            0xE868
#define REG_SWITCH_MAC_HIGH    0xE86C
#define REG_SWITCH_MAC_LOW     0xE870
#define REG_LAN12_POWERMAGR    0xE874
#define REG_LAN34_POWERMAGR    0xE878
#define REG_DIG_TEST           0xE87C
#define REG_ANA_TEST           0xE880
#define REG_WAN_POW_SAVE       0xEA1C

#ifndef	KS8695		/* note that KS8695P is default */
/* most bit definition are same as KS8695, except few new bits */
#define KS8695_SEC0			0xE800
#define KS8695_E800			0xE800

/* new bits */
#define	KS8695_SEC0_BACKOFF_EN		0x80000000	/* new backoff enable for UNH, bit 31 */
#define	KS8695_SEC0_FRAME_LEN_CHECK	0x00020000	/* frame length field check, bit 17 */
#define	KS8695_SEC0_DMA_HALF_DUPLEX	0x00000010	/* LAN DMA port 5 half duplex mode bit 4 */

#define KS8695_SEC1			0xE804
#define KS8695_E804			0xE804

/* new bits */
#define	KS8695_SEC1_NO_IEEE_AN		0x00000800	/* non IEEE specific auto-nego bit 11 */
#define	KS8695_SEC1_TPID_MODE		0x00000400	/* Special TPID mode bit 10 */
#define	KS8695_SEC1_NO_TX_8021X_FLOW_CTRL	0x00000080	/* IEEE 802.1x transmit flow control disable bit 7 */
#define	KS8695_SEC1_NO_RX_8021X_FLOW_CTRL	0x00000040	/* IEEE 802.1x receive flow control disable bit 6 */
#define	KS8695_SEC1_HUGE_PACKET		0x00000020	/* huge packet support bit 5 */
#define	KS8695_SEC1_8021Q_VLAN_EN	0x00000010	/* IEEE 802.1q VLAN enable bit 4 */
#define	KS8695_SEC1_MII_10BT		0x00000002	/* Switch MII 10BT bit 1 */
#define	KS8695_SEC1_NULL_VID		0x00000001	/* null VID replacement bit 0 */

/* Port 1-4 and 5 Configuration Register Set 1 */
/* bit definition is same as KS8695 */
#define KS8695_SEP1C1			0xE80C
#define KS8695_E80C			0xE80C
#define KS8695_SEP2C1			0xE818
#define KS8695_E818			0xE818
#define KS8695_SEP3C1			0xE824
#define KS8695_E824			0xE824
#define KS8695_SEP4C1			0xE830
#define KS8695_E830			0xE830
#define KS8695_SEP5C1			0xE83C