ks8695p.h

kedin bsp for vxWorks

/* ks8695p.h - Micrel KS8695P header file */


/*
modification history
--------------------
9/15/2003  Ritter Yeh  created 
*/

/*
This file contains I/O address and related constants for the Micrel
KS8695P demo board.
*/

#ifndef	INCks8695p
#define	INCks8695p

#ifdef __cplusplus
extern "C" {
#endif

#define TARGET_KS8695P

/* Flash definitions */

#define FLASH_BASE		0x02800000	/* Base address of Flash part */
#define FLASH_BLOCK_NUM		63		/* 64 kB block used as NVRAM */
#define FLASH_ADRS		(FLASH_BASE + (FLASH_BLOCK_NUM * 0x10000))
#define KS8695P_FLASH_SIZE 	0x00400000 	/* Total Flash available. */
#define FLASH_WIDTH		1	  	/* One 8-bit wide parts */
#define FLASH_CHIP_WIDTH        1
#define FLASH_WIDTH_SPECIAL_2			/* see flash28.h */
#define SYS_FLASH_WRITE				/* use enable/disable routines*/




#define BUS		BUS_TYPE_PCI


/* - Hard coded id of the core module we are compiling for. */

#define CORE_MODULE 0

/*
 * interrupt control stuff
 * Note: FIQ is not handled within VxWorks so this is just IRQ
 */


#define KS8695P_INT_NUM_LEVELS	32
#define KS8695P_INT_CSR_MASK	0xFF03FFFF /* Mask out invalid status bits */


/* Interrupt levels */

#define INT_LVL_CCRS		0	/* Communications Channel Receive Status */
#define INT_LVL_CCTS    	1	/* Communications Channel Transmit Status */
#define INT_LVL_EXTI0S		2	/* External Interrupt 0 Status */
#define INT_LVL_EXTI1S  	3	/* External Interrupt 1 Status */
#define INT_LVL_EXTI2S          4	/* External Interrupt 2 Status */
#define INT_LVL_EXTI3S 		5	/* External Interrupt 3 Status */
#define INT_LVL_T0MS   		6	/* Timer 0 Status */
#define INT_LVL_T1MS   		7	/* Timer 1 Status */
#define INT_LVL_UTS		8	/* UART Transmit Status */
#define INT_LVL_URS 		9	/* UART Receive Status */
#define INT_LVL_ULES		10	/* UART Line Error Status */
#define INT_LVL_UMS 		11	/* UART Modem Status */
#define INT_LVL_LMRPSS          12      /* LAN MAC Receive Process Stopped Status */
#define INT_LVL_LMTPSS          13	/* LAN MAC Transmit Process Stopped Status */
#define INT_LVL_LMRBUS   	14	/* LAN MAC Receive Buffer Unavailable Status */
#define INT_LVL_LMTBUS          15	/* LAN MAC Transmit Buffer Unavailable Status */
#define INT_LVL_LMRS		16	/* LAN MAC Receive Status */
#define INT_LVL_LMTS            17	/* LAN MAC Transmit Status */
#define INT_LVL_RESEV18         18      /* Reserved */
#define INT_LVL_RESEV19         19      /* Reserved */
#define INT_LVL_RESEV20         20      /* Reserved */
#define INT_LVL_RESEV21         21      /* Reserved */
#define INT_LVL_RESEV22         22      /* Reserved */
#define INT_LVL_RESEV23         23      /* Reserved */
#define INT_LVL_ABERS		24	/* AMBA Bus Error Response Status */
#define INT_LVL_WMRPSS		25 	/* WAN MAC Receive Process Stopped Status */
#define INT_LVL_WMTPSS          26	/* WAN MAC Transmit Process Stopped Status */
#define INT_LVL_WMRBUS          27	/* WAN MAC Receive Buffer Unavailable Status */
#define INT_LVL_WMTBUS          28	/* WAN MAC Transmit Buffer Unavailable Status */
#define INT_LVL_WMRS		29	/* WAN MAC Receive Status */
#define INT_LVL_WMTS  		30	/* WAN MAC Transmit Status */
#define INT_LVL_WMLCS           31	/* WAN MAC Link Changed Status */


/* interrupt vectors */

#define INT_VEC_CCRS		INUM_TO_IVEC(INT_LVL_CCRS)
#define INT_VEC_CCTS    	INUM_TO_IVEC(INT_LVL_CCTS)
#define INT_VEC_EXTI0S		INUM_TO_IVEC(INT_LVL_EXTI0S)
#define INT_VEC_EXTI1S  	INUM_TO_IVEC(INT_LVL_EXTI1S)
#define INT_VEC_EXTI2S          INUM_TO_IVEC(INT_LVL_EXTI2S)
#define INT_VEC_EXTI3S 		INUM_TO_IVEC(INT_LVL_EXTI3S)
#define INT_VEC_T0MS   		INUM_TO_IVEC(INT_LVL_T0MS)
#define INT_VEC_T1MS   		INUM_TO_IVEC(INT_LVL_T1MS)
#define INT_VEC_UTS		INUM_TO_IVEC(INT_LVL_UTS)
#define INT_VEC_URS 		INUM_TO_IVEC(INT_LVL_URS)
#define INT_VEC_ULES		INUM_TO_IVEC(INT_LVL_ULES)
#define INT_VEC_UMS 		INUM_TO_IVEC(INT_LVL_UMS)
#define INT_VEC_LMRPSS          INUM_TO_IVEC(INT_LVL_LMRPSS)
#define INT_VEC_LMTPSS          INUM_TO_IVEC(INT_LVL_LMTPSS)
#define INT_VEC_LMRBUS   	INUM_TO_IVEC(INT_LVL_LMRBUS)
#define INT_VEC_LMTBUS          INUM_TO_IVEC(INT_LVL_LMTBUS)
#define INT_VEC_LMRS		INUM_TO_IVEC(INT_LVL_LMRS)
#define INT_VEC_LMTS            INUM_TO_IVEC(INT_LVL_LMTS)
#define INT_VEC_RESEV18         INUM_TO_IVEC(INT_LVL_RESEV18)
#define INT_VEC_RESEV19         INUM_TO_IVEC(INT_LVL_RESEV19)
#define INT_VEC_RESEV20         INUM_TO_IVEC(INT_LVL_RESEV20)
#define INT_VEC_RESEV21         INUM_TO_IVEC(INT_LVL_RESEV21)
#define INT_VEC_RESEV22         INUM_TO_IVEC(INT_LVL_RESEV22)
#define INT_VEC_RESEV23         INUM_TO_IVEC(INT_LVL_RESEV23)
#define INT_VEC_ABERS		INUM_TO_IVEC(INT_LVL_ABERS)
#define INT_VEC_WMRPSS		INUM_TO_IVEC(INT_LVL_WMRPSS)
#define INT_VEC_WMTPSS          INUM_TO_IVEC(INT_LVL_WMTPSS)
#define INT_VEC_WMRBUS          INUM_TO_IVEC(INT_LVL_WMRBUS)
#define INT_VEC_WMTBUS          INUM_TO_IVEC(INT_LVL_WMTBUS)
#define INT_VEC_WMRS		INUM_TO_IVEC(INT_LVL_WMRS)
#define INT_VEC_WMTS  		INUM_TO_IVEC(INT_LVL_WMTS)
#define INT_VEC_WMLCS           INUM_TO_IVEC(INT_LVL_WMLCS)




#define SYS_TIMER_INT_LVL (INT_LVL_T0MS)
#define AUX_TIMER_INT_LVL (INT_LVL_T1MS)

/* Add corresponding INT_VEC definitions for intConnect calls. */

#define SYS_TIMER_INT_VEC (INT_VEC_T0MS)
#define AUX_TIMER_INT_VEC (INT_VEC_T1MS)



/* Frequency of counter/timers */

#define SYS_TIMER_CLK	25000000
#define AUX_TIMER_CLK	25000000


#define SYS_CLK_RATE_MIN ((SYS_TIMER_CLK+0xFFFF)/0x10000)
#define SYS_CLK_RATE_MAX 25000


#define AUX_CLK_RATE_MIN ((AUX_TIMER_CLK+0xFFFF)/0x10000)
#define AUX_CLK_RATE_MAX 25000



/* PCI definitions */

/* Interrupt number for PCI */

#define INT_NUM_IRQ0	INT_LVL_EXTI0S


/* Bit field definitions */

#define BIT0                            0x00000001
#define BIT1                            0x00000002
#define BIT2                            0x00000004
#define BIT3                            0x00000008
#define BIT4                            0x00000010
#define BIT5                            0x00000020
#define BIT6                            0x00000040
#define BIT7                            0x00000080
#define BIT8                            0x00000100
#define BIT9                            0x00000200
#define BIT10                           0x00000400
#define BIT11                           0x00000800
#define BIT12                           0x00001000
#define BIT13                           0x00002000
#define BIT14                           0x00004000
#define BIT15                           0x00008000
#define BIT16                           0x00010000
#define BIT17                           0x00020000
#define BIT18                           0x00040000
#define BIT19                           0x00080000
#define BIT20                           0x00100000

/* Handy sizes */

#define SZ_1K                           0x00000400
#define SZ_4K                           0x00001000
#define SZ_8K                           0x00002000
#define SZ_16K                          0x00004000
#define SZ_64K                          0x00010000
#define SZ_128K                         0x00020000
#define SZ_256K                         0x00040000
#define SZ_512K                         0x00080000

#define SZ_1M                           0x00100000
#define SZ_2M                           0x00200000
#define SZ_4M                           0x00400000
#define SZ_8M                           0x00800000
#define SZ_16M                          0x01000000
#define SZ_32M                          0x02000000
#define SZ_64M                          0x04000000
#define SZ_128M                         0x08000000
#define SZ_256M                         0x10000000
#define SZ_512M                         0x20000000

#define SZ_1G                           0x40000000
#define SZ_2G                           0x80000000


/* Local Bus to PCI Bridge definitions */


/* defines for generic pciIoMapLib.c code */

#define PCI_IN_BYTE(x)		*(volatile UINT8 *) (x)
#define PCI_OUT_BYTE(x,y)	*(volatile UINT8 *) (x) = (UINT8)  y
#define PCI_IN_WORD(x)		*(volatile UINT16 *)(x)
#define PCI_OUT_WORD(x,y)	*(volatile UINT16 *)(x) = (UINT16) y
#define PCI_IN_LONG(x)		*(volatile UINT32 *)(x)
#define PCI_OUT_LONG(x,y)	*(volatile UINT32 *)(x) = (UINT32) y

/* restrict use to the first bus, by default */

#define PCI_MAX_BUS 1

/* memory map as seen by the CPU on the local bus */

#define CPU_PCI_IO_ADRS		0x10000000 	/* PCI I/O space base */
#define CPU_PCI_IO_SIZE		0x00010000
#define CPU_PCI_IO_MASK		0xFFFF0000

#define CPU_PCI_CNFG_ADRS	0x11000000	/* PCI config space */
#define CPU_PCI_CNFG_SIZE	0x1000000

#define CPU_PCI_MEM_ADRS	0x60000000
#define CPU_PCI_MEM_SIZE	0x20000000
#define CPU_PCI_MEM_MASK	0xE0000000

/* PCI view of PCI space for PCI devices */

#define PCI_IO_ADRS             0x10000000      /* base of PCI I/O address */
#define PCI2DRAM_BASE_ADRS      0x60000000      /* memory seen from PCI bus */

/* PCI view of PCI memory space for PCI memory devices */

#define PCI_MEM_ADRS		0x60000000	/* base of PCI memory space */

/* PCI address to CPU address offset */

#define PCI2CPU_IO_OFFSET	(CPU_PCI_IO_ADRS - PCI_IO_ADRS)
#define PCI2CPU_MEM_OFFSET	(CPU_PCI_MEM_ADRS - PCI_MEM_ADRS)

/* PCI bus resources */

#define PCI_IO_SIZE		0x00004000	/* PCI I/O slot size */
#define PCI_MEM_SIZE		0x00004000	/* PCI memory slot size */

#define PCI_MEM_ADR0            PCI_MEM_ADRS + SZ_64M  
#define PCI_IO_ADR0             PCI_IO_ADRS     /* I/O base for CSR 32Bytes */
#define PCI_IO_SIZE0            PCI_IO_SIZE     /* I/O size for CSR */
#define PCI_INT_LVL0            INT_LVL_EXTI0S	/* Interrupt level */
#define PCI_INT_VEC0            INT_VEC_EXTI0S	/* Interrupt vector */

#define PCI_MEM_ADR1            PCI_MEM_ADR0 + PCI_MEM_SIZE
#define PCI_IO_ADR1             PCI_IO_ADR0 + PCI_IO_SIZE
#define PCI_IO_SIZE1            PCI_IO_SIZE
#define PCI_INT_LVL1            INT_LVL_EXTI0S
#define PCI_INT_VEC1            INT_VEC_EXTI0S

#define PCI_MEM_ADR2            PCI_MEM_ADR1 + PCI_MEM_SIZE
#define PCI_IO_ADR2             PCI_IO_ADR1 + PCI_IO_SIZE
#define PCI_IO_SIZE2            PCI_IO_SIZE
#define PCI_INT_LVL2            INT_LVL_EXTI0S
#define PCI_INT_VEC2            INT_VEC_EXTI0S


/* PCI memory base address register configuration mode */

#define FORCE		0x00	/* overwrite membase address register */
#define AUTO		0x01	/* read membase address register */


/*
 * Max number of END devices we support
 */

#define KS8695P_MAX_END_DEVS 5



#undef  KS8695P_ENET_FIXED_BUF_ADRS	/* do not use fixed address bufs */
#define KS8695P_ENET_CHECK_BUFFERS	/* check cacheDmaMalloc() addresses */


#ifdef  KS8695P_ENET_FIXED_BUF_ADRS

/*
 * Provide definitions for the buffer address for the three possible PCI cards.
 * The SDRAM alias address should be available on all boards.
 */

#define KS8695P_ENET_PRIMARY_BUF_ADRS KS8695P_SDRAM_ALIAS_BASE

/* next two areas require a later board, or the FPGAs to have been upgraded */

#define KS8695P_ENET_SECONDARY_BUF_ADRS KS8695P_MBRD_SSRAM_BASE
#define KS8695P_ENET_TERTIARY_BUF_ADRS (KS8695P_MBRD_SSRAM_BASE + 0x40000)
#endif /* KS8695P_ENET_FIXED_BUF_ADRS */


#define KS8695P_DEC_BUF_SIZE	0x30000

/*
 * Assuming we are on a 720T, and three drivers are being started, the
 * smallest slot is 256 kbytes, so reduce memory usage to fit into 256 Kbyte