sdram_test.c

ADI公司TIGERSHARC的访问SDRAM的程序

//*********************************************************
//
//  sdram_test.c : Test of Tiger Sharc SDRAM interface
//
//  PROVIDED BY:
//  ------------
//  BittWare Research Systems, Inc.
//  33 North Main Street
//  Concord, NH  03301
//  Ph: 603-226-0404
//  Fax: [phone]
//  WWW: www.bittware.com
//  E-mail: [e-mail]
//
//  Copyright 2001, BittWare, Inc.
//
//  The user is hereby granted a non-exclusive license to use and or 
//  modify this software provided that it runs on BittWare hardware.  
//  Usage of this software on non-BittWare hardware without the express 
//  written permission of BittWare is strictly prohibited.
//
//
//    Ver.  Dates     Author  Changes                                
//    ----  --------  ------  -----------------------------
//    1.0   02/01/02   rpc     Create
//
//*********************************************************

#include <sysreg.h>
#include <builtins.h>
#include <signal.h>
#include "memory_tests.h"

#define	SDRAM_BASE_ADDRESS			0x4000000
#define SDRAM_SIZE					0x4000000  // 128M SODIMM
#define NUMBER_OF_TEST_LOOPS_TO_RUN	10

  	
// Globals for test results and status
int total_error_count;
int errors[11];
int current_num_loops;
int done;

// Globals for test parameters
// Use globals for the test start address, length, and number of loops so that we can change these with the debugger/emulator
// to test internal, external, or MMS as desired
// Init them to the defs from above
int	*sdram_base = (int *) SDRAM_BASE_ADDRESS;
int	sdram_size = SDRAM_SIZE;
int num_loops_to_run = NUMBER_OF_TEST_LOOPS_TO_RUN;


void main(void) 
{
    int i;
	int errs;

	// Set up SYSCON and the SDRAM config
//	__builtin_sysreg_write(__SYSCON, 0x003a5000); // 64-bit external bus for memory (MBUB)
//	__builtin_sysreg_write(__SDRCON, 0x3723); //0x00003703); // SDRAM enabled, CAS LATENCY = two, Pipe Depth = 0, Page Boundry = 256,
												  // Refresh Rate = 600, PRC to RAS DELAY = 2, RAS TO PRC DELAY = 5,
												  // INIT Sequence = MRS then REFRESH (MBUB)

	// Run the memory tests
	total_error_count = 0;
	current_num_loops = 0;
	done = 0;


	while (current_num_loops < num_loops_to_run)
	{
	// Verify even and odd bits in each location
		errs = static_pattern_test(sdram_base, sdram_size, 0xaaaaaaaa);
		errors[0] +=errs;
		total_error_count += errs;
		
		errs = static_pattern_test(sdram_base, sdram_size, 0x55555555);
		errors[1] += errs;
		total_error_count += errs;

	// Set all bits and clear all bits
        errs = static_pattern_test(sdram_base, sdram_size, 0xffffffff);
		errors[2] += errs;
		total_error_count += errs;

		errs = static_pattern_test(sdram_base, sdram_size, 0x00000000);
		errors[3] += errs;
		total_error_count += errs;

	// Run a counting pattern through
	    errs = incrementing_pattern_test(sdram_base, sdram_size, 0, 1);
		errors[4] += errs;
		total_error_count += errs;
	
	// Verify alternating bits in memory and on the bus for each subsequent location
	    errs = alternating_pattern_test(sdram_base, sdram_size, 0x55555555, 0xaaaaaaaa);
		errors[5] += errs;
		total_error_count += errs;

	// Run a decrementing pattern
	    errs = incrementing_pattern_test(sdram_base, sdram_size, 0xffffffff, -1);
		errors[6] += errs;
		total_error_count += errs;
	
	// Walk a zero through a location (tests independence of data lines)
	    errs = walking_zero_test(sdram_base, 0, 31);
		errors[7] += errs;
		total_error_count += errs;
	
	// Walk a one through a location (test independence of data lines)
	    errs = walking_one_test(sdram_base, 0, 31);
		errors[8] += errs;
		total_error_count += errs;
	
	// Write the address as the data
	    errs = data_address_test(sdram_base, sdram_size);
		errors[9] += errs;
		total_error_count += errs;

	// Write the complement of the address as the data
	    errs = data_address_complement_test(sdram_base, sdram_size);
		errors[10] += errs;
		total_error_count += errs;

		current_num_loops++;
	}

	done = 1;

	while(1)
	{
	    i = i-i;
	}
}


//
// End of file: sdram_test.c
//