opcodes.c

这是模拟器源代码

//---------------------------------------------------------------

// ADC

int ins_adc(void)
{
	DEST_REG = BASE_REG + DP_REG_OPERAND(IMM_SHIFT) + CFLAG;
	
	advance_instruction_pipe(); return 1;
}

int ins_adc_reg (void)
{
	DEST_REG = BASE_REG + DP_REG_OPERAND(REG_SHIFT) + CFLAG;
	
	advance_instruction_pipe(); return 2;
}

int ins_adc_imm(void)
{
	DEST_REG = BASE_REG + DP_IMM_OPERAND() + CFLAG;
	
	advance_instruction_pipe(); return 1;
}

int ins_adcs(void)
{
	u32 op1 = BASE_REG;
	u32 op2 = DP_REG_OPERAND(IMM_SHIFT);
	DEST_REG = op1 + op2 + CFLAG;
	SET_ADD_FLAGS(op1, op2, DEST_REG);
	
	advance_instruction_pipe(); return 1;
}

int ins_adcs_reg (void)
{
	u32 op1 = BASE_REG;
	u32 op2 = DP_REG_OPERAND(REG_SHIFT);
	DEST_REG = op1 + op2 + CFLAG;
	SET_ADD_FLAGS(op1, op2, DEST_REG);
	
	advance_instruction_pipe(); return 2;
}

int ins_adcs_imm(void)
{
	u32 op1 = BASE_REG;
	u32 op2 = DP_IMM_OPERAND();
	DEST_REG = op1 + op2 + CFLAG;
	SET_ADD_FLAGS(op1, op2, DEST_REG);
	
	advance_instruction_pipe(); return 1;
}

//---------------------------------------------------------------

// SBC

int ins_sbc(void)
{
	DEST_REG = BASE_REG - DP_REG_OPERAND(IMM_SHIFT) - !CFLAG;
	
	advance_instruction_pipe(); return 1;
}

int ins_sbc_reg (void)
{
	DEST_REG = BASE_REG - DP_REG_OPERAND(REG_SHIFT) - !CFLAG;
	
	advance_instruction_pipe(); return 2;
}

int ins_sbc_imm(void)
{
	DEST_REG = BASE_REG + DP_IMM_OPERAND() - !CFLAG;
	
	advance_instruction_pipe(); return 1;
}

int ins_sbcs(void)
{
	u32 op1 = BASE_REG;
	u32 op2 = DP_REG_OPERAND(IMM_SHIFT);
	DEST_REG = op1 - op2 - !CFLAG;
	SET_SUB_FLAGS(op1, op2, DEST_REG);
	
	advance_instruction_pipe(); return 1;
}

int ins_sbcs_reg (void)
{
	u32 op1 = BASE_REG;
	u32 op2 = DP_REG_OPERAND(REG_SHIFT);
	DEST_REG = op1 - op2 - !CFLAG;
	SET_SUB_FLAGS(op1, op2, DEST_REG);
	
	advance_instruction_pipe(); return 2;
}

int ins_sbcs_imm(void)
{
	u32 op1 = BASE_REG;
	u32 op2 = DP_IMM_OPERAND();
	DEST_REG = op1 - op2 - !CFLAG;
	SET_SUB_FLAGS(op1, op2, DEST_REG);
	
	advance_instruction_pipe(); return 1;
}

//---------------------------------------------------------------

// RSC

int ins_rsc(void)	
{
	DEST_REG = DP_REG_OPERAND(IMM_SHIFT) - BASE_REG - !CFLAG;
	
	advance_instruction_pipe(); return 1;
}

int ins_rsc_reg (void)
{
	DEST_REG = DP_REG_OPERAND(REG_SHIFT) - BASE_REG - !CFLAG;
	
	advance_instruction_pipe(); return 2;
}

int ins_rsc_imm(void)
{
	DEST_REG = DP_IMM_OPERAND() - BASE_REG - !CFLAG;
	
	advance_instruction_pipe(); return 1;
}

int ins_rscs(void)
{
	u32 op1 = BASE_REG;
	u32 op2 = DP_REG_OPERAND(IMM_SHIFT);
	DEST_REG = op2 - op1 - !CFLAG;
	SET_SUB_FLAGS(op2, op1, DEST_REG);

	advance_instruction_pipe(); return 1;
}

int ins_rscs_reg (void)
{
	u32 op1 = BASE_REG;
	u32 op2 = DP_REG_OPERAND(REG_SHIFT);
	DEST_REG = op2 - op1 - !CFLAG;
	SET_SUB_FLAGS(op2, op1, DEST_REG);
	advance_instruction_pipe(); return 2;
}

int ins_rscs_imm(void)
{
	u32 op1 = BASE_REG;
	u32 op2 = DP_IMM_OPERAND();
	DEST_REG = op2 - op1 - !CFLAG;
	SET_SUB_FLAGS(op2, op1, DEST_REG);

	advance_instruction_pipe(); return 1;
}

//---------------------------------------------------------------------

// TST

int ins_tst(void)
{
	u32 temp = BASE_REG & DP_REG_OPERAND_C(IMM_SHIFT);
	SET_DP_LOG_FLAGS (temp);
	advance_instruction_pipe();	return 1;
}

int ins_tst_reg (void)
{
	u32 temp = BASE_REG & DP_REG_OPERAND_C(REG_SHIFT);
	SET_DP_LOG_FLAGS (temp);
	advance_instruction_pipe();
	return 2;
}

int ins_tst_imm(void)
{
	u32 temp = BASE_REG & DP_IMM_OPERAND();
	SET_DP_LOG_FLAGS (temp);
	advance_instruction_pipe(); return 1;
}

//---------------------------------------------------------------------

// TEQ

int ins_teq(void)
{
	u32 temp = BASE_REG ^ DP_REG_OPERAND_C(IMM_SHIFT);
	SET_DP_LOG_FLAGS (temp);
	advance_instruction_pipe(); return 1;
}

int ins_teq_reg (void)
{
	u32 temp = BASE_REG ^ DP_REG_OPERAND_C(REG_SHIFT);
	SET_DP_LOG_FLAGS (temp);
	advance_instruction_pipe(); return 2;
}

int ins_teq_imm(void)
{
	u32 temp = BASE_REG ^ DP_IMM_OPERAND();
	SET_DP_LOG_FLAGS (temp);
	advance_instruction_pipe(); return 1;
}

//---------------------------------------------------------------------

// CMP

int ins_cmp(void)
{
	u32 op1 = BASE_REG;
	u32 op2 = DP_REG_OPERAND(IMM_SHIFT);
	SET_SUB_FLAGS (op1, op2, op1 - op2);
	advance_instruction_pipe(); return 1;
}

int ins_cmp_reg(void)
{
	u32 op1 = BASE_REG;
	u32 op2 = DP_REG_OPERAND(REG_SHIFT);
	SET_SUB_FLAGS (op1, op2, op1 - op2);
	advance_instruction_pipe(); return 2;
}

int ins_cmp_imm(void)	
{
	u32 op1 = BASE_REG;
	u32 op2 = DP_IMM_OPERAND();
	SET_SUB_FLAGS(op1, op2, op1 - op2);
	advance_instruction_pipe(); return 1;
}

//---------------------------------------------------------------------

// CMN

int ins_cmn(void)
{
	u32 op1 = BASE_REG;
	u32 op2 = DP_REG_OPERAND(IMM_SHIFT);
	SET_ADD_FLAGS (op1, op2, op1 + op2);
	advance_instruction_pipe(); return 1;
}

int ins_cmn_reg (void)
{
	u32 op1 = BASE_REG;
	u32 op2 = DP_REG_OPERAND(REG_SHIFT);
	SET_ADD_FLAGS (op1, op2, op1 + op2);
	advance_instruction_pipe(); return 2;
}

int ins_cmn_imm(void)
{
	u32 op1 = BASE_REG;
	u32 op2 = DP_IMM_OPERAND();
	SET_ADD_FLAGS(op1, op2, op1 + op2);
	advance_instruction_pipe(); return 1;
}

//---------------------------------------------------------------------

// ORR

int ins_orr(void)
{
	DEST_REG = BASE_REG | DP_REG_OPERAND(IMM_SHIFT);
	advance_instruction_pipe(); return 1;
}

int ins_orr_reg (void)
{
	DEST_REG = BASE_REG | DP_REG_OPERAND(REG_SHIFT);
	advance_instruction_pipe(); return 2;
}

int ins_orr_imm(void)
{
	DEST_REG = BASE_REG | DP_IMM_OPERAND();
	advance_instruction_pipe(); return 1;
}

int ins_orrs(void)
{	
	DEST_REG = BASE_REG | DP_REG_OPERAND_C(IMM_SHIFT);
	SET_DP_LOG_FLAGS(DEST_REG);
	advance_instruction_pipe();	return 1;
}

int ins_orrs_reg (void)
{
	DEST_REG = BASE_REG | DP_REG_OPERAND_C(REG_SHIFT);
	SET_DP_LOG_FLAGS(DEST_REG);
	advance_instruction_pipe(); return 2;
}

int ins_orrs_imm(void)
{
	DEST_REG = BASE_REG | DP_IMM_OPERAND();
	SET_DP_LOG_FLAGS(DEST_REG);
	advance_instruction_pipe(); return 1;
}

//---------------------------------------------------------------------

// MOV

int ins_mov(void)
{
	DEST_REG = DP_REG_OPERAND(IMM_SHIFT);
	if (((OPCODE>>12)&0xF)==0xF) { fill_instruction_pipe(); return 3; }
	advance_instruction_pipe(); return 1;
}

int ins_mov_reg (void)
{
	DEST_REG = DP_REG_OPERAND(REG_SHIFT);
	if (((OPCODE>>12)&0xF)==0xF) { fill_instruction_pipe(); return 4; }
	advance_instruction_pipe(); return 2;
}

int ins_mov_imm(void)
{
	DEST_REG = DP_IMM_OPERAND();
	if (((OPCODE>>12)&0xF)==0xF) { fill_instruction_pipe();	return 4; }
	advance_instruction_pipe(); return 1;
}

int ins_movs(void)
{
	DEST_REG = DP_REG_OPERAND_C(IMM_SHIFT);
	SET_DP_LOG_FLAGS(DEST_REG);
	if (((OPCODE>>12)&0xF)==0xF) { fill_instruction_pipe(); return 3; }
	advance_instruction_pipe();	return 1;	
}

int ins_movs_reg (void)
{
	DEST_REG = DP_REG_OPERAND_C(REG_SHIFT);
	SET_DP_LOG_FLAGS(DEST_REG);
	if (((OPCODE>>12)&0xF)==0xF) { fill_instruction_pipe();	return 4; }
	advance_instruction_pipe(); return 2;
}

int ins_movs_imm(void)
{
	DEST_REG = DP_IMM_OPERAND();
	SET_DP_LOG_FLAGS(DEST_REG);
	if (((OPCODE>>12)&0xF)==0xF) { fill_instruction_pipe();	return 4; }
	advance_instruction_pipe(); return 1;
}

//---------------------------------------------------------------------

// BIC

int ins_bic(void)
{
	DEST_REG = BASE_REG & (~DP_REG_OPERAND(IMM_SHIFT));
	advance_instruction_pipe();	return 1;
}

int ins_bic_reg (void)
{
	DEST_REG = BASE_REG & (~DP_REG_OPERAND(REG_SHIFT));
	advance_instruction_pipe(); return 2;
}

int ins_bic_imm(void)
{
	DEST_REG = BASE_REG & (~DP_IMM_OPERAND());
	advance_instruction_pipe(); return 1;
}

int ins_bics(void)
{
	DEST_REG = BASE_REG & (~DP_REG_OPERAND_C(IMM_SHIFT));
	SET_DP_LOG_FLAGS(DEST_REG);
	advance_instruction_pipe(); return 1;
}

int ins_bics_reg (void)
{
	DEST_REG = BASE_REG & (~DP_REG_OPERAND_C(REG_SHIFT));
	SET_DP_LOG_FLAGS(DEST_REG);
	advance_instruction_pipe(); return 2;
}

int ins_bics_imm(void)	
{
	DEST_REG = BASE_REG & (~DP_IMM_OPERAND());
	SET_DP_LOG_FLAGS(DEST_REG);
	advance_instruction_pipe(); return 1;
}

//---------------------------------------------------------------------

// MVN

int ins_mvn(void)
{
	DEST_REG = (~DP_REG_OPERAND(IMM_SHIFT));
	advance_instruction_pipe(); return 1;
}

int ins_mvn_reg (void)
{
	DEST_REG = (~DP_REG_OPERAND(REG_SHIFT));
	advance_instruction_pipe();	return 2;
}

int ins_mvn_imm(void)	
{	
	DEST_REG = ~DP_IMM_OPERAND();
	advance_instruction_pipe(); return 1;
}

int ins_mvns(void)
{
	DEST_REG = (~DP_REG_OPERAND_C(IMM_SHIFT));
	SET_DP_LOG_FLAGS(DEST_REG);
	advance_instruction_pipe(); return 1;
}

int ins_mvns_reg (void)
{
	DEST_REG = (~DP_REG_OPERAND_C(REG_SHIFT));
	SET_DP_LOG_FLAGS(DEST_REG);
	advance_instruction_pipe(); return 2;
}

int ins_mvns_imm(void)
{
	DEST_REG = ~DP_IMM_OPERAND();
	SET_DP_LOG_FLAGS(DEST_REG);
	advance_instruction_pipe();	return 1;
}

//---------------------------------------------------------------------

// MRS-MSR

int ins_mrs_cpsr(void)
{	
	DEST_REG = CPSR;
	advance_instruction_pipe();	return 1;
}

int ins_msr_cpsr(void)
{
	CPSR = arm->gp_reg [(OPCODE&0xF)];
	advance_instruction_pipe(); return 1;
}
int ins_mrs_spsr(void)	
{
	DEST_REG = arm->spsr [CPSR&0x1F];
	advance_instruction_pipe(); return 1;
}

int ins_msr_spsr(void)
{
	arm->spsr [CPSR&0x1F] = arm->gp_reg [(OPCODE&0xF)];
	advance_instruction_pipe(); return 1;
}

int ins_msr_cpsr_imm(void)
{
	CPSR = DP_IMM_OPERAND() & 0xF00000FF;
	advance_instruction_pipe(); return 1;
}

int ins_msr_spsr_imm(void)	
{
	arm->spsr [CPSR&0x1F] = DP_IMM_OPERAND() & 0xF00000FF;
	advance_instruction_pipe(); return 1;
}

//---------------------------------------------------------------------

/*---------------------------------------------------------------------
					DATA TRANSFER
----------------------------------------------------------------------*/

int ins_ldr_pre_up (void)
{
	u32 offset = DP_REG_OPERAND(IMM_SHIFT);
	
	DEST_REG = read_word (BASE_REG + offset);
	if (OPCODE&0x200000) BASE_REG += offset;	
	if (((OPCODE>>12)&0xF)==15) fill_instruction_pipe(); else advance_instruction_pipe();
	return 1;
}

int ins_ldr_pre_down (void)
{
	u32 offset = DP_REG_OPERAND(IMM_SHIFT);

	DEST_REG = read_word (BASE_REG - offset);
	if (OPCODE&0x200000) BASE_REG -= offset;
	if (((OPCODE>>12)&0xF)==15) fill_instruction_pipe(); else advance_instruction_pipe();
	return 1;
}

int ins_ldr_post_up (void)
{
	u32 offset = DP_REG_OPERAND(IMM_SHIFT);
	DEST_REG = read_word (BASE_REG);
	BASE_REG += offset;		
	if (((OPCODE>>12)&0xF)==15) fill_instruction_pipe(); else advance_instruction_pipe();
	return 1;
}

int ins_ldr_post_down (void)
{
	u32 offset = DP_REG_OPERAND(IMM_SHIFT);
	DEST_REG = read_word (BASE_REG);
	BASE_REG -= offset;		
	if (((OPCODE>>12)&0xF)==15) fill_instruction_pipe(); else advance_instruction_pipe();
	return 1;
}

int ins_ldr_imm_pre_up (void)
{
	u32 offset = (OPCODE&0xFFF);
	DEST_REG = read_word (BASE_REG + offset);
	if (OPCODE&0x200000) BASE_REG += offset;	
	if (((OPCODE>>12)&0xF)==15) fill_instruction_pipe(); else advance_instruction_pipe();
	return 3;
}

int ins_ldr_imm_pre_down (void)
{
	u32 offset = (OPCODE&0xFFF);
	DEST_REG = read_word (BASE_REG - offset);
	if (OPCODE&0x200000) BASE_REG -= offset;
	if (((OPCODE>>12)&0xF)==15) fill_instruction_pipe(); else advance_instruction_pipe();
	return 3;
}

int ins_ldr_imm_post_up (void)
{
	u32 offset = (OPCODE&0xFFF);
	DEST_REG = read_word (BASE_REG);
	BASE_REG += offset;
	if (((OPCODE>>12)&0xF)==15) fill_instruction_pipe(); else advance_instruction_pipe();
	return 3;
}

int ins_ldr_imm_post_down (void)
{
	u32 offset = (OPCODE&0xFFF);
	DEST_REG = read_word (BASE_REG);
	BASE_REG -= offset;
	if (((OPCODE>>12)&0xF)==15) fill_instruction_pipe(); else advance_instruction_pipe();
	return 3;
}

//----------------------------------------------------------------

int ins_ldrb_pre_up (void)
{
	u32 offset = DP_REG_OPERAND(IMM_SHIFT);

	DEST_REG = (u32)read_byte (BASE_REG + offset);
	if (OPCODE&0x200000) BASE_REG += offset;	
	advance_instruction_pipe(); return 1;
}

int ins_ldrb_pre_down (void)
{
	u32 offset = DP_REG_OPERAND(IMM_SHIFT);

	DEST_REG = (u32)read_byte (BASE_REG - offset);
	if (OPCODE&0x200000) BASE_REG -= offset;	
	advance_instruction_pipe(); return 1;
}

int ins_ldrb_post_up (void)
{
	u32 offset = DP_REG_OPERAND(IMM_SHIFT);
	DEST_REG = (u32)read_byte (BASE_REG);
	BASE_REG += offset;
	advance_instruction_pipe(); return 1;
}

int ins_ldrb_post_down (void)