myinit.s

一个运行在PIC上的WEB服务器

	.include "memory.s"
	.include "snds.s"

	.text

# --- Define entry point
        .global  __main  /* defined to ensure that C runtime system*/
__main:                  /*is not linked in*/

# --- Setup interrupt / exception vectors
# If the ROM is at address 0 this is just a sequence of branches
        B       Reset_Handler
        B       Undefined_Handler
        B       SWI_Handler
        B       Prefetch_Handler
        B       Abort_Handler
        NOP     	 	/*Reserved vector*/
        B       IRQ_Handler
        B       FIQ_Handler


#==========================================================
# The Default Exception Handler Vector Entry Pointer Setup
#==========================================================
FIQ_Handler:
	SUB	sp, sp, #4
	STMFD	sp!, {r0}
	LDR	r0, =HandleFiq
	LDR	r0, [r0]
	STR	r0, [sp, #4]
	LDMFD	sp!, {r0, pc}

IRQ_Handler:
	SUB	sp, sp, #4
	STMFD	sp!, {r0}
	LDR	r0, =HandleIrq
	LDR	r0, [r0]
	STR	r0, [sp, #4]
	LDMFD	sp!, {r0, pc}

Prefetch_Handler:
	SUBS PC, LR, #4
#	SUB	sp, sp, #4
#	STMFD	sp!, {r0}
#	LDR	r0, =HandlePrefetch
#	LDR	r0, [r0]
#	STR	r0, [sp, #4]
#	LDMFD	sp!, {r0, pc}

Abort_Handler:
	SUBS PC, LR, #8
#	SUB	sp, sp, #4
#	STMFD	sp!, {r0}
#	LDR	r0, =HandleAbort
#	LDR	r0, [r0]
#	STR	r0, [sp, #4]
#	LDMFD	sp!, {r0, pc}

Undefined_Handler:
	mov pc, lr
#	SUB	sp, sp, #4
#	STMFD	sp!, {r0}
#	LDR	r0, =HandleUndef
#	LDR	r0, [r0]
#	STR	r0, [sp, #4]
#	LDMFD	sp!, {r0, pc}

SWI_Handler:
	mov pc, lr
#	SUB	sp, sp, #4
#	STMFD	sp!, {r0}
#	LDR	r0, =HandleSwi
#	LDR	r0, [r0]
#	STR	r0, [sp, #4]
#	LDMFD	sp!, {r0, pc}



	.text 
Main:

#==========================================================
# The Reset Entry Point
#==========================================================
          .global	Reset_Handler
Reset_Handler:                           /* Reset Entry Point */

	LDR	r1, =IntMask
	LDR	r0, =0xFFFFFFFF
	STR	r0, [r1]

	#=====================================
	# Initialise STACK 
	#=====================================
INITIALIZE_STACK:
	MRS	r0, cpsr
	BIC	r0, r0, #LOCKOUT | MODE_MASK
	ORR	r2, r0, #USR_MODE	

	ORR	r1, r0, #LOCKOUT | FIQ_MODE
	MSR	cpsr_cf, r1
	MSR	spsr_cf, r2 
	LDR	sp, =FIQ_STACK

	ORR	r1, r0, #LOCKOUT | IRQ_MODE
	MSR	cpsr_cf, r1
	MSR	spsr_cf, r2
	LDR	sp, =IRQ_STACK

	ORR	r1, r0, #LOCKOUT | ABT_MODE
	MSR	cpsr_cf, r1
	MSR	spsr_cf, r2
	LDR	sp, =ABT_STACK

	ORR	r1, r0, #LOCKOUT | UDF_MODE
	MSR	cpsr_cf, r1
	MSR	spsr_cf, r2
	LDR	sp, =UDF_STACK

	ORR	r1, r0, #LOCKOUT | SUP_MODE
	MSR	cpsr_cf, r1
	MSR	spsr_cf, r2
	LDR	sp, =SUP_STACK   /*Change CPSR to SVC mode*/

	#==================================================
	# Special Register Configuration for SYNC DRAM
	#==================================================
SYNC_DRAM_CONFIGURATION:
	LDR	r0, =0x3FF0000		 
	LDR	r1, =0x83FFFF92   	/*SetValue = 0x83FFFF91*/
#	LDR	r1, =0x83FFFF20   	/*SetValue = 0x83FFFF91*/
	STR	r1, [r0]	  	/*Cache,WB disable*/
                           		/*Start_addr = 0x3FF00000*/

	#ROM and RAM Configuration(Multiple Load and Store)
    #ADRL    r0, SystemInitDataSDRAM
    LDR    r0, =SystemInitDataSDRAM
	LDMIA   r0, {r1-r12}
	LDR	r0, =0x3FF0000 + 0x3010 /*ROMCntr Offset : 0x3010*/
	STMIA   r0, {r1-r12}

	#=============================
	# Exception Vector Table Setup 
	#=============================
EXCEPTION_VECTOR_TABLE_SETUP:
	LDR	r0, =HandleReset	/*Exception Vector Table Memory Loc.*/
	LDR	r1, =ExceptionHandlerTable /*Exception Handler Assign*/
	MOV	r2, #8			/*Number of Exception is 8*/
ExceptLoop:
	LDR	r3, [r1], #4
	STR	r3, [r0], #4
	SUBS	r2, r2, #1		/*Down Count*/
	BNE	ExceptLoop

	#=====================================
	# Initialise memory required by C code
	#=====================================
	
	
	
	#====================================================
	# Now change to user mode and set up user mode stack.
	#====================================================
    /*
    MRS     r0, cpsr
	BIC	r0, r0, #LOCKOUT | MODE_MASK
	ORR	r1, r0, #USR_MODE
	MSR	cpsr_cf, r0
	LDR	sp, =USR_STACK
	*/
	
	MSR	cpsr_cf, #0x13		/* enable irq and fiq */
	
	
       /* Call C_Entry application routine with a pointer to the first */
       /* available memory address after ther compiler's global data   */
       /* This memory may be used by the application.                  */
	#===========================
	# Now we enter the C Program
	#===========================


        .extern  C_Entry
        BL      C_Entry

#===========================================
# Exception Vector Function Definition
# Consist of function Call from C-Program.
#===========================================
SystemUndefinedHandler:
	.extern	ISR_UndefHandler
	STMFD	sp!, {r0-r12}
	B	ISR_UndefHandler
	LDMFD	sp!, {r0-r12, pc}^

SystemSwiHandler:
	STMFD	sp!, {r0-r12,lr}
	LDR	r0, [lr, #-4]
	BIC	r0, r0, #0xff000000
	CMP	r0, #0xff
	BEQ	MakeSVC
	LDMFD	sp!, {r0-r12, pc}^
MakeSVC:
	MRS	r1, spsr
	BIC	r1, r1, #MODE_MASK
	ORR	r2, r1, #SUP_MODE
	MSR	spsr_cf, r2
	LDMFD	sp!, {r0-r12, pc}^

SystemPrefetchHandler:
	.extern	ISR_PrefetchHandler
	STMFD	sp!, {r0-r12, lr}
	B	ISR_PrefetchHandler
	LDMFD	sp!, {r0-r12, lr}
	#ADD	sp, sp, #4
	SUBS	pc, lr, #4

SystemAbortHandler:
	.extern	ISR_AbortHandler
	STMFD	sp!, {r0-r12, lr}
	B	ISR_AbortHandler
	LDMFD	sp!, {r0-r12, lr}
	#ADD	sp, sp, #4
	SUBS	pc, lr, #8

SystemReserv:
	SUBS	pc, lr, #4

SystemIrqHandler:
	.extern	ISR_IrqHandler
	STMFD	sp!, {r0-r12, lr}
	BL	ISR_IrqHandler
	LDMFD	sp!, {r0-r12, lr}
	SUBS	pc, lr, #4

SystemFiqHandler:
	.extern	ISR_FiqHandler
	STMFD	sp!, {r0-r7, lr}
	BL	ISR_FiqHandler
	LDMFD	sp!, {r0-r7, lr}
	SUBS	pc, lr, #4


	.data

#======================================================
# DRAM System Initialize Data KS32C50100
#======================================================
SystemInitData:
	.long rEXTDBWTH	/*DRAM1(Half), ROM5(Byte), ROM1(Half), else 32bit*/
	.long rROMCON0	/*0x0000000 ~ 0x01FFFFF, ROM0,4Mbit,2cycle*/
	.long rROMCON1	
   	.long rROMCON2	/*0x0400000 ~ 0x05FFFFF, ROM2*/
	.long rROMCON3	/*0x0600000 ~ 0x07FFFFF, ROM3*/
	.long rROMCON4	/*0x0800000 ~ 0x09FFFFF, ROM4*/
	.long rROMCON5	
	.long rDRAMCON0   /*0x1000000 ~ 0x13FFFFF, DRAM0 4M,*/
	.long rDRAMCON1	/*0x1400000 ~ 0x17FFFFF, DRAM1 4M,*/
	.long rDRAMCON2	/*0x1800000 ~ 0x1EFFFFF, DRAM2 16M*/
	.long rDRAMCON3	/*0x1C00000 ~ 0x1FFFFFF*/
	.long rREFEXTCON  /*External I/O, Refresh*/

#======================================================
# SDRAM System Initialize Data	(KS32C50100 only)
#======================================================
SystemInitDataSDRAM:
	.long 0x01503000	/*DRAM1(Half), ROM5(Byte), ROM1(Half), else 32bit*/
	.long 0x0	/*0x0000000 ~ 0x01FFFFF, ROM0,4Mbit,2cycle*/
	.long 0x00000060
  	.long 0x00000060	/*0x0400000 ~ 0x05FFFFF, ROM2*/
	.long 0x0	/*0x0600000 ~ 0x07FFFFF, ROM3*/
	.long 0x0	/*0x0800000 ~ 0x09FFFFF, ROM4*/
	.long 0x00000060
	.long 0x10000301  /*0x1000000 ~ 0x13FFFFF, DRAM0 4M,*/
	.long 0x00000000	/*0x1400000 ~ 0x17FFFFF, DRAM1 4M,*/
	.long 0x00000000	/*0x1800000 ~ 0x1EFFFFF, DRAM2 16M*/
	.long 0x00000000	/* 0x1C00000 ~ 0x1FFFFFF*/
	.long 0x9c298360 /* External I/O, Refresh	*/
	

#===========================================
# Exception Handler Vector Table Entry Point
#===========================================
ExceptionHandlerTable:
	.long	UserCodeArea
	.long	SystemUndefinedHandler
	.long	SystemSwiHandler
	.long	SystemPrefetchHandler
	.long	SystemAbortHandler
	.long	SystemReserv
	.long	SystemIrqHandler
#	.extern OSTickISR
#	.long	OSTickISR
	.long	SystemFiqHandler



	.ALIGN
/***************************************************/
	.bss
/***************************************************/
                .space       SUP_STACK_SIZE
SUP_STACK:
                .space       UDF_STACK_SIZE
UDF_STACK:
                .space       ABT_STACK_SIZE
ABT_STACK:
                .space       IRQ_STACK_SIZE
IRQ_STACK:
                .space       FIQ_STACK_SIZE
FIQ_STACK:
                .space       USR_STACK_SIZE
USR_STACK:

/***************************************************/
	.end