bsp.h

dsp开发平台的show文件

         .mmregs
*––––––––––––––––––––– TIMER2 Registers ––––––––––––––––––
TIM1 .set 0030h ; Timer1
PRD1 .set 0031h ; Timer1 Period Reg
TCR1 .set 0032h ; Timer1 Ctrl Reg
*==============McBSP0 Registers============*    
McBSP0_DRR2     .set 0020h     ; McBSP0 Data Rx Reg2
McBSP0_DRR1     .set 0021h     ; McBSP0 Data Rx Reg1
McBSP0_DXR2     .set 0022h     ; McBSP0 Data Tx Reg2
McBSP0_DXR1     .set 0023h     ; McBSP0 Data Tx Reg1
McBSP0_SPSA     .set 0038h     ; McBSP0 Sub Bank Addr Reg
McBSP0_SPSD     .set 0039h     ; McBSP0 Sub Bank Data Reg

*==============McBSP1 Registers============*
McBSP1_DRR2     .set 0040h     ; McBSP1 Data Rx Reg2
McBSP1_DRR1     .set 0041h     ; McBSP1 Data Rx Reg1
McBSP1_DXR2     .set 0042h     ; McBSP1 Data Tx Reg2
McBSP1_DXR1     .set 0043h     ; McBSP1 Data Tx Reg1
McBSP1_SPSA     .set 0048h     ; McBSP1 Sub Bank Addr Reg
McBSP1_SPSD     .set 0049h     ; McBSP1 Sub Bank Data Reg

*==============McBSP2 Registers============*
McBSP2_DRR2     .set 0030h     ; McBSP2 Data Rx Reg2
McBSP2_DRR1     .set 0031h     ; McBSP2 Data Rx Reg1
McBSP2_DXR2     .set 0032h     ; McBSP2 Data Tx Reg2
McBSP2_DXR1     .set 0033h     ; McBSP2 Data Tx Reg1
McBSP2_SPSA     .set 0034h     ; McBSP2 Sub Bank Addr Reg
McBSP2_SPSD     .set 0035h     ; McBSP2 Sub Bank Data Reg

*==== McBSP0 & McBSP1 & McBSP2 Sub-Bank Addressed Registers====*

SPCR1           .set 0000h     ; McBSP Ser Port Ctrl Reg1
SPCR2           .set 0001h     ; McBSP Ser Port Ctrl Reg2
RCR1            .set 0002h     ; McBSP Rx Ctrl Reg1
RCR2            .set 0003h     ; McBSP Rx Ctrl Reg2
XCR1            .set 0004h     ; McBSP Tx Ctrl Reg1
XCR2            .set 0005h     ; McBSP Tx Ctrl Reg2
SRGR1           .set 0006h     ; McBSP Sample Rate Gen Reg1
SRGR2           .set 0007h     ; McBSP Sample Rate Gen Reg2
MCR1            .set 0008h     ; McBSP Multichan Reg1
MCR2            .set 0009h     ; McBSP Multichan Reg2
RCERA           .set 000Ah     ; McBSP Rx Chan Enable Reg Partition A
RCERB           .set 000Bh     ; McBSP Rx Chan Enable Reg Partition B
XCERA           .set 000Ch     ; McBSP Tx Chan Enable Reg Partition A
XCERB           .set 000Dh     ; McBSP Tx Chan Enable Reg Partition B
PCR             .set 000Eh     ; McBSP Pin Ctrl Reg
**************
GPIOCR .set 003Ch ; GP I/O Pins Control Reg
GPIOSR .set 003Dh ; GP I/O Pins Status Reg
*––––––––––––––––––– onboard I/O Memory Mapped Register ––––––––––––––––––––
DSP_CPLD_CNTL1 .set 0000h ; Control Reg1
DSP_CPLD_STAT .set 0001h ; Status Reg
DSP_CPLD_DMCNTL .set 0002h ; Data Memory Control Reg
DSP_CPLD_DBIO .set 0003h ; Daughterboard / GPIO Reg
DSP_CPLD_CNTL2 .set 0004h ; Control Reg2
DSP_CPLD_SEM0 .set 0005h ; Semaphore 0
DSP_CPLD_SEM1 .set 0006h ; Semaphore 1