cistpl.c

pcmcia source code

/*======================================================================

    PCMCIA Card Information Structure parser

    cistpl.c 1.98 2002/06/29 06:23:09

    The contents of this file are subject to the Mozilla Public
    License Version 1.1 (the "License"); you may not use this file
    except in compliance with the License. You may obtain a copy of
    the License at http://www.mozilla.org/MPL/

    Software distributed under the License is distributed on an "AS
    IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
    implied. See the License for the specific language governing
    rights and limitations under the License.

    The initial developer of the original code is David A. Hinds
    <[e-mail]>.  Portions created by David A. Hinds
    are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.

    Alternatively, the contents of this file may be used under the
    terms of the GNU General Public License version 2 (the "GPL"), in
    which case the provisions of the GPL are applicable instead of the
    above.  If you wish to allow the use of your version of this file
    only under the terms of the GPL and not to allow others to use
    your version of this file under the MPL, indicate your decision
    by deleting the provisions above and replace them with the notice
    and other provisions required by the GPL.  If you do not delete
    the provisions above, a recipient may use your version of this
    file under either the MPL or the GPL.
    
======================================================================*/

#define __NO_VERSION__

#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/major.h>
#include <linux/errno.h>
#include <linux/timer.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <asm/io.h>
#include <asm/byteorder.h>

#include <pcmcia/cs_types.h>
#include <pcmcia/bus_ops.h>
#include <pcmcia/ss.h>
#include <pcmcia/cs.h>
#include <pcmcia/bulkmem.h>
#include <pcmcia/cisreg.h>
#include <pcmcia/cistpl.h>
#include "cs_internal.h"

static const u_char mantissa[] = {
    10, 12, 13, 15, 20, 25, 30, 35,
    40, 45, 50, 55, 60, 70, 80, 90
};

static const u_int exponent[] = {
    1, 10, 100, 1000, 10000, 100000, 1000000, 10000000
};

/* Convert an extended speed byte to a time in nanoseconds */
#define SPEED_CVT(v) \
    (mantissa[(((v)>>3)&15)-1] * exponent[(v)&7] / 10)
/* Convert a power byte to a current in 0.1 microamps */
#define POWER_CVT(v) \
    (mantissa[((v)>>3)&15] * exponent[(v)&7] / 10)
#define POWER_SCALE(v)		(exponent[(v)&7])

/* Upper limit on reasonable # of tuples */
#define MAX_TUPLES		200

/*====================================================================*/

/* Parameters that can be set with 'insmod' */

#define INT_MODULE_PARM(n, v) static int n = v; MODULE_PARM(n, "i")

INT_MODULE_PARM(cis_width,	0);		/* 16-bit CIS? */

/*======================================================================

    Low-level functions to read and write CIS memory.  I think the
    write routine is only useful for writing one-byte registers.
    
======================================================================*/

/* Bits in attr field */
#define IS_ATTR		1
#define IS_INDIRECT	8

static int setup_cis_mem(socket_info_t *s);

static void set_cis_map(socket_info_t *s, pccard_mem_map *mem)
{
    s->ss_entry(s->sock, SS_SetMemMap, mem);
    if (s->cap.features & SS_CAP_STATIC_MAP) {
	if (s->cis_virt)
	    bus_iounmap(s->cap.bus, s->cis_virt);
	s->cis_virt = bus_ioremap(s->cap.bus, mem->sys_start,
				  s->cap.map_size);
    }
}

void read_cis_mem(socket_info_t *s, int attr, u_int addr,
		  u_int len, void *ptr)
{
    pccard_mem_map *mem = &s->cis_mem;
    u_char *sys, *buf = ptr;
    
    DEBUG(3, "cs: read_cis_mem(%d, %#x, %u)\n", attr, addr, len);
    if (setup_cis_mem(s) != 0) {
	memset(ptr, 0xff, len);
	return;
    }
    mem->flags = MAP_ACTIVE | ((cis_width) ? MAP_16BIT : 0);

    if (attr & IS_INDIRECT) {
	/* Indirect accesses use a bunch of special registers at fixed
	   locations in common memory */
	u_char flags = ICTRL0_COMMON|ICTRL0_AUTOINC|ICTRL0_BYTEGRAN;
	if (attr & IS_ATTR) { addr *= 2; flags = ICTRL0_AUTOINC; }
	mem->card_start = 0; mem->flags = MAP_ACTIVE;
	set_cis_map(s, mem);
	sys = s->cis_virt;
	bus_writeb(s->cap.bus, flags, sys+CISREG_ICTRL0);
	bus_writeb(s->cap.bus, addr & 0xff, sys+CISREG_IADDR0);
	bus_writeb(s->cap.bus, (addr>>8) & 0xff, sys+CISREG_IADDR1);
	bus_writeb(s->cap.bus, (addr>>16) & 0xff, sys+CISREG_IADDR2);
	bus_writeb(s->cap.bus, (addr>>24) & 0xff, sys+CISREG_IADDR3);
	for ( ; len > 0; len--, buf++)
	    *buf = bus_readb(s->cap.bus, sys+CISREG_IDATA0);
    } else {
	u_int inc = 1;
	if (attr) { mem->flags |= MAP_ATTRIB; inc++; addr *= 2; }
	sys += (addr & (s->cap.map_size-1));
	mem->card_start = addr & ~(s->cap.map_size-1);
	while (len) {
	    set_cis_map(s, mem);
	    sys = s->cis_virt + (addr & (s->cap.map_size-1));
	    for ( ; len > 0; len--, buf++, sys += inc) {
		if (sys == s->cis_virt+s->cap.map_size) break;
		*buf = bus_readb(s->cap.bus, sys);
	    }
	    mem->card_start += s->cap.map_size;
	    addr = 0;
	}
    }
    DEBUG(3, "cs:  %#2.2x %#2.2x %#2.2x %#2.2x ...\n",
	  *(u_char *)(ptr+0), *(u_char *)(ptr+1),
	  *(u_char *)(ptr+2), *(u_char *)(ptr+3));
}

void write_cis_mem(socket_info_t *s, int attr, u_int addr,
		   u_int len, void *ptr)
{
    pccard_mem_map *mem = &s->cis_mem;
    u_char *sys, *buf = ptr;
    
    DEBUG(3, "cs: write_cis_mem(%d, %#x, %u)\n", attr, addr, len);
    if (setup_cis_mem(s) != 0) return;
    mem->flags = MAP_ACTIVE | ((cis_width) ? MAP_16BIT : 0);

    if (attr & IS_INDIRECT) {
	/* Indirect accesses use a bunch of special registers at fixed
	   locations in common memory */
	u_char flags = ICTRL0_COMMON|ICTRL0_AUTOINC|ICTRL0_BYTEGRAN;
	if (attr & IS_ATTR) { addr *= 2; flags = ICTRL0_AUTOINC; }
	mem->card_start = 0; mem->flags = MAP_ACTIVE;
	set_cis_map(s, mem);
	sys = s->cis_virt;
	bus_writeb(s->cap.bus, flags, sys+CISREG_ICTRL0);
	bus_writeb(s->cap.bus, addr & 0xff, sys+CISREG_IADDR0);
	bus_writeb(s->cap.bus, (addr>>8) & 0xff, sys+CISREG_IADDR1);
	bus_writeb(s->cap.bus, (addr>>16) & 0xff, sys+CISREG_IADDR2);
	bus_writeb(s->cap.bus, (addr>>24) & 0xff, sys+CISREG_IADDR3);
	for ( ; len > 0; len--, buf++)
	    bus_writeb(s->cap.bus, *buf, sys+CISREG_IDATA0);
    } else {
	int inc = 1;
	if (attr & IS_ATTR) { mem->flags |= MAP_ATTRIB; inc++; addr *= 2; }
	mem->card_start = addr & ~(s->cap.map_size-1);
	while (len) {
	    set_cis_map(s, mem);
	    sys = s->cis_virt + (addr & (s->cap.map_size-1));
	    for ( ; len > 0; len--, buf++, sys += inc) {
		if (sys == s->cis_virt+s->cap.map_size) break;
		bus_writeb(s->cap.bus, *buf, sys);
	    }
	    mem->card_start += s->cap.map_size;
	    addr = 0;
	}
    }
}

/*======================================================================

    This is tricky... when we set up CIS memory, we try to validate
    the memory window space allocations.
    
======================================================================*/

/* Scratch pointer to the socket we use for validation */
static socket_info_t *vs = NULL;

/* Validation function for cards with a valid CIS */
static int cis_readable(u_long base)
{
    cisinfo_t info1, info2;
    int ret;
    vs->cis_mem.sys_start = base;
    vs->cis_mem.sys_stop = base+vs->cap.map_size-1;
    vs->cis_virt = bus_ioremap(vs->cap.bus, base, vs->cap.map_size);
    ret = validate_cis(vs->clients, &info1);
    /* invalidate mapping and CIS cache */
    bus_iounmap(vs->cap.bus, vs->cis_virt); vs->cis_used = 0;
    if ((ret != 0) || (info1.Chains == 0))
	return 0;
    vs->cis_mem.sys_start = base+vs->cap.map_size;
    vs->cis_mem.sys_stop = base+2*vs->cap.map_size-1;
    vs->cis_virt = bus_ioremap(vs->cap.bus, base+vs->cap.map_size,
			       vs->cap.map_size);
    ret = validate_cis(vs->clients, &info2);
    bus_iounmap(vs->cap.bus, vs->cis_virt); vs->cis_used = 0;
    return ((ret == 0) && (info1.Chains == info2.Chains));
}

/* Validation function for simple memory cards */
static int checksum(u_long base)
{
    int i, a, b, d;
    vs->cis_mem.sys_start = base;
    vs->cis_mem.sys_stop = base+vs->cap.map_size-1;
    vs->cis_virt = bus_ioremap(vs->cap.bus, base, vs->cap.map_size);
    vs->cis_mem.card_start = 0;
    vs->cis_mem.flags = MAP_ACTIVE;
    vs->ss_entry(vs->sock, SS_SetMemMap, &vs->cis_mem);
    /* Don't bother checking every word... */
    a = 0; b = -1;
    for (i = 0; i < vs->cap.map_size; i += 44) {
	d = bus_readl(vs->cap.bus, vs->cis_virt+i);
	a += d; b &= d;
    }
    bus_iounmap(vs->cap.bus, vs->cis_virt);
    return (b == -1) ? -1 : (a>>1);
}

static int checksum_match(u_long base)
{
    int a = checksum(base), b = checksum(base+vs->cap.map_size);
    return ((a == b) && (a >= 0));
}

static int setup_cis_mem(socket_info_t *s)
{
    if (!(s->cap.features & SS_CAP_STATIC_MAP) &&
	(s->cis_mem.sys_start == 0)) {
	int low = !(s->cap.features & SS_CAP_PAGE_REGS);
	vs = s;
	validate_mem(cis_readable, checksum_match, low);
	s->cis_mem.sys_start = 0;
	vs = NULL;
	if (find_mem_region(&s->cis_mem.sys_start, s->cap.map_size,
			    s->cap.map_size, low, "card services")) {
	    printk(KERN_NOTICE "cs: unable to map card memory!\n");
	    return CS_OUT_OF_RESOURCE;
	}
	s->cis_mem.sys_stop = s->cis_mem.sys_start+s->cap.map_size-1;
	s->cis_virt = bus_ioremap(s->cap.bus, s->cis_mem.sys_start,
				  s->cap.map_size);
    }
    return 0;
}

void release_cis_mem(socket_info_t *s)
{
    if (s->cis_mem.sys_start != 0) {
	s->cis_mem.flags &= ~MAP_ACTIVE;
	s->ss_entry(s->sock, SS_SetMemMap, &s->cis_mem);
	if (!(s->cap.features & SS_CAP_STATIC_MAP))
	    release_mem_region(s->cis_mem.sys_start, s->cap.map_size);
	bus_iounmap(s->cap.bus, s->cis_virt);
	s->cis_mem.sys_start = 0;
	s->cis_virt = NULL;
    }
}

/*======================================================================

    This is a wrapper around read_cis_mem, with the same interface,
    but which caches information, for cards whose CIS may not be
    readable all the time.
    
======================================================================*/

static void read_cis_cache(socket_info_t *s, int attr, u_int addr,
			   u_int len, void *ptr)
{
    int i;
    char *caddr;

    if (s->fake_cis) {
	if (s->fake_cis_len > addr+len)
	    memcpy(ptr, s->fake_cis+addr, len);
	else
	    memset(ptr, 0xff, len);
	return;
    }
    caddr = s->cis_cache;
    for (i = 0; i < s->cis_used; i++) {
	if ((s->cis_table[i].addr == addr) &&
	    (s->cis_table[i].len == len) &&
	    (s->cis_table[i].attr == attr)) break;
	caddr += s->cis_table[i].len;
    }
    if (i < s->cis_used) {
	memcpy(ptr, caddr, len);
	return;
    }
#ifdef CONFIG_CARDBUS
    if (s->state & SOCKET_CARDBUS)
	read_cb_mem(s, 0, attr, addr, len, ptr);
    else
#endif
	read_cis_mem(s, attr, addr, len, ptr);
    /* Copy data into the cache, if there is room */
    if ((i < MAX_CIS_TABLE) &&
	(caddr+len < s->cis_cache+MAX_CIS_DATA)) {
	s->cis_table[i].addr = addr;
	s->cis_table[i].len = len;
	s->cis_table[i].attr = attr;
	s->cis_used++;
	memcpy(caddr, ptr, len);
    }	    
}

/*======================================================================

    This verifies if the CIS of a card matches what is in the CIS
    cache.
    
======================================================================*/

int verify_cis_cache(socket_info_t *s)
{
    char buf[256], *caddr;
    int i;
    
    caddr = s->cis_cache;
    for (i = 0; i < s->cis_used; i++) {
#ifdef CONFIG_CARDBUS
	if (s->state & SOCKET_CARDBUS)
	    read_cb_mem(s, 0, s->cis_table[i].attr, s->cis_table[i].addr,
			s->cis_table[i].len, buf);
	else
#endif
	    read_cis_mem(s, s->cis_table[i].attr, s->cis_table[i].addr,
			 s->cis_table[i].len, buf);
	if (memcmp(buf, caddr, s->cis_table[i].len) != 0)
	    break;
	caddr += s->cis_table[i].len;
    }
    return (i < s->cis_used);
}

/*======================================================================

    For really bad cards, we provide a facility for uploading a
    replacement CIS.
    
======================================================================*/

int replace_cis(client_handle_t handle, cisdump_t *cis)
{
    socket_info_t *s;
    if (CHECK_HANDLE(handle))
	return CS_BAD_HANDLE;
    s = SOCKET(handle);
    if (s->fake_cis != NULL) {
	kfree(s->fake_cis);
	s->fake_cis = NULL;
    }
    if (cis->Length > CISTPL_MAX_CIS_SIZE)
	return CS_BAD_SIZE;
    s->fake_cis = kmalloc(cis->Length, GFP_KERNEL);
    if (s->fake_cis == NULL)
	return CS_OUT_OF_RESOURCE;
    s->fake_cis_len = cis->Length;
    memcpy(s->fake_cis, cis->Data, cis->Length);
    return CS_SUCCESS;
}

/*======================================================================

    The high-level CIS tuple services
    
======================================================================*/

typedef struct tuple_flags {
    u_int		link_space:4;
    u_int		has_link:1;
    u_int		mfc_fn:3;
    u_int		space:4;
} tuple_flags;

#define LINK_SPACE(f)	(((tuple_flags *)(&(f)))->link_space)
#define HAS_LINK(f)	(((tuple_flags *)(&(f)))->has_link)
#define MFC_FN(f)	(((tuple_flags *)(&(f)))->mfc_fn)
#define SPACE(f)	(((tuple_flags *)(&(f)))->space)

int get_next_tuple(client_handle_t handle, tuple_t *tuple);

int get_first_tuple(client_handle_t handle, tuple_t *tuple)
{
    socket_info_t *s;
    if (CHECK_HANDLE(handle))
	return CS_BAD_HANDLE;
    s = SOCKET(handle);
    if (!(s->state & SOCKET_PRESENT))
	return CS_NO_CARD;
    tuple->TupleLink = tuple->Flags = 0;
#ifdef CONFIG_CARDBUS
    if (s->state & SOCKET_CARDBUS) {
	u_int ptr;
	pcibios_read_config_dword(s->cap.cardbus, 0, 0x28, &ptr);
	tuple->CISOffset = ptr & ~7;
	SPACE(tuple->Flags) = (ptr & 7);
    } else
#endif
    {
	/* Assume presence of a LONGLINK_C to address 0 */
	tuple->CISOffset = tuple->LinkOffset = 0;
	SPACE(tuple->Flags) = HAS_LINK(tuple->Flags) = 1;
    }
    if (!(s->state & SOCKET_CARDBUS) && (s->functions > 1) &&
	!(tuple->Attributes & TUPLE_RETURN_COMMON)) {
	cisdata_t req = tuple->DesiredTuple;
	tuple->DesiredTuple = CISTPL_LONGLINK_MFC;
	if (get_next_tuple(handle, tuple) == CS_SUCCESS) {
	    tuple->DesiredTuple = CISTPL_LINKTARGET;
	    if (get_next_tuple(handle, tuple) != CS_SUCCESS)
		return CS_NO_MORE_ITEMS;
	} else
	    tuple->CISOffset = tuple->TupleLink = 0;
	tuple->DesiredTuple = req;
    }
    return get_next_tuple(handle, tuple);
}

static int follow_link(socket_info_t *s, tuple_t *tuple)
{
    u_char link[5];
    u_int ofs;

    if (MFC_FN(tuple->Flags)) {
	/* Get indirect link from the MFC tuple */
	read_cis_cache(s, LINK_SPACE(tuple->Flags),
		       tuple->LinkOffset, 5, link);
	ofs = le32_to_cpu(*(u_int *)(link+1));
	SPACE(tuple->Flags) = (link[0] == CISTPL_MFC_ATTR);
	/* Move to the next indirect link */
	tuple->LinkOffset += 5;
	MFC_FN(tuple->Flags)--;
    } else if (HAS_LINK(tuple->Flags)) {
	ofs = tuple->LinkOffset;
	SPACE(tuple->Flags) = LINK_SPACE(tuple->Flags);
	HAS_LINK(tuple->Flags) = 0;
    } else {
	return -1;
    }
    if (!(s->state & SOCKET_CARDBUS) && SPACE(tuple->Flags)) {
	/* This is ugly, but a common CIS error is to code the long
	   link offset incorrectly, so we check the right spot... */
	read_cis_cache(s, SPACE(tuple->Flags), ofs, 5, link);
	if ((link[0] == CISTPL_LINKTARGET) && (link[1] >= 3) &&
	    (strncmp(link+2, "CIS", 3) == 0))
	    return ofs;
	/* Then, we try the wrong spot... */
	ofs = ofs >> 1;
    }
    read_cis_cache(s, SPACE(tuple->Flags), ofs, 5, link);
    if ((link[0] != CISTPL_LINKTARGET) || (link[1] < 3) ||
	(strncmp(link+2, "CIS", 3) != 0))
	return -1;
    return ofs;
}

int get_next_tuple(client_handle_t handle, tuple_t *tuple)
{