tim2_ar.lst

aduc814的汇编程序例子

TIM2_AR                                                                                                       PAGE 1

                       1    ;====================================================================
                       2    ;
                       3    ; Author        : ADI - Apps
                       4    ;
                       5    ; Date          : Febuary 2001
                       6    ;
                       7    ; File          : Tim2_AR.asm
                       8    ;
                       9    ; Hardware      : ADuC814
                      10    ;
                      11    ; Description   : Flashes light every 256*56 machine cycles (@ 4Hz
                      12    ;                 for core freq = 2.097152MHz) using timer 2 in Auto 
                      13    ;                 Reload Mode. 
                      14    ;____________________________________________________________________
                      15    $MOD814                       ;Use 8052 predefined Symbols
                      16    
  00B3                17    LED     EQU     P3.3
                      18    
                      19    ;____________________________________________________________________
                      20                                                      ; BEGINNING OF CODE
----                  21    CSEG
0000                  22    ORG 0000H
                      23    
0000 020060           24            JMP MAIN
                      25    ;____________________________________________________________________
                      26                                              ; TIMER 2 INTERRUPT ROUTINE
002B                  27    ORG 002Bh
                      28    
002B B2B3             29            CPL     LED        ; Flash the light
002D C2CF             30            CLR     TF2        ; The TF2 flag must be cleared in software
002F 32               31            RETI
                      32    
                      33    
                      34    ;____________________________________________________________________
                      35                                                           ; MAIN PROGRAM
0060                  36    ORG 0060h                    ; Start code at address above interrupts                   
                      37    
0060                  38    MAIN:                         ; Main program
                      39    
0060 D2AD             40            SETB     ET2          ; Enable timer2 interrupt
                      41    
0062 75CC00           42            MOV      TL2, #00h    ; Initialise timer 2 registers & Reload 
0065 75CDC9           43            MOV      TH2, #0C9h    ; values to rollover every 55*256
0068 75CA00           44            MOV      RCAP2L, #00h ; machine cycles (17.47us)
006B 75CBC8           45            MOV      RCAP2H, #0C8h
                      46    
006E D2AF             47            SETB     EA           ; Enable interrupts
                      48    
0070 75C804           49            MOV      T2CON, #04h  ; Start timer 2 in 16-bit reload mode
                      50    
0073 80FE             51            JMP      $            ; Wait here for timer Interrupts
                      52    
                      53    END

VERSION 1.2h ASSEMBLY COMPLETE, 0 ERRORS FOUND
TIM2_AR                                                                                                       PAGE 2

EA . . . . . . . . . . . . . . .  B ADDR  00AFH  PREDEFINED  
ET2. . . . . . . . . . . . . . .  B ADDR  00ADH  PREDEFINED  
LED. . . . . . . . . . . . . . .    NUMB  00B3H  
MAIN . . . . . . . . . . . . . .  C ADDR  0060H  
P3 . . . . . . . . . . . . . . .  D ADDR  00B0H  PREDEFINED  
RCAP2H . . . . . . . . . . . . .  D ADDR  00CBH  PREDEFINED  
RCAP2L . . . . . . . . . . . . .  D ADDR  00CAH  PREDEFINED  
T2CON. . . . . . . . . . . . . .  D ADDR  00C8H  PREDEFINED  
TF2. . . . . . . . . . . . . . .  B ADDR  00CFH  PREDEFINED  
TH2. . . . . . . . . . . . . . .  D ADDR  00CDH  PREDEFINED  
TL2. . . . . . . . . . . . . . .  D ADDR  00CCH  PREDEFINED