mcu_drv.h

atmel c5122 USB C51程序

/*H**************************************************************************
* NAME:         mcu_drv.h         
*----------------------------------------------------------------------------
* Copyright (c) 2003 Atmel.
*----------------------------------------------------------------------------
* RELEASE:      c5122-scib-usb-hid-2_4_0      
* REVISION:     1.7.6.18     
*----------------------------------------------------------------------------
* PURPOSE:
* This file contains the AT8xC5122 driver definitions
*****************************************************************************/

#ifndef _MCU_DRV_H_
#define _MCU_DRV_H_

/*_____ I N C L U D E S ____________________________________________________*/

#ifndef ASM_INCLUDE
#include <intrins.h>
#endif

/*_____ M A C R O S ________________________________________________________*/


/*_____ D E F I N I T I O N ________________________________________________*/

/*--------------------------- SYSTEM MANAGEMENT -----------------------*/
#define MSK_PCON_POF         0x10
#define MSK_SMOD1            0x80    /* PCON */
#define MSK_SMOD0            0x40
#define MSK_GF1              0x08
#define MSK_GF0              0x04
#define MSK_PD               0x02
#define MSK_IDL              0x01


#define MSK_EXT16            0x40    /* AUXR */
#define MSK_M0               0x20
#define MSK_DPHDIS           0x10
#define MSK_XRS              0x04
#define MSK_EXTRAM           0x02
#define MSK_AO               0x01
#define ERAM_256             0x00
#define ERAM_512             0x04
//#define ERAM_1024            0x08
//#define ERAM_2048            0x0C

#define VAL_DIV2             0x0F    /* fcpu = fosc*1/(2*(16-CKRL)) */
#define VAL_DIV4             0x0E
#define VAL_DIV6             0x0D
#define VAL_DIV8             0x0C
#define VAL_DIV32            0x00
#define VAL_96MHZ            0xB0
#define MSK_CKSEL_CKS        0x01
#define MSK_PLLCON_PLLEN     0x02
#define MSK_PLLCON_EXT48     0x04
#define MSK_PLLCON_PLOCK     0x01
#define MSK_PLLEN            0x02    /* PLLCON */
#define MSK_EXT48            0x04
#define MSK_PLOCK            0x01

#define MSK_RCON_RPS           8     /* RCON */

#define B_IPHC                 6             /* For SFR addresses 0-8 */ 
#define B_IPHT2                5              
#define B_IPHS                 4
#define B_IPHT1                3
#define B_IPHX1                2
#define B_IPHT0                1
#define B_IPHX0                0

#define B_CIDL                 7
#define B_WDTE                 6
#define B_CPS1                 2
#define B_CPS0                 1
#define B_ECF                  0

#define B_ECOMX                6
#define B_CAPPX                5
#define B_CAPNX                4
#define B_MATX                 3
#define B_TOGX                 2
#define B_PWMX                 1
#define B_ECCFX                0

/*--------------------------- INTERRUPTIONS ----------------------------*/

#define IRQ_INT0               0
#define IRQ_T0                 1
#define IRQ_INT1               2
#define IRQ_T1                 3
#define IRQ_UART               5
#define IRQ_KBD                7
#define IRQ_SPI                9
#define IRQ_SCIB               10
#define IRQ_USB                13

#define MSK_EA                 0x80    /* IEN0 */
#define MSK_EUSB               0x40    /* IEN1 */
#define MSK_IPH1_PKBH          0x01    /* PKBH */
#define MSK_IPL1_PKBL          0x01    /* PKBL */
#define MSK_IEN1_EKB           0x01    /* EKB */
#define MSK_IPL1_PSCIL         0x08    /* PSCIL */
#define MSK_IPH1_PSCIH         0x08    /* PSCIH */

#define MSK_ISEL_CPLEV         0x80
#define MSK_ISEL_OEIT          0x40
#define MSK_ISEL_PRESIT        0x20
#define MSK_ISEL_RXIT          0x10 
#define MSK_ISEL_OELEV         0x08
#define MSK_ISEL_OEEN          0x04
#define MSK_ISEL_PRESEN        0x02
#define MSK_ISEL_RXEN          0x01

/*--------------------------- WATCHDOG --------------------------------*/

#define MSK_WTO     0x07    /* WDTPRG*/

/*--------------------------- PORTS -----------------------------------*/

#define MSK_PMOD1_P5H_QB       0x3F    /* P5-6 to P5-7 in Quasi Bidirectionnal mode */
#define MSK_PMOD1_P5H_OPP      0x40    /* P5-6 to P5-7 in Output Push Pull mode */
#define MSK_PMOD1_P5H_IWD      0x80    /* P5-6 to P5-7 in Input Weak pull-Down mode */
#define MSK_PMOD1_P5H_IWU      0xC0    /* P5-6 to P5-7 in Input Weak pull-Up mode */

#define MSK_PMOD1_P5M_QB       0xCF    /* P5-3 to P5-5 in Quasi Bidirectionnal mode */
#define MSK_PMOD1_P5M_OPP      0x10    /* P5-3 to P5-5 in Output Push Pull mode */
#define MSK_PMOD1_P5M_IWD      0x20    /* P5-3 to P5-5 in Input Weak pull-Down mode*/
#define MSK_PMOD1_P5M_IWU      0x30    /* P5-3 to P5-5 in Input Weak pull-Up mode*/

#define MSK_PMOD1_P5L_QB       0xF3    /* P5-0 to P5-2 in Quasi Bidirectionnal mode */
#define MSK_PMOD1_P5L_OPP      0x04    /* P5-0 to P5-2 in Output Push Pull mode */
#define MSK_PMOD1_P5L_IMU      0x08    /* P5-0 to P5-2 in Input Medium pull-Up mode*/
#define MSK_PMOD1_P5L_IWU      0x0C    /* P5-0 to P5-2 in Input Weak pull-Up mode*/

#define MSK_PMOD0_P2_QB        0xCF    /* P2 in Quasi Bidirectionnal mode */
#define MSK_PMOD0_P2_OPP       0x10    /* P2 in Output Push Pull mode */
#define MSK_PMOD0_P2_OLS       0x20    /* P2 in Output Low Speed mode */
#define MSK_PMOD0_P2_IWD       0x30    /* P2 in Input Weak pull-Down mode */

/*--------------------------- SPI CONTROLLER -----------------------------*/

#define MSK_SPR                0x83    /* SPCON */
#define MSK_SPEN               0x40
#define MSK_SSDIS              0x20
#define MSK_MSTR               0x10
#define MSK_MODE               0x0C
#define MSK_CPOL               0x08
#define MSK_CPHA               0x04

#define MSK_SPIF               0x80    /* SPSTA */
#define MSK_WCOL               0x40
#define MSK_MODF               0x10

/*--------------------------- KEYBOARD CONTROLLER -----------------------*/

#define MSK_KBLS_LLD           0x00    /* Low Level Detection */
#define MSK_KBLS_HLD           0xFF    /* High Level Detection */
#define MSK_KBF_RST_FLAG0      0x01    /* Reset flag 0 */
#define MSK_KBE_STDIO          0x00    /* Keyboard lines set as standard I/O */
#define MSK_KBE_INTERRUPT      0xFF    /* Keyboard lines set to generate an interrupt */

/*--------------------------- USB MACRO -------------------------------*/

///////////////////////////////////////////////////////////////////////// 
//BUG#227 : USB Wake-up interrupt bit.
//WUPCPU bit in USBINT register is not cleared if CPU frequency is greater 
//or equal than 12 Mhz/X2
#define C5122_BUG227_USB_WAKEUP_INTERRUPT
/////////////////////////////////////////////////////////////////////////

#define MSK_TXCMPL             0x01    /* UEPSTAX */
#define MSK_RXOUTB0            0x02
#define MSK_RXOUT              0x02
#define MSK_RXOUTB1            0x40
#define MSK_RXOUTB0B1          0x42
#define MSK_RXSETUP            0x04
#define MSK_STALLED            0x08
#define MSK_TXRDY              0x10
#define MSK_STALLRQ            0x20
#define MSK_DIR                0x80
#define MSK_EP_DIR             0x7F

#define MSK_NAKIEN             0x40    /* UEPCONX */
#define MSK_NAKOUT             0x20
#define MSK_NAKIN              0x10

#define MSK_SPINT              0x01    /* USBINT */
#define MSK_SOFINT             0x08
#define MSK_EORINT             0x10
#define MSK_WUPCPU             0x20

#define MSK_ESPINT             0x01    /* USBIEN */
#define MSK_ESOFINT            0x08
#define MSK_EEORINT            0x10
#define MSK_EWUPCPU            0x20

#define MSK_SUSPCLK            0x40    /* USBCON */
#define MSK_DETACH             0x10

#define MSK_ESPINT             0x01
#define MSK_EEORINT            0x10
#define MSK_EWUPCPU            0x20

#define MSK_USBE               0x80    /* USBCON */
#define MSK_CONFG              0x02
#define MSK_FADDEN             0x01
#define MSK_UPRSM              0x08
#define MSK_SDRMWUP            0x20
#define MSK_RMWUPE             0x04

/*--------------------------- SCIB MACRO -------------------------------*/

//Sfr (SCSR    , 0xAB);

/* #define MSK_SCSR_ 0x80 reserved*/ 
/* #define MSK_SCSR_ 0x40 reserved*/
/* #define MSK_SCSR_ 0x20 reserved*/
#define MSK_SCSR_REPSEL        0x10
#define MSK_SCSR_ALTKPS1       0x08
#define MSK_SCSR_ALTKPS0       0x04
#define MSK_SCSR_SCCLK1        0x02
#define MSK_SCSR_SCRS          0x01

//Sfr (SCCON     , 0xAC);   /*0xAC if SCRS = 0*/

#define MSK_SCCON_CLK          0x80  
/* #define MSK_SCSRC_ 0x40 reserved*/
#define MSK_SCCON_CARDC8          0x20
#define MSK_SCCON_CARDC4       0x10
#define MSK_SCCON_CARDIO       0x08
#define MSK_SCCON_CARDCLK      0x04
#define MSK_SCCON_CARDRST      0x02
#define MSK_SCCON_CARDVCC      0x01

//Sfr (SCETU0    , 0xAC);   /*0xAC if SCRS = 1*/

#define MSK_SCETU0_ETU7        0x80
#define MSK_SCETU0_ETU6        0x40
#define MSK_SCETU0_ETU5        0x20
#define MSK_SCETU0_ETU4        0x10
#define MSK_SCETU0_ETU3        0x08
#define MSK_SCETU0_ETU2        0x04
#define MSK_SCETU0_ETU1        0x02
#define MSK_SCETU0_ETU0        0x01

//Sfr (SCISR    , 0xAD);    /*0xAD if SCRS = 0*/

#define MSK_SCISR_SCTBE        0x80
#define MSK_SCISR_CARDIN       0x40
/*#define MSK_SCISR_ 0x20 reserved*/
#define MSK_SCISR_VCARDOK      0x10
#define MSK_SCISR_SCWTO        0x08
#define MSK_SCISR_SCTC         0x04
#define MSK_SCISR_SCRC         0x02
#define MSK_SCISR_SCPE         0x01

//Sfr (SCETU1   , 0xAD);    /*0xAD if SCRS = 1*/

#define MSK_SCETU1_COMP        0x80
/*#define MSK_SCETU1_ 0x40 reserved*/
/*#define MSK_SCETU1_ 0x20 reserved*/
/*#define MSK_SCETU1_ 0x10 reserved*/
/*#define MSK_SCETU1_ 0x08 reserved*/
#define MSK_SCETU1_ETU10       0x40
#define MSK_SCETU1_ETU9        0x20
#define MSK_SCETU1_ETU8        0x10

//Sfr (SCIIR    , 0xAE);    /*0xAE if SCRS = 0*/

#define MSK_SCIIR_SCTBI        0x80
/*#define MSK_SCIIR_ 0x40 reserved*/
#define MSK_SCIIR_ICARDERR     0x20
#define MSK_SCIIR_VCARDERR     0x10
#define MSK_SCIIR_SCWTI        0x08
#define MSK_SCIIR_SCTI         0x04
#define MSK_SCIIR_SCRI         0x02
#define MSK_SCIIR_SCPI         0x01

//Sfr (SCIER    , 0xAE);    /*0xAE if SCRS = 1*/

#define MSK_SCIER_ESCTBI       0x80
/*#define MSK_SCIER_ 0x40 reserved*/
#define MSK_SCIER_ICARDER      0x20
#define MSK_SCIER_EVCARDER     0x10
#define MSK_SCIER_ESCWT        0x08
#define MSK_SCIER_ESCTI        0x04
#define MSK_SCIER_ESCRI        0x02
#define MSK_SCIER_ESCPI        0x01

//Sfr (CKCON1    , 0xAF);   /*0xAF*/

#define MSK_CKCON1_SCX2        0x08

//Sfr (IEN1    , 0xB1);     /* 0xB1 */

/*#define MSK_IEN1_ 0x80 reserved*/
#define MSK_IEN1_EUSB          0x40
/*#define MSK_IEN1_ 0x20 reserved*/
/*#define MSK_IEN1_ 0x10 reserved*/
#define MSK_IEN1_ESCI          0x08
/*#define MSK_IEN1_ 0x04 reserved*/
/*#define MSK_IEN1_ 0x02 reserved*/
#define MSK_IEN1_EKB           0x01
#define MSK_IEN1_ESPI          0x04 

//Sfr (SCICR    , 0xB6);

#define MSK_SCICR_RESET        0x80
#define MSK_SCICR_CARDDET      0x40 
#define MSK_SCICR_VCARD1       0x20 
#define MSK_SCICR_VCARD0       0x10 
#define MSK_SCICR_UART         0x08 
#define MSK_SCICR_WTEN         0x04 
#define MSK_SCICR_CREP         0x02 
#define MSK_SCICR_CONV         0x01 


#define MSK_DCCKPS_BOOST        0x30

/* CLOCK TREE */
#define MSK_X2                  0x01 /* CKCON */
#define MSK_T0X2                0x02
#define MSK_T1X2                0x04
#define MSK_T2X2                0x08
#define MSK_UARTX2              0x10
#define MSK_PCAX2               0x20
#define MSK_WDX2                0x40


/* TIMERS */
#define MSK_GATE1               0x80 /* TMOD */
#define MSK_C_T1                0x40
#define MSK_MO1                 0x30
#define MSK_GATE0               0x08
#define MSK_C_T0                0x04
#define MSK_MO0                 0x03


/* UART */
#define MSK_UART_MODE0          0x00 /* SCON */
#define MSK_UART_8BIT           0x40
#define MSK_UART_MODE1          0x40
#define MSK_UART_MODE2          0x80
#define MSK_UART_MODE3          0xC0
#define MSK_UART_9BIT           0xC0
#define MSK_UART_MULTIPROC      0x20
#define MSK_UART_ENABLE_RX      0x10
#define MSK_UART_TX_BIT9        0x08
#define MSK_UART_RX_BIT9        0x04
#define MSK_UART_TX_READY       0x02
#define MSK_UART_RX_DONE        0x01


/* WATCHDOG */
#define MSK_WTO                 0x07 /* WDTPRG*/