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📄 interrupt.cc

📁 Small Device C Compiler 面向Inter8051
💻 CC
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/* * Simulator of microcontrollers (interrupt.cc) * * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. *  * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu * *//* This file is part of microcontroller simulator: ucsim.UCSIM is free software; you can redistribute it and/or modifyit under the terms of the GNU General Public License as published bythe Free Software Foundation; either version 2 of the License, or(at your option) any later version.UCSIM is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; without even the implied warranty ofMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See theGNU General Public License for more details.You should have received a copy of the GNU General Public Licensealong with UCSIM; see the file COPYING.  If not, write to the FreeSoftware Foundation, 59 Temple Place - Suite 330, Boston, MA02111-1307, USA. *//*@1@*/// prj#include "utils.h"// sim#include "itsrccl.h"// local#include "interruptcl.h"#include "regs51.h"//#include "uc51cl.h"#include "types51.h"cl_interrupt::cl_interrupt(class cl_uc *auc):  cl_hw(auc, HW_INTERRUPT, 0, "irq"){  was_reti= DD_FALSE;}intcl_interrupt::init(void){  class cl_mem *sfr;  sfr= uc->mem(MEM_SFR);  if (sfr)    {      //sfr->register_hw(IE, this, 0);      register_cell(sfr, IE, 0, wtd_restore);      register_cell(sfr, TCON, &cell_tcon, wtd_restore_write);      bit_INT0= sfr->read(P3) & bm_INT0;      bit_INT1= sfr->read(P3) & bm_INT1;    }  return(0);}voidcl_interrupt::added_to_uc(void){  uc->it_sources->add(new cl_it_src(bmEX0, TCON, bmIE0, 0x0003, true,				    "external #0", 1));  uc->it_sources->add(new cl_it_src(bmEX1, TCON, bmIE1, 0x0013, true,				    "external #1", 3));}voidcl_interrupt::write(class cl_cell *cell, t_mem *val){  if (cell == cell_tcon)    {      bit_IT0= *val & bmIT0;      bit_IT1= *val & bmIT1;    }  else    // IE register    was_reti= DD_TRUE;}/*voidcl_interrupt::mem_cell_changed(class cl_mem *mem, t_addr addr){}*/intcl_interrupt::tick(int cycles){  if (!bit_IT0 && !bit_INT0)    cell_tcon->set_bit1(bmIE0);  if (!bit_IT1 && !bit_INT1)    cell_tcon->set_bit1(bmIE1);  return(resGO);}voidcl_interrupt::reset(void){  was_reti= DD_FALSE;}voidcl_interrupt::happen(class cl_hw *where, enum hw_event he, void *params){  struct ev_port_changed *ep= (struct ev_port_changed *)params;  if (where->cathegory == HW_PORT &&      he == EV_PORT_CHANGED &&      ep->id == 3)    {      t_mem p3n= ep->new_pins & ep->new_value;      t_mem p3o= ep->pins & ep->prev_value;      if (bit_IT0 &&	  !(p3n & bm_INT0) &&	  (p3o & bm_INT0))	cell_tcon->set_bit1(bmIE0);      if (bit_IT1 &&	  !(p3n & bm_INT1) &&	  (p3o & bm_INT1))	cell_tcon->set_bit1(bmIE1);      bit_INT0= p3n & bm_INT0;      bit_INT1= p3n & bm_INT1;    }}voidcl_interrupt::print_info(class cl_console *con){  int ie= uc->get_mem(MEM_SFR, IE);  int i;  con->dd_printf("Interrupts are %s. Interrupt sources:\n",		 (ie&bmEA)?"enabled":"disabled");  con->dd_printf("  Handler  En  Pr Req Act Name\n");  for (i= 0; i < uc->it_sources->count; i++)    {      class cl_it_src *is= (class cl_it_src *)(uc->it_sources->at(i));      con->dd_printf("  0x%06x", is->addr);      con->dd_printf(" %-3s", (ie&(is->ie_mask))?"en":"dis");      con->dd_printf(" %2d", uc->it_priority(is->ie_mask));      con->dd_printf(" %-3s",		     (uc->get_mem(MEM_SFR, is->src_reg)&(is->src_mask))?		     "YES":"no");      con->dd_printf(" %-3s", (is->active)?"act":"no");      con->dd_printf(" %s", object_name(is));      con->dd_printf("\n");    }  con->dd_printf("Active interrupt service(s):\n");  con->dd_printf("  Pr Handler  PC       Source\n");  for (i= 0; i < uc->it_levels->count; i++)    {      class it_level *il= (class it_level *)(uc->it_levels->at(i));      if (il->level >= 0)	{	  con->dd_printf("  %2d", il->level);	  con->dd_printf(" 0x%06x", il->addr);	  con->dd_printf(" 0x%06x", il->PC);	  con->dd_printf(" %s", (il->source)?(object_name(il->source)):			 "nothing");	  con->dd_printf("\n");	}    }}/* End of s51.src/interrupt.cc */

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