📄 z80.cc
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/* * Simulator of microcontrollers (z80.cc) * * some z80 code base from Karl Bongers karl@turbobit.com * * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. * * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu * *//* This file is part of microcontroller simulator: ucsim.UCSIM is free software; you can redistribute it and/or modifyit under the terms of the GNU General Public License as published bythe Free Software Foundation; either version 2 of the License, or(at your option) any later version.UCSIM is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; without even the implied warranty ofMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See theGNU General Public License for more details.You should have received a copy of the GNU General Public Licensealong with UCSIM; see the file COPYING. If not, write to the FreeSoftware Foundation, 59 Temple Place - Suite 330, Boston, MA02111-1307, USA. *//*@1@*/#include "ddconfig.h"#include <stdarg.h> /* for va_list */#include <stdio.h>#include <stdlib.h>#include <ctype.h>#include "i_string.h"// prj#include "pobjcl.h"// sim#include "simcl.h"// local#include "z80cl.h"#include "glob.h"#include "regsz80.h"#define uint32 t_addr#define uint8 unsigned char#define int8 char/*******************************************************************//* * Base type of Z80 controllers */cl_z80::cl_z80(class cl_sim *asim): cl_uc(asim){ type= CPU_Z80;}intcl_z80::init(void){ cl_uc::init(); /* Memories now exist */ rom= mem(MEM_ROM);// ram= mem(MEM_XRAM); ram= rom; // zero out ram(this is assumed in regression tests) for (int i=0x8000; i<0x10000; i++) { ram->set((t_addr) i, 0); } return(0);}char *cl_z80::id_string(void){ return("unspecified Z80");}/* * Making elements of the controller */t_addrcl_z80::get_mem_size(enum mem_class type){ switch(type) { case MEM_ROM: return(0x10000); case MEM_XRAM: return(0x10000); default: return(0); } return(cl_uc::get_mem_size(type));}voidcl_z80::mk_hw_elements(void){ //class cl_base *o; /* t_uc::mk_hw() does nothing */}/* * Help command interpreter */struct dis_entry *cl_z80::dis_tbl(void){ return(disass_z80);}/*struct name_entry *cl_z80::sfr_tbl(void){ return(0);}*//*struct name_entry *cl_z80::bit_tbl(void){ //FIXME return(0);}*/intcl_z80::inst_length(t_addr addr){ int len = 0; char *s; s = get_disasm_info(addr, &len, NULL, NULL); return len;}intcl_z80::inst_branch(t_addr addr){ int b; char *s; s = get_disasm_info(addr, NULL, &b, NULL); return b;}intcl_z80::longest_inst(void){ return 4;}char *cl_z80::get_disasm_info(t_addr addr, int *ret_len, int *ret_branch, int *immed_offset){ char *b = NULL; uint code; int len = 0; int immed_n = 0; int i; int start_addr = addr; struct dis_entry *dis_e; code= get_mem(MEM_ROM, addr++); dis_e = NULL; switch(code) { case 0xcb: /* ESC code to lots of op-codes, all 2-byte */ code= get_mem(MEM_ROM, addr++); i= 0; while ((code & disass_z80_cb[i].mask) != disass_z80_cb[i].code && disass_z80_cb[i].mnemonic) i++; dis_e = &disass_z80_cb[i]; b= disass_z80_cb[i].mnemonic; if (b != NULL) len += (disass_z80_cb[i].length + 1); break; case 0xed: /* ESC code to about 80 opcodes of various lengths */ code= get_mem(MEM_ROM, addr++); i= 0; while ((code & disass_z80_ed[i].mask) != disass_z80_ed[i].code && disass_z80_ed[i].mnemonic) i++; dis_e = &disass_z80_ed[i]; b= disass_z80_ed[i].mnemonic; if (b != NULL) len += (disass_z80_ed[i].length + 1); break; case 0xdd: /* ESC codes,about 284, vary lengths, IX centric */ code= get_mem(MEM_ROM, addr++); if (code == 0xcb) { immed_n = 2; addr++; // pass up immed data code= get_mem(MEM_ROM, addr++); i= 0; while ((code & disass_z80_ddcb[i].mask) != disass_z80_ddcb[i].code && disass_z80_ddcb[i].mnemonic) i++; dis_e = &disass_z80_ddcb[i]; b= disass_z80_ddcb[i].mnemonic; if (b != NULL) len += (disass_z80_ddcb[i].length + 2); } else { i= 0; while ((code & disass_z80_dd[i].mask) != disass_z80_dd[i].code && disass_z80_dd[i].mnemonic) i++; dis_e = &disass_z80_dd[i]; b= disass_z80_dd[i].mnemonic; if (b != NULL) len += (disass_z80_dd[i].length + 1); } break; case 0xfd: /* ESC codes,sme as dd but IY centric */ code= get_mem(MEM_ROM, addr++); if (code == 0xcb) { immed_n = 2; addr++; // pass up immed data code= get_mem(MEM_ROM, addr++); i= 0; while ((code & disass_z80_fdcb[i].mask) != disass_z80_fdcb[i].code && disass_z80_fdcb[i].mnemonic) i++; dis_e = &disass_z80_fdcb[i]; b= disass_z80_fdcb[i].mnemonic; if (b != NULL) len += (disass_z80_fdcb[i].length + 2); } else { i= 0; while ((code & disass_z80_fd[i].mask) != disass_z80_fd[i].code && disass_z80_fd[i].mnemonic) i++; dis_e = &disass_z80_fd[i]; b= disass_z80_fd[i].mnemonic; if (b != NULL) len += (disass_z80_fd[i].length + 1); } break; default: i= 0; while ((code & disass_z80[i].mask) != disass_z80[i].code && disass_z80[i].mnemonic) i++; dis_e = &disass_z80[i]; b= disass_z80[i].mnemonic; if (b != NULL) len += (disass_z80[i].length); break; } if (ret_branch) { *ret_branch = dis_e->branch; } if (immed_offset) { if (immed_n > 0) *immed_offset = immed_n; else *immed_offset = (addr - start_addr); } if (len == 0) len = 1; if (ret_len) *ret_len = len; return b;}char *cl_z80::disass(t_addr addr, char *sep){ char work[256], temp[20]; char *buf, *p, *b, *t; int len = 0; int immed_offset = 0; p= work; b = get_disasm_info(addr, &len, NULL, &immed_offset); if (b == NULL) {
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