inst_cb.cc

Small Device C Compiler 面向Inter8051

/*
 * Simulator of microcontrollers (inst.cc)
 *
 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
 * 
 * To contact author send email to [e-mail]
 *
 */

/* This file is part of microcontroller simulator: ucsim.

UCSIM is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

UCSIM is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with UCSIM; see the file COPYING.  If not, write to the Free
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
/*@1@*/

#include "ddconfig.h"

// local
#include "z80cl.h"
#include "regsz80.h"
#include "z80mac.h"

int
cl_z80::inst_cb_rlc(t_mem code)
{
  switch(code) {
    case 0x00: // RLC B
      rlc_byte(regs.bc.h);
    break;
    case 0x01: // RLC C
      rlc_byte(regs.bc.l);
    break;
    case 0x02: // RLC D
      rlc_byte(regs.de.h);
    break;
    case 0x03: // RLC E
      rlc_byte(regs.de.l);
    break;
    case 0x04: // RLC H
      rlc_byte(regs.hl.h);
    break;
    case 0x05: // RLC L
      rlc_byte(regs.hl.l);
    break;
    case 0x06: // RLC (HL)
      { unsigned char tmp;
        tmp = get1(regs.HL);
        rlc_byte(tmp);
        store1(regs.HL, tmp);
      }
    break;
    case 0x07: // RLC A
      rlc_byte(regs.A);
    break;
  }
  return(resGO);
}

int
cl_z80::inst_cb_rrc(t_mem code)
{
  switch(code) {
    case 0x08: // RRC B
      rrc_byte(regs.bc.h);
    break;
    case 0x09: // RRC C
      rrc_byte(regs.bc.l);
    break;
    case 0x0A: // RRC D
      rrc_byte(regs.de.h);
    break;
    case 0x0B: // RRC E
      rrc_byte(regs.de.l);
    break;
    case 0x0C: // RRC H
      rrc_byte(regs.hl.h);
    break;
    case 0x0D: // RRC L
      rrc_byte(regs.hl.l);
    break;
    case 0x0E: // RRC (HL)
      { unsigned char tmp;
        tmp = get1(regs.HL);
        rrc_byte(tmp);
        store1(regs.HL, tmp);
      }
    break;
    case 0x0F: // RRC A
      rrc_byte(regs.A);
    break;
  }
  return(resGO);
}

int
cl_z80::inst_cb_rl(t_mem code)
{
  switch(code) {
    case 0x10: // RL B
      rl_byte(regs.bc.h);
    break;
    case 0x11: // RL C
      rl_byte(regs.bc.l);
    break;
    case 0x12: // RL D
      rl_byte(regs.de.h);
    break;
    case 0x13: // RL E
      rl_byte(regs.de.l);
    break;
    case 0x14: // RL H
      rl_byte(regs.hl.h);
    break;
    case 0x15: // RL L
      rl_byte(regs.hl.l);
    break;
    case 0x16: // RL (HL)
      { unsigned char tmp;
        tmp = get1(regs.HL);
        rl_byte(tmp);
        store1(regs.HL, tmp);
      }
    break;
    case 0x17: // RL A
      rl_byte(regs.A);
    break;
  }
  return(resGO);
}

int
cl_z80::inst_cb_rr(t_mem code)
{
  switch(code) {
    case 0x18: // RR B
      rr_byte(regs.bc.h);
    break;
    case 0x19: // RR C
      rr_byte(regs.bc.l);
    break;
    case 0x1A: // RR D
      rr_byte(regs.de.h);
    break;
    case 0x1B: // RR E
      rr_byte(regs.de.l);
    break;
    case 0x1C: // RR H
      rr_byte(regs.hl.h);
    break;
    case 0x1D: // RR L
      rr_byte(regs.hl.l);
    break;
    case 0x1E: // RR (HL)
      { unsigned char tmp;
        tmp = get1(regs.HL);
        rr_byte(tmp);
        store1(regs.HL, tmp);
      }
    break;
    case 0x1F: // RR A
      rr_byte(regs.A);
    break;
  }
  return(resGO);
}

int
cl_z80::inst_cb_sla(t_mem code)
{
  switch(code) {
    case 0x20: // SLA B
      sla_byte(regs.bc.h);
    break;
    case 0x21: // SLA C
      sla_byte(regs.bc.l);
    break;
    case 0x22: // SLA D
      sla_byte(regs.de.h);
    break;
    case 0x23: // SLA E
      sla_byte(regs.de.l);
    break;
    case 0x24: // SLA H
      sla_byte(regs.hl.h);
    break;
    case 0x25: // SLA L
      sla_byte(regs.hl.l);
    break;
    case 0x26: // SLA (HL)
      { unsigned char tmp;
        tmp = get1(regs.HL);
        sla_byte(tmp);
        store1(regs.HL, tmp);
      }
    break;
    case 0x27: // SLA A
      sla_byte(regs.A);
    break;
  }
  return(resGO);
}

int
cl_z80::inst_cb_sra(t_mem code)
{
  switch(code) {
    case 0x28: // SRA B
      sra_byte(regs.bc.h);
    break;
    case 0x29: // SRA C
      sra_byte(regs.bc.l);
    break;
    case 0x2A: // SRA D
      sra_byte(regs.de.h);
    break;
    case 0x2B: // SRA E
      sra_byte(regs.de.l);
    break;
    case 0x2C: // SRA H
      sra_byte(regs.hl.h);
    break;
    case 0x2D: // SRA L
      sra_byte(regs.hl.l);
    break;
    case 0x2E: // SRA (HL)
      { unsigned char tmp;
        tmp = get1(regs.HL);
        sra_byte(tmp);
        store1(regs.HL, tmp);
      }
    break;
    case 0x2F: // SRA A
      sra_byte(regs.A);
    break;
  }
  return(resGO);
}

int
cl_z80::inst_cb_slia(t_mem code)
{
  switch(code) {
    case 0x30: // SLIA B	(Shift Left Inverted Arithmetic)
      slia_byte(regs.bc.h);
    break;
    case 0x31: // SLIA C	like SLA, but shifts in a 1 bit
      slia_byte(regs.bc.l);
    break;
    case 0x32: // SLIA D
      slia_byte(regs.de.h);
    break;
    case 0x33: // SLIA E
      slia_byte(regs.de.l);
    break;
    case 0x34: // SLIA H
      slia_byte(regs.hl.h);
    break;
    case 0x35: // SLIA L
      slia_byte(regs.hl.l);
    break;
    case 0x36: // SLIA (HL)
      { unsigned char tmp;
        tmp = get1(regs.HL);
        slia_byte(tmp);
        store1(regs.HL, tmp);
      }
    break;
    case 0x37: // SLIA A
      slia_byte(regs.A);
    break;
  }
  return(resGO);
}

int
cl_z80::inst_cb_srl(t_mem code)
{
  switch(code) {
    case 0x38: // SRL B
      srl_byte(regs.bc.h);
    break;
    case 0x39: // SRL C
      srl_byte(regs.bc.l);
    break;
    case 0x3A: // SRL D
      srl_byte(regs.de.h);
    break;
    case 0x3B: // SRL E
      srl_byte(regs.de.l);
    break;
    case 0x3C: // SRL H
      srl_byte(regs.hl.h);
    break;
    case 0x3D: // SRL L
      srl_byte(regs.hl.l);
    break;
    case 0x3E: // SRL (HL)
      { unsigned char tmp;
        tmp = get1(regs.HL);
        srl_byte(tmp);
        store1(regs.HL, tmp);
      }
    break;
    case 0x3F: // SRL A
      srl_byte(regs.A);
    break;
  }
  return(resGO);
}


int
cl_z80::inst_cb_bit(t_mem code)
{
#define bit_bitnum ((code >> 3) & 7)

  switch(code & 7) {
    case 0x0: // BIT x,B
      bit_byte(regs.bc.h, bit_bitnum); break;
    case 0x1: // BIT x,C
      bit_byte(regs.bc.l, bit_bitnum); break;
    case 0x2: // BIT x,D
      bit_byte(regs.de.h, bit_bitnum); break;
    case 0x3: // BIT x,E
      bit_byte(regs.de.l, bit_bitnum); break;
    case 0x4: // BIT x,H
      bit_byte(regs.hl.h, bit_bitnum); break;
    case 0x5: // BIT x,L
      bit_byte(regs.hl.l, bit_bitnum); break;
    case 0x6: // BIT x,(HL)
      { unsigned char tmp;
        tmp = get1(regs.HL);
        bit_byte(tmp, bit_bitnum);
        store1(regs.HL, tmp);
      }
    break;
    case 0x7: // BIT x,A
      bit_byte(regs.A, bit_bitnum); break;
    break;
  }
  return(resGO);