xa_sfr.cc

Small Device C Compiler 面向Inter8051

{CPU_XA, 0x400, "PSW"}, /* Program status word */
{CPU_XA, 0x400, "PSWL"}, /* Program status word (low byte) */
{CPU_XA, 0x401, "PSWH"}, /* Program status word (high byte) */
{CPU_XA, 0x402, "PSW51"}, /* 80C51 compatible PSW */
{CPU_XA, 0x403, "SSEL"}, /* Segment selection register */
{CPU_XA, 0x404, "PCON"}, /* Power control register */
{CPU_XA, 0x410, "TCON"}, /* Timer 0 and 1 control register */
{CPU_XA, 0x411, "TSTAT"}, /* Timer 0 and 1 extended status */
{CPU_XA, 0x418, "T2CON"}, /* Timer 2 control register */
{CPU_XA, 0x419, "T2MOD"}, /* Timer 2 mode control */
{CPU_XA, 0x41F, "WDCON"}, /* Watchdog control register */
{CPU_XA, 0x420, "S0CON"}, /* Serial port 0 control register */
{CPU_XA, 0x421, "S0STAT"}, /* Serial port 0 extended status */
{CPU_XA, 0x424, "S1CON"}, /* Serial port 1 control register */
{CPU_XA, 0x425, "S1STAT"}, /* Serial port 1 extended status */
{CPU_XA, 0x426, "IEL"}, /* Interrupt enable low byte */
{CPU_XA, 0x427, "IEH"}, /* Interrupt enable high byte */
{CPU_XA, 0x42A, "SWR"}, /* Software Interrupt Request */
{CPU_XA, 0x430, "P0"}, /* Port 0 */
{CPU_XA, 0x431, "P1"}, /* Port 1 */
{CPU_XA, 0x432, "P2"}, /* Port 2 */
{CPU_XA, 0x433, "P3"}, /* Port3 */
{CPU_XA, 0x440, "SCR"}, /* System configuration register */
{CPU_XA, 0x441, "DS"}, /* Data segment */
{CPU_XA, 0x442, "ES"}, /* Extra segment */
{CPU_XA, 0x443, "CS"}, /* Code segment */
{CPU_XA, 0x450, "TL0"}, /* Timer 0 low byte */
{CPU_XA, 0x451, "TH0"}, /* Timer 0 high byte */
{CPU_XA, 0x452, "TL1"}, /* Timer 1 low byte */
{CPU_XA, 0x453, "TH1"}, /* Timer 1 high byte */
{CPU_XA, 0x454, "RTL0"}, /* Timer 0 extended reload, low byte */
{CPU_XA, 0x455, "RTH0"}, /* Timer 0 extended reload, high byte */
{CPU_XA, 0x456, "RTL1"}, /* Timer 1 extended reload, low byte */
{CPU_XA, 0x457, "RTH1"}, /* Timer 1 extended reload, high byte */
{CPU_XA, 0x458, "TL2"}, /* Timer 2 low byte */
{CPU_XA, 0x459, "TH2"}, /* Timer 2 high byte */
{CPU_XA, 0x45A, "T2CAPL"}, /* Timer 2 capture register, low byte */
{CPU_XA, 0x45B, "T2CAPH"}, /* Timer 2 capture register, high byte */
{CPU_XA, 0x45C, "TMOD"}, /* Timer 0 and 1 mode register */
{CPU_XA, 0x45D, "WFEED1"}, /* Watchdog feed 1 */
{CPU_XA, 0x45E, "WFEED2"}, /* Watchdog feed 2 */
{CPU_XA, 0x45F, "WDL"}, /* Watchdog timer reload */
{CPU_XA, 0x460, "S0BUF"}, /* Serial port 0 buffer register */
{CPU_XA, 0x461, "S0ADDR"}, /* Serial port 0 address register */
{CPU_XA, 0x462, "S0ADEN"}, /* Serial port 0 address enable register */
{CPU_XA, 0x464, "S1BUF"}, /* Serial port 1 buffer register */
{CPU_XA, 0x465, "S1ADDR"}, /* Serial port 1 address register */
{CPU_XA, 0x466, "S1ADEN"}, /* Serial port 1 address enable register */
{CPU_XA, 0x468, "BTRL"}, /* Bus timing register high byte */
{CPU_XA, 0x469, "BTRH"}, /* Bus timing register low byte */
{CPU_XA, 0x46A, "BCR"}, /* Bus configuration register */
{CPU_XA, 0x470, "P0CFGA"}, /* Port 0 configuration A */
{CPU_XA, 0x471, "P1CFGA"}, /* Port 1 configuration A */
{CPU_XA, 0x472, "P2CFGA"}, /* Port 2 configuration A */
{CPU_XA, 0x473, "P3CFGA"}, /* Port 3 configuration A */
{CPU_XA, 0x47A, "SWE"}, /* Software Interrupt Enable */
{CPU_XA, 0x4A0, "IPA0"}, /* Interrupt priority 0 */
{CPU_XA, 0x4A1, "IPA1"}, /* Interrupt priority 1 */
{CPU_XA, 0x4A2, "IPA2"}, /* Interrupt priority 2 */
{CPU_XA, 0x4A4, "IPA4"}, /* Interrupt priority 4 */
{CPU_XA, 0x4A5, "IPA5"}, /* Interrupt priority 5 */
{CPU_XA, 0x4F0, "P0CFGB"}, /* Port 0 configuration B */
{CPU_XA, 0x4F1, "P1CFGB"}, /* Port 1 configuration B */
{CPU_XA, 0x4F2, "P2CFGB"}, /* Port 2 configuration B */
{CPU_XA, 0x4F3, "P3CFGB"}, /* Port 3 configuration B */