nv3.c

基于组件方式开发操作系统的OSKIT源代码

    PCRTC_Val(REPAINT1_LARGE_SCREEN,modetiming->CrtcHDisplay<1280) |
    PCRTC_Def(REPAINT1_PALETTE_WIDTH,6BITS);

  /* Need to figure out what the algorithm to set these are */
  moderegs[NV3REG_SAVE(5)]=0x83;/*PCRTC_Def(FIFO_CONTROL_BURST_LENGTH,64);*/
  moderegs[NV3REG_SAVE(6)]=0x22;/*PCRTC_Val(FIFO_WATERMARK,256>>3)|
                     PCRTC_Val(FIFO_RESET,1);*/


  /* PixelFormat controls how many bits per pixel. 
   * There is another register in the 
   * DAC which controls if mode is 5:5:5 or 5:6:5
   */
  pixelDepth=(modeinfo->bitsPerPixel+1)/8;
  if(pixelDepth>3) pixelDepth=3;
  moderegs[NV3REG_SAVE(3)]=pixelDepth;

  k=
     PRAMDAC_Def(GENERAL_CONTROL_IDC_MODE,GAMMA)|
     PRAMDAC_Val(GENERAL_CONTROL_565_MODE,modeinfo->greenWeight==6)|
     PRAMDAC_Def(GENERAL_CONTROL_TERMINATION,37OHM)|
     PRAMDAC_Def(GENERAL_CONTROL_BPC,6BITS)|  
     PRAMDAC_Def(GENERAL_CONTROL_VGA_STATE,SEL); /* Not sure about this */

if(modeinfo->bitsPerPixel>8)k|=PRAMDAC_Def(GENERAL_CONTROL_BPC,8BITS);

   moderegs[NV3REG_SAVE(20)] = k&0xff;
   moderegs[NV3REG_SAVE(21)] = (k >> 8)&0xff;
   moderegs[NV3REG_SAVE(22)] = (k >> 16) & 0xff ;
   moderegs[NV3REG_SAVE(23)] = ( k >> 24 ) & 0xff ;

  k=PRAMDAC_Def(PLL_COEFF_SELECT_MPLL_SOURCE,PROG)|
                            PRAMDAC_Def(PLL_COEFF_SELECT_VPLL_SOURCE,PROG)|
                            PRAMDAC_Def(PLL_COEFF_SELECT_VCLK_RATIO,DB2);
   moderegs[NV3REG_SAVE(16)] = k&0xff;
   moderegs[NV3REG_SAVE(17)] = (k >> 8)&0xff;
   moderegs[NV3REG_SAVE(18)] = (k >> 16) & 0xff ;
   moderegs[NV3REG_SAVE(19)] = ( k >> 24 ) & 0xff ;

  /* Disable Tetris tiling for now. This looks completely mad but could 
   * give some significant performance gains. Will perhaps experiment 
   * later on with this stuff!  
   */
  k=
      PFB_Val(CONFIG_0_RESOLUTION,((modeinfo->lineWidth+31)/32))|
      PFB_Val(CONFIG_0_PIXEL_DEPTH,pixelDepth)|
      PFB_Def(CONFIG_0_TILING,ENABLED); 
   moderegs[NV3REG_SAVE(8)] = k&0xff;
   moderegs[NV3REG_SAVE(9)] = (k >> 8)&0xff;
   moderegs[NV3REG_SAVE(10)] = (k >> 16) & 0xff ;
   moderegs[NV3REG_SAVE(11)] = ( k >> 24 ) & 0xff ;

moderegs[88]=28;

if(modeinfo->greenWeight==5){moderegs[NV3REG_SAVE(21)]&=0xef;}; 

nv3_is_linear=0;

return ;

}



static int nv3_setmode(int mode, int prv_mode)
{
    unsigned char *moderegs;
    ModeTiming *modetiming;
    ModeInfo *modeinfo;
    int i;
    if ((mode < G640x480x256 /*&& mode != G320x200x256*/)
	|| mode == G720x348x2) {
	return __svgalib_vga_driverspecs.setmode(mode, prv_mode);
    }

    if (!nv3_modeavailable(mode))
	return 1;

    modeinfo = __svgalib_createModeInfoStructureForSvgalibMode(mode);

    modetiming = malloc(sizeof(ModeTiming));
    if (__svgalib_getmodetiming(modetiming, modeinfo, cardspecs)) {
	free(modetiming);
	free(modeinfo);
	return 1;
    }

    moderegs = malloc(NV3_TOTAL_REGS);

    nv3_initializemode(moderegs, modetiming, modeinfo, mode);
    free(modetiming);

    __svgalib_setregs(moderegs);	/* Set standard regs. */
    nv3_setregs(moderegs, mode);	/* Set extended regs. */
    free(moderegs);

    __svgalib_InitializeAcceleratorInterface(modeinfo);

    for(i=0;i<256;i++)vga_setpalette(i,i,i,i);
    free(modeinfo);
    return 0;
}


/* Unlock chipset-specific registers */

static void nv3_unlock(void)
{
__svgalib_outSR(LOCK_EXT_INDEX,UNLOCK_EXT_MAGIC);    
}


/* Relock chipset-specific registers */
/* (currently not used) */

static void nv3_lock(void)
{
__svgalib_outSR(LOCK_EXT_INDEX,UNLOCK_EXT_MAGIC+1);    

}


/* Indentify chipset, initialize and return non-zero if detected */

static int nv3_test(void)
{  unsigned long buf[16];
   
   if (__svgalib_pci_find_vendor_vga(0x12d2,buf))return 0;
   if (((buf[0]>>16)&0xffff)!=0x18)return 0;
   MMIOBASE=buf[4]&0xffffff00;
   LINEARBASE=buf[5]&0xffffff00;
   nv3_init(0,0,0);
return 1;
}


/* No r/w paging - I guess it's possible, but is it useful? */
static void nv3_setrdpage(int page)
{
}
static void nv3_setwrpage(int page)
{
}


/* Set display start address (not for 16 color modes) */

static void nv3_setdisplaystart(int address)
{  unsigned char byte;
  inb(0x3da);
  outb(0x3c0,0x13);
  outb(0x3c0,(address&3) << 1);
  address = address << 2 ;
  outw(0x3d4, (address & 0x00FF00) | 0x0C);
  outw(0x3d4, ((address & 0x00FF) << 8) | 0x0D);

  byte=PCRTC_Read(REPAINT0) & 0xf0;
  PCRTC_Write(REPAINT0,(address&0x0f)|byte);

}


/* Set logical scanline length (usually multiple of 8) */
/* Cirrus supports multiples of 8, up to 4088 */

static void nv3_setlogicalwidth(int width)
{
}

static int nv3_linear(int op, int param)
{
if (op==LINEAR_ENABLE || op==LINEAR_DISABLE){ nv3_is_linear=1-nv3_is_linear; return 0;}
if (op==LINEAR_QUERY_BASE) { return LINEARBASE ;}
if (op == LINEAR_QUERY_RANGE || op == LINEAR_QUERY_GRANULARITY) return 0;		/* No granularity or range. */
    else return -1;		/* Unknown function. */
}

static int nv3_match_programmable_clock(int clock)
{
return clock ;
}
static int nv3_map_clock(int bpp, int clock)
{
return clock ;
}
static int nv3_map_horizontal_crtc(int bpp, int pixelclock, int htiming)
{
return htiming;
}
/* Function table (exported) */

DriverSpecs __svgalib_nv3_driverspecs =
{
    nv3_saveregs,
    nv3_setregs,
    nv3_unlock,
    nv3_lock,
    nv3_test,
    nv3_init,
    nv3_setpage,
    nv3_setrdpage,
    nv3_setwrpage,
    nv3_setmode,
    nv3_modeavailable,
    nv3_setdisplaystart,
    nv3_setlogicalwidth,
    nv3_getmodeinfo,
    0,				/* old blit funcs */
    0,
    0,
    0,
    0,
    0,				/* ext_set */
    0,				/* accel */
    nv3_linear,
    0				/* accelspecs, filled in during init. */
};

#ifdef OSKIT
#define MapDevice(device,base) \
    osenv_mem_map_phys((MMIOBASE)+DEVICE_BASE(device), DEVICE_SIZE(device), \
	&nv##device##Port, 0)
#else
#define MapDevice(device,base) \
  nv##device##Port=(unsigned*)(mmap(0, \
     	DEVICE_SIZE(device),PROT_WRITE,MAP_SHARED,__svgalib_mem_fd,\
        (MMIOBASE)+DEVICE_BASE(device)))
#endif

/* Initialize chipset (called after detection) */

static int nv3_init(int force, int par1, int par2)
{   nv3_unlock();
    if (force) {
	nv3_memory = par1;
	nv3_chiptype = par2;
    };
    MapDevice(PRAMDAC,regBase);
    MapDevice(PFB,regBase);
        
    if(!force){
       nv3_memory=1024<<(PFB_Read(BOOT_0)&3); 
       nv3_chiptype=0;
    };
    if (__svgalib_driver_report) {
	printf("Using RIVA 128 driver, %iKB.\n",nv3_memory);
    };
    cardspecs = malloc(sizeof(CardSpecs));
    cardspecs->videoMemory = nv3_memory;
    cardspecs->maxPixelClock4bpp = 75000;	
    cardspecs->maxPixelClock8bpp = 230000;	
    cardspecs->maxPixelClock16bpp = 230000;	
    cardspecs->maxPixelClock24bpp = 230000;
    cardspecs->maxPixelClock32bpp = 230000;
    cardspecs->flags = (CLOCK_PROGRAMMABLE | INTERLACE_DIVIDE_VERT | GREATER_1024_DIVIDE_VERT);
    cardspecs->maxHorizontalCrtc = 2040;
    cardspecs->maxPixelClock4bpp = 0;
    cardspecs->nClocks =0;
    cardspecs->clocks = NULL;
    cardspecs->mapClock = nv3_map_clock;
    cardspecs->mapHorizontalCrtc = nv3_map_horizontal_crtc;
    cardspecs->matchProgrammableClock=nv3_match_programmable_clock;
    __svgalib_driverspecs = &__svgalib_nv3_driverspecs;
    return 0;
}

static int NV3ClockSelect(float clockIn,float *clockOut,int *mOut,
                                        int *nOut,int *pOut)
{ 
  int m,n,p;
  float bestDiff=1e10;
  float target=0.0;
  float best=0.0;
  float diff;
  int nMax,nMin;
  
  *clockOut=0.0;
  for(p=P_MIN;p<=P_MAX;p++) {
    for(m=M_MIN;m<=M_MAX;m++) {
      float fm=(float)m;
      /* Now calculate maximum and minimum values for n */
      nMax=(int) (((256000/PLL_INPUT_FREQ)*fm)-0.5);
      nMin=(int) (((128000/PLL_INPUT_FREQ)*fm)+0.5);
      n=(int)(((clockIn*((float)(1<<p)))/PLL_INPUT_FREQ)*fm);
      if(n>=nMin && n<=nMax) {  
        float fn=(float)n;
        target=(PLL_INPUT_FREQ*(fn/fm))/((float)(1<<p));
        diff=fabs(target-clockIn);
        if(diff<bestDiff) {
          bestDiff=diff;
          best=target;
          *mOut=m;*nOut=n;*pOut=p;
          *clockOut=best;
	}
      }
    }
  }
  return (best!=0.0);    
}