mach64.c

基于组件方式开发操作系统的OSKIT源代码

	case BPP_4:
	default:
	    break;
	}
	FreqCDT1[j].h_disp = 0;
    }
    /* table 2 */
    for (i = 0, j = 0; MaxCDT2[i].h_disp != 0; i++) {
	/* pick out 8 bpp modes for now */
	switch (MaxCDT2[i].color_depth) {
	case BPP_8:
	    if ((MaxCDT2[i].ram_req >> mask) >
		StartupInfo.Mem_Size)
		break;

	    FreqCDT2[j].h_disp = MaxCDT2[i].h_disp;
	    FreqCDT2[j].dacmask = MaxCDT2[i].dacmask;
	    FreqCDT2[j].ram_req = MaxCDT2[i].ram_req;
	    FreqCDT2[j].max_dot_clk = MaxCDT2[i].max_dot_clk;
	    FreqCDT2[j].color_depth = MaxCDT2[i].color_depth;
	    j++;
	    break;
	case BPP_32:
	case BPP_16:
	case BPP_15:
	case BPP_4:
	default:
	    break;
	}
	FreqCDT2[j].h_disp = 0;
    }

#ifdef REPORT_CLKTAB
    fprintf(stdout, "Color Depth Table 1\n");
    for (i = 0; MaxCDT1[i].h_disp != 0; i++) {
	fprintf(stdout, "%d %d %d %d %d\n", MaxCDT1[i].h_disp,
		MaxCDT1[i].dacmask, MaxCDT1[i].ram_req,
		MaxCDT1[i].max_dot_clk, MaxCDT1[i].color_depth);
    }
    fprintf(stdout, "Color Depth Table 2 - if present\n");
    for (i = 0; MaxCDT2[i].h_disp != 0; i++) {
	fprintf(stdout, "%d %d %d %d %d\n", MaxCDT2[i].h_disp,
		MaxCDT2[i].dacmask, MaxCDT2[i].ram_req,
		MaxCDT2[i].max_dot_clk, MaxCDT2[i].color_depth);
    }
#endif
#ifdef REPORT
    fprintf(stdout, "Valid Color Depth Table 1\n");
    for (i = 0; FreqCDT1[i].h_disp != 0; i++) {
#ifdef REPORT_CLKTAB
	fprintf(stdout, "%d %d %d %d %d\n", FreqCDT1[i].h_disp,
		FreqCDT1[i].dacmask, FreqCDT1[i].ram_req,
		FreqCDT1[i].max_dot_clk, FreqCDT1[i].color_depth);
#endif
	fprintf(stdout, "Width: %d, MaxDotClk: %dMHz, Depth: %d bpp\n",
		FreqCDT1[i].h_disp * 8, FreqCDT1[i].max_dot_clk,
		M64_BPP[FreqCDT1[i].color_depth]);
    }
    fprintf(stdout, "Valid Color Depth Table 2 - if present\n");
    for (i = 0; FreqCDT2[i].h_disp != 0; i++) {
#ifdef REPORT_CLKTAB
	fprintf(stdout, "%d %d %d %d %d\n", FreqCDT2[i].h_disp,
		FreqCDT2[i].dacmask, FreqCDT2[i].ram_req,
		FreqCDT2[i].max_dot_clk, FreqCDT2[i].color_depth);
#endif
	fprintf(stdout, "Width: %d, MaxDotClk: %dMHz, Depth: %d bpp\n",
		FreqCDT2[i].h_disp * 8, FreqCDT2[i].max_dot_clk,
		M64_BPP[FreqCDT2[i].color_depth]);
    }
#endif
}

/*************************************************************************/

/* generates a quick register dump */
static void mach64_report(void)
{
    UL reg;

    reg = inl(ioBUS_CNTL);
    printf("BUS_CNTL: %lx ", reg);
    DUMP(reg);

    reg = inl(ioCONFIG_CHIP_ID);
    printf("CONFIG_CHIP_ID: %lx ", reg);
    DUMP(reg);


    reg = inl(ioCONFIG_CNTL);
    printf("CONFIG_CNTL: %lx ", reg);
    DUMP(reg);

    reg = inl(ioCONFIG_STAT0);
    printf("CONFIG_STAT0: %lx ", reg);
    DUMP(reg);

    reg = inl(ioCONFIG_STAT1);
    printf("CONFIG_STAT1: %lx ", reg);
    DUMP(reg);

    reg = inl(ioGEN_TEST_CNTL);
    printf("GEN_TEST_CNTL: %lx ", reg);
    DUMP(reg);

    reg = inl(ioMEM_CNTL);
    printf("MEM_CNTL: %lx ", reg);
    DUMP(reg);

    reg = inl(ioMEM_VGA_RP_SEL);
    printf("MEM_VGA_RP_SEL: %lx ", reg);
    DUMP(reg);

    reg = inl(ioMEM_VGA_WP_SEL);
    printf("MEM_VGA_WP_SEL: %lx ", reg);
    DUMP(reg);

    reg = inl(ioDAC_CNTL);
    printf("DAC_CNTL: %lx ", reg);
    DUMP(reg);

    reg = inl(ioCLOCK_SEL_CNTL);
    printf("CLOCK_CNTL: %lx ", reg);
    DUMP(reg);

    reg = inl(ioCRTC_GEN_CNTL);
    printf("CRTC_GEN: %lx ", reg);
    DUMP(reg);

    reg = inl(ioSCRATCH_REG0);
    printf("SCRATCH 0: %lx ", reg);
    DUMP(reg);

    reg = inl(ioSCRATCH_REG1);
    printf("SCRATCH 1: %lx ", reg);
    DUMP(reg);

    reg = inl(ioCRTC_H_SYNC_STRT_WID);
    printf("H_S_S_W: %lx ", reg);
    DUMP(reg);
}

/*************************************************************************/

/* program the ati68860 ramdac -- standard on old mach64's */
static int mach64_dac_ati68860(US c_depth, US accelmode)
{
    US gmode, dsetup, temp, mask;

    /* filter pixel depth */
    if (c_depth == BPP_8) {
	gmode = 0x83;
	dsetup = 0x61;
    } else {
	printf("unsupported bpp\n");
	exit(1);
    }

    /* if we are in vga mode */
    if (!accelmode) {
	gmode = 0x80;
	dsetup = 0x60;
    }
    temp = inb(ioDAC_CNTL);
    outb(ioDAC_CNTL, (temp & ~DAC_EXT_SEL_RS2) | DAC_EXT_SEL_RS3);

    outb(ioDAC_REGS + 2, 0x1d);
    outb(ioDAC_REGS + 3, gmode);
    outb(ioDAC_REGS, 0x02);

    temp = inb(ioDAC_CNTL);
    outb(ioDAC_CNTL, temp | DAC_EXT_SEL_RS2 | DAC_EXT_SEL_RS3);

    if (M64_Mem_Size[StartupInfo.Mem_Size] < 1024)
	mask = 0x04;
    else if (M64_Mem_Size[StartupInfo.Mem_Size] == 1024)
	mask = 0x08;
    else
	mask = 0x0c;

    temp = inb(ioDAC_REGS);
    outb(ioDAC_REGS, (dsetup | mask) | (temp & 0x80));
    temp = inb(ioDAC_CNTL);
    outb(ioDAC_CNTL, (temp & ~(DAC_EXT_SEL_RS2 | DAC_EXT_SEL_RS3)));

    /* pixel delay from ati */
    temp = inb(ioCRTC_H_SYNC_STRT_WID + 1);
    temp = 0x1c;		/*was temp+= */
    outb(ioCRTC_H_SYNC_STRT_WID + 1, temp & 0x07);
    temp >>= 3;
    temp = temp + inb(ioCRTC_H_SYNC_STRT_WID);
    outb(ioCRTC_H_SYNC_STRT_WID, temp);

    return 0;
}

/* general ramdac program */
static void mach64_dac_program(US c_depth, US accelmode, US dotclock)
{
    US temp, mux;

    /* check to see if we are using an accelerator mode and turn on
       the extended mode display and crtc */
    if (accelmode) {
	temp = inb(CRTC_GEN_CNTL) & ~CRTC_PIX_BY_2_EN;
	outb(ioCRTC_GEN_CNTL, temp);
	outb(ioCRTC_GEN_CNTL + 3, CRTC_EXT_DISP_EN | CRTC_EXT_EN);
    } else {
	outb(ioCRTC_GEN_CNTL + 3, 0);
    }

    temp = inb(ioCRTC_GEN_CNTL + 3);
    outb(ioCRTC_GEN_CNTL + 3, temp | CRTC_EXT_DISP_EN);

    /* switch on the dac type */
    mux = mach64_dac_ati68860(c_depth, accelmode);

    inb(ioDAC_REGS);
    outb(ioCRTC_GEN_CNTL + 3, temp);

    temp = inb(ioCRTC_GEN_CNTL) & ~CRTC_PIX_BY_2_EN;
    if (mux)
	temp = temp | CRTC_PIX_BY_2_EN;
    outb(ioCRTC_GEN_CNTL, temp);
}

/* setup the crtc registers */
static void mach64_crtc_programming(US mode, US c_depth, US refrate)
{
    CRTC_Table *pcrtc;
    UB temp3, temp0;

    /* fix to mode 640x480 */
    pcrtc = &CRTC_tinfo[0];

    /* determine the fifo value and dot clock */
    pcrtc->fifo_vl = 0x02;
    pcrtc->pdot_clock = pcrtc->dot_clock;

    temp3 = inb(ioCRTC_GEN_CNTL + 3);
    temp0 = inb(ioCRTC_GEN_CNTL + 0);
    outb(ioCRTC_GEN_CNTL + 3, temp3 & ~CRTC_EXT_EN);

    /* here would would program the clock... but we won't */

    /* horizontal */
    outb(CRTC_H_TOTAL, pcrtc->h_total);
    outb(CRTC_H_DISP, pcrtc->h_disp);
    outb(CRTC_H_SYNC_STRT, pcrtc->h_sync_strt);
    outb(CRTC_H_SYNC_WID, pcrtc->h_sync_wid);

    printf("CRTC_H_TD: %x\n", inl(ioCRTC_H_TOTAL_DISP));
    printf("CRTC_H_SN: %x\n", inl(ioCRTC_H_SYNC_STRT_WID));

    /* vertical */
    outw(CRTC_V_TOTAL, pcrtc->v_total);
    outw(CRTC_V_DISP, pcrtc->v_disp);
    outw(CRTC_V_SYNC_STRT, pcrtc->v_sync_strt);
    outb(CRTC_V_SYNC_WID, pcrtc->v_sync_wid);

    printf("CRTC_V_TD: %lx\n", (UL) inl(ioCRTC_V_TOTAL_DISP));
    printf("CRTC_V_SN: %lx\n", (UL) inl(ioCRTC_V_SYNC_STRT_WID));

    /* clock stuff */
    /* 50/2 */
    pcrtc->clock_cntl = 0x00 | 0x10;
    /* CX clock */
    pcrtc->clock_cntl = 0x08;
    /*outb(CLOCK_CNTL,pcrtc->clock_cntl|CLOCK_STROBE); */
    outb(CLOCK_CNTL, pcrtc->clock_cntl);
    printf("CLK: %lx\n", (UL) inl(ioCLOCK_SEL_CNTL));

    /* overscan */
    outb(OVR_WID_LEFT, 0);
    outb(OVR_WID_RIGHT, 0);
    outb(OVR_WID_BOTTOM, 0);
    outb(OVR_WID_TOP, 0);
    outb(OVR_CLR_8, 0);
    outb(OVR_CLR_B, 0);
    outb(OVR_CLR_G, 0);
    outb(OVR_CLR_R, 0);

    /* pitch */
    outl(ioCRTC_OFF_PITCH, (UL) 80 << 22);
    mreg[mSRC_OFF_PITCH / 4 + 0xC00 / 4] = (UL) 80 << 22;
    mreg[mDST_OFF_PITCH / 4 + 0xC00 / 4] = (UL) 80 << 22;

    /* turn on display */
    outb(ioCRTC_GEN_CNTL + 0, temp0 &
	 ~(CRTC_PIX_BY_2_EN | CRTC_DBL_SCAN_EN | CRTC_INTERLACE_EN));
    outb(ioCRTC_GEN_CNTL + 1, c_depth);
    outb(ioCRTC_GEN_CNTL + 2, pcrtc->fifo_vl);
    outb(ioCRTC_GEN_CNTL + 3, temp3 | CRTC_EXT_DISP_EN | CRTC_EXT_EN);

    mreg[mDP_PIX_WIDTH / 4 + 0xC00 / 4] = (UL) 0x01020202;
    mreg[mDP_CHAIN_MASK / 4 + 0xC00 / 4] = (UL) 0x8080;
    mreg[mCONTEXT_MASK / 4 + 0xC00 / 4] = (UL) 0xffffffff;
    /* woudn't a macro be nice */
    mreg[mDST_CNTL / 4 + 0xC00 / 4] = (UL) 0x00;

    printf("CRTC_GEN_IN_CRTC: %x\n", inl(ioCRTC_GEN_CNTL));
    /* configure ramdac */
    mach64_dac_program(c_depth, 1, pcrtc->pdot_clock);

    mach64_report();
}

/*************************************************************************/
static int mach64_saveregs(UB * regs)
{
    int i, retval;
    UL temp;
    UB tb;

    /* store all the crtc, clock, memory registers */
    retval = EXT;
    for (i = 0; i < 13; i++) {
	temp = inl(sr_accel[i]);
	printf("Saved: %d %lx\n", i, temp);
	regs[retval++] = (UB) temp & 0x000000ff;
	temp = temp >> 8;
	regs[retval++] = (UB) temp & 0x000000ff;
	temp = temp >> 8;
	regs[retval++] = (UB) temp & 0x000000ff;
	temp = temp >> 8;
	regs[retval++] = (UB) temp & 0x000000ff;

    }

    /* store the dac --68860 */
    tb = inb(ioDAC_CNTL);
    outb(ioDAC_CNTL, (tb & ~DAC_EXT_SEL_RS2) | DAC_EXT_SEL_RS3);
    regs[retval++] = (UB) inb(ioDAC_REGS + 2);
    regs[retval++] = (UB) inb(ioDAC_REGS + 3);
    regs[retval++] = (UB) inb(ioDAC_REGS);
    tb = inb(ioDAC_CNTL);
    outb(ioDAC_CNTL, tb | DAC_EXT_SEL_RS2 | DAC_EXT_SEL_RS3);
    regs[retval++] = (UB) inb(ioDAC_REGS);
    tb = inb(ioDAC_CNTL);
    outb(ioDAC_CNTL, (tb & ~(DAC_EXT_SEL_RS2 | DAC_EXT_SEL_RS3)));

    return retval - EXT + 1;
}

static void mach64_setregs(const UB * regs, int mode)
{
    int i, retval;
    UL temp;
    UB tb;

    outb(0x3ce, 6);
    outb(0x3cf, 0);
    outb(ioCONFIG_CNTL, (inb(ioCONFIG_CNTL) & 0xfb));
    outb(ioCRTC_GEN_CNTL + 3, 0);

    return;
    /* restore all the crtc, clock, memory registers */
    retval = EXT;
    for (i = 0; i < 13; i++) {
	temp = (UL) 0;
	temp = temp | (regs[retval++] << 24);
	temp = temp | (regs[retval++] << 16);
	temp = temp | (regs[retval++] << 8);
	temp = temp | regs[retval++];
	outl(sr_accel[i], temp);

    }

    /* store the dac --68860 */
    tb = inb(ioDAC_CNTL);
    outb(ioDAC_CNTL, (tb & ~DAC_EXT_SEL_RS2) | DAC_EXT_SEL_RS3);
    outb(ioDAC_REGS + 2, regs[retval++]);
    outb(ioDAC_REGS + 3, regs[retval++]);
    outb(ioDAC_REGS, regs[retval++]);
    tb = inb(ioDAC_CNTL);
    outb(ioDAC_CNTL, tb | DAC_EXT_SEL_RS2 | DAC_EXT_SEL_RS3);
    outb(ioDAC_REGS, regs[retval++]);
    tb = inb(ioDAC_CNTL);
    outb(ioDAC_CNTL, (tb & ~(DAC_EXT_SEL_RS2 | DAC_EXT_SEL_RS3)));

}

static void mach64_getmodeinfo(int mode, vga_modeinfo * modeinfo)
{
    /*__svgalib_vga_driverspecs.getmodeinfo(mode, modeinfo); */
    modeinfo->startaddressrange = 0xfffff;
/*      modeinfo->startaddressrange=0xfffffffc&(2048*1024-1);
 */

    modeinfo->maxpixels = 640 * 480;
/*      modeinfo->bytesperpixel=infotable[mode].bytesperpixel;
   modeinfo->linewidth_unit=8;
   modeinfo->linewidth=infotable[mode].xbytes;
   modeinfo->maxlogicalwidth=0xff*8*modeinfo->bytesperpixel;
   modeinfo->startaddressrange=0xffc00000;
 */
}

static int mach64_modeavailable(int mode)
{
/*
   if (mode>__svgalib_max_modes)
 */
    if (mode > __GLASTMODE)
	return 0;
    if (mode < G640x480x256 || mode == G720x348x2)
	return __svgalib_vga_driverspecs.modeavailable(mode);
    else if (mode != G640x480x256)
	return 0;

    return SVGADRV;
}

static int mach64_setmode(int mode, int prv_mode)
{
    const UB *regs = NULL;
    UB di;

    mach64_setregs(regs, mode);

    if (mode < G640x480x256 || mode == G720x348x2)
	return __svgalib_vga_driverspecs.setmode(mode, prv_mode);

    if (mode == G640x480x256) {

	/* I don't think this is necessary since I dont even
	   use the vga */
	/* set packed pixel register */
	outb(ATIPORT, ATISEL(0x30));
	di = inb(ATIPORT);
	printf("pre ext: %d\n", di);
	outb(ATIPORT, ATISEL(0x30));
	outb(ATIPORT, di | 0x20);

	/* all maps */
	outb(0x3c4, 2);
	outb(0x3c5, 0x0f);

	/* linear */
	outb(ATIPORT, ATISEL(0x36));
	di = inb(ATIPORT);
	outb(ATIPORT, ATISEL(0x36));
	outb(ATIPORT, di | 0x04);

	/* turn off memory boundary */
	outl(ioMEM_CNTL, inl(ioMEM_CNTL) & 0xfff8ffff);

	/* disable interrups */
	outl(ioCRTC_INT_CNTL, 0);

	/* 8 bit dac */
	outb(ioDAC_CNTL + 1, inb(ioDAC_CNTL + 1) | 0x01);
	outb(ioCRTC_GEN_CNTL + 3, 3);
	/* setup small aperature */
	mach64_small_aperature();


	mach64_setpage(0);
#ifdef DEBUG
	printf("About to call crtc programming...\n");
#endif
	mach64_crtc_programming(0, BPP_8, 60);
	di = 0;
/*              for (di=0;di<32;di++){ 
   mach64_setpage(di);usleep(10000);
   for (i=0;i<64*1024;i++){
   graph_mem[i]=i%16;}
   }
	 *//*            for (j=0;j<1024*2048/8;j+=640){
	   usleep(1);
	   outw(ioCRTC_OFF_PITCH,j/8);
	   }  
	 *//*            outw(ioCRTC_OFF_PITCH,4000);
	   outb(ioCRTC_OFF_PITCH+2,inb(ioCRTC_OFF_PITCH+2)|0x10);
	   outw(ioCRTC_OFF_PITCH,80*480);
	 */ outw(ioCRTC_OFF_PITCH, 0);
	mach64_setpage(0);
/*              for(j=0;j<64000;j++){
   graph_mem[j]=0x0c;
   }
   sleep(2);
 */ mach64_setpage(0);
	mach64_report();
	return 0;
    }
    return 1;


}

static void mach64_setdisplaystart(int address)
{
    /*__svgalib_vga_driverspecs.setdisplaystart(address); */
}

static void mach64_setlogicalwidth(int width)
{
    /*__svgalib_vga_driverspecs.setlogicalwidth(width); */
}

static void mach64_setpage(int page)
{
    printf("PAGE: %d\n", page);
    outb(ioMEM_VGA_WP_SEL, 255 - (page * 2));
    outb(ioMEM_VGA_WP_SEL + 2, 255 - ((page * 2) + 1));
    outb(ioMEM_VGA_RP_SEL, 255 - (page * 2));
    outb(ioMEM_VGA_RP_SEL + 2, 255 - ((page * 2) + 1));
}

static void mach64_small_aperature(void)
{
    int i;

    /* 256 color mode */
    outb(0x3ce, 5);
    printf("pre 5:%d\n", inb(0x3cf));
    outb(0x3ce, 5);
    outb(0x3cf, 0x60);
    outb(0x3ce, 5);
    printf("afe 5:%d\n", inb(0x3cf));
    /* APA mode with 128K at A0000 */
    outb(0x3ce, 6);
    printf("pre 6:%d\n", inb(0x3cf));
    outb(0x3ce, 6);
    outb(0x3cf, 1);
    outb(0x3ce, 6);
    printf("afe 6:%d\n", inb(0x3cf));

    /* setup small aperature */
    outb(ioCONFIG_CNTL, (inb(ioCONFIG_CNTL) | 0x04) & 0xff);
    /* map ram */
#ifdef OSKIT
    { 
	void *tmp;
	osenv_mem_map_phys(0xbf000, 4 * 1024, &tmp, 0);
    }
#else
    mreg = (UL *) mmap((caddr_t) 0,
		       4 * 1024,
		       PROT_READ | PROT_WRITE,
		       MAP_SHARED | MAP_FIXED,
		       __svgalib_mem_fd,
		       (off_t) ((UB *) 0xbf000));
#endif
    if (mreg < 0) {
	printf("Mapping failed\n");
	exit(1);
    }
    printf("IOPORT: %x\n", inl(ioCONFIG_STAT0));
    for (i = 0; i <= 0xce; i++) {
	printf("MEMA: %x %lx\n", i, mreg[i + 0xc00 / 4]);
    }
}