📄 apm.c
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break;case 11:moderegs[0x16]+=31;break;case 12:moderegs[0x16]+=25;break;case 39:moderegs[0x16]+=28;break;}*/moderegs[0x16]=moderegs[6]+1;} moderegs[APMREG_SAVE(10)] = 0xe8; moderegs[APMREG_SAVE(11)] = 0x01; moderegs[APMREG_SAVE(12)] = 0x1f; moderegs[APMREG_SAVE(13)] = 0x07; /* new->XRE8 = RDXL_IOP(0xe8); */apm_is_linear=0;return ;}static int apm_setmode(int mode, int prv_mode){ unsigned char *moderegs; ModeTiming *modetiming; ModeInfo *modeinfo; if ((mode < G640x480x256 /*&& mode != G320x200x256*/) || mode == G720x348x2) {/* __svgalib_clear_accelspecs(__svgalib_driverspecs->accelspecs);*/ /* Let the standard VGA driver set standard VGA modes */ /* But first reset an Cirrus extended register that */ /* an old XFree86 Trident probe corrupts. */ return __svgalib_vga_driverspecs.setmode(mode, prv_mode); } if (!apm_modeavailable(mode)) return 1; modeinfo = __svgalib_createModeInfoStructureForSvgalibMode(mode); modetiming = malloc(sizeof(ModeTiming)); if (__svgalib_getmodetiming(modetiming, modeinfo, cardspecs)) { free(modetiming); free(modeinfo); return 1; } moderegs = malloc(APM_TOTAL_REGS); apm_initializemode(moderegs, modetiming, modeinfo, mode); free(modetiming); __svgalib_setregs(moderegs); /* Set standard regs. */ apm_setregs(moderegs, mode); /* Set extended regs. */ free(moderegs); __svgalib_InitializeAcceleratorInterface(modeinfo); free(modeinfo); return 0;}/* Unlock chipset-specific registers */static void apm_unlock(void){ int vgaIOBase, temp; vgaIOBase = (inb(0x3CC) & 0x01) ? 0x3D0 : 0x3B0; outb(vgaIOBase + 4, 0x11); temp = inb(vgaIOBase + 5); outb(vgaIOBase + 5, temp & 0x7F); __svgalib_outSR(0x10, 0x12);}/* Relock chipset-specific registers *//* (currently not used) */static void apm_lock(void){}/* Indentify chipset, initialize and return non-zero if detected */static int apm_test(void){ int i; int oldSEQ10;#if 0 char id_ap6420[] = "Pro6420"; char id_ap6422[] = "Pro6422"; char id_at24[] = "Pro6424";#endif char id_at3d[] = "ProAT3D"; /* Yeah, the manual could have been correct... */ char idstring[] = " "; if ((getenv("IOPERM") == NULL) && (iopl(3) < 0)) { printf("svgalib(apm): Cannot get I/O permissions.\n"); exit(-1); } /* * Warning! A fully compliant VGA will most probably interprete this as * __svgalib_outbSR(0x00, 0x02), hence stop the sequencer, to play safe * we keep the old setting. */ oldSEQ10 = __svgalib_inSR(0x10); __svgalib_outSR(0x10, 0x12); for (i = 0; i < 7; i++) idstring[i] = __svgalib_inSR(0x11+i); /* reset iopl, apm_init will raise it again */ if (getenv("IOPERM") == NULL) iopl(0); /* * Just in case, restore any old setting & select SEQ00: */ __svgalib_outSR(0x10, oldSEQ10); __svgalib_inSR(0); if (!memcmp(id_at3d, idstring, 7)) { apm_init(0,0,0) ; return 1; } return 0;}/* No r/w paging */static void apm_setrdpage(int page){}static void apm_setwrpage(int page){}/* Set display start address (not for 16 color modes) *//* Cirrus supports any address in video memory (up to 2Mb) */static void apm_setdisplaystart(int address){ int i; outw(0x3d4, (address & 0x00FF00) | 0x0C); outw(0x3d4, ((address & 0x00FF) << 8) | 0x0D); /* * Here the high-order bits are masked and shifted, and put into * the appropriate extended registers. */ outb(0x3d4,0x1c); i=(inb(0x3d5)&0xf0)|((address & 0x0f0000) >> 16); __svgalib_outCR(0x1c,i);/* modinx(vgaIOBase + 4, 0x1c, 0x0f, (address & 0x0f0000) >> 16); */}/* Set logical scanline length (usually multiple of 8) *//* Cirrus supports multiples of 8, up to 4088 */static void apm_setlogicalwidth(int width){}static int apm_linear(int op, int param){if (op==LINEAR_ENABLE || op==LINEAR_DISABLE){ apm_is_linear=1-apm_is_linear; return 0;}if (op==LINEAR_QUERY_BASE) {__svgalib_outSR(0x1d,0x193>>2); return inb(apm_xbase+3)<<24 ;}if (op == LINEAR_QUERY_RANGE || op == LINEAR_QUERY_GRANULARITY) return 0; /* No granularity or range. */ else return -1; /* Unknown function. */}static int apm_match_programmable_clock(int clock){return clock ;}static int apm_map_clock(int bpp, int clock){return clock ;}static int apm_map_horizontal_crtc(int bpp, int pixelclock, int htiming){return htiming;}/* Function table (exported) */DriverSpecs __svgalib_apm_driverspecs ={ apm_saveregs, apm_setregs, apm_unlock, apm_lock, apm_test, apm_init, apm_setpage, apm_setrdpage, apm_setwrpage, apm_setmode, apm_modeavailable, apm_setdisplaystart, apm_setlogicalwidth, apm_getmodeinfo, 0, /* old blit funcs */ 0, 0, 0, 0, 0, /* ext_set */ 0, /* accel */ apm_linear, 0, /* accelspecs, filled in during init. */ NULL, /* Emulation */};/* Initialize chipset (called after detection) */static int apm_init(int force, int par1, int par2){ /* Get I/O priviledge */ if ((getenv("IOPERM") == NULL) && (iopl(3) < 0)) { printf("svgalib(apm): Cannot get I/O permissions.\n"); exit(-1); } apm_unlock(); if (force) { apm_memory = par1; apm_chiptype = par2; } else { int i; char id_ap6420[] = "Pro6420"; char id_ap6422[] = "Pro6422"; char id_at24[] = "Pro6424"; char id_at3d[] = "ProAT3D"; /* Yeah, the manual could have been correct... */ char idstring[] = " "; __svgalib_outSR(0x10, 0x12); for (i = 0; i < 7; i++) idstring[i] = __svgalib_inSR(0x11+i); if (!memcmp(id_ap6420, idstring, 7)) { apm_chiptype=0; return 1; } else if (!memcmp(id_ap6422, idstring, 7)) { apm_chiptype=1; return 1; } else if (!memcmp(id_at24, idstring, 7)) { apm_chiptype=2; return 1; } else if (!memcmp(id_at3d, idstring, 7)) { apm_chiptype=3; } /*else return 1;*/ apm_memory=__svgalib_inSR(0x20)*64-34; /* maybe will support accel some day */ }; if (__svgalib_driver_report) { printf("Using AT3d driver, %iKB.\n",apm_memory); } apm_xbase= (__svgalib_inSR(0x1f) << 8 ) + __svgalib_inSR(0x1e); cardspecs = malloc(sizeof(CardSpecs)); cardspecs->videoMemory = apm_memory; cardspecs->maxPixelClock4bpp = 75000; cardspecs->maxPixelClock8bpp = 175500; cardspecs->maxPixelClock16bpp = 144000; cardspecs->maxPixelClock24bpp = 75000; cardspecs->maxPixelClock32bpp = 94500; cardspecs->flags = (CLOCK_PROGRAMMABLE | INTERLACE_DIVIDE_VERT | GREATER_1024_DIVIDE_VERT); cardspecs->maxHorizontalCrtc = 2040; cardspecs->maxPixelClock4bpp = 0; cardspecs->nClocks =0; cardspecs->clocks = NULL; cardspecs->mapClock = apm_map_clock; cardspecs->mapHorizontalCrtc = apm_map_horizontal_crtc; cardspecs->matchProgrammableClock=apm_match_programmable_clock; __svgalib_driverspecs = &__svgalib_apm_driverspecs; return 0;}#define WITHIN(v,c1,c2) (((v) >= (c1)) && ((v) <= (c2)))static unsignedcomp_lmn(unsigned clock){ int n, m, l, f; double fvco; double fout; double fmax; double fref; double fvco_goal; double k, c; fmax = 400000.0; fref = 14318.0; for (m = 1; m <= 5; m++) { for (l = 3; l >= 0; l--) { for (n = 8; n <= 127; n++) { fout = ((double)(n + 1) * fref)/((double)(m + 1) * (1 << l)); fvco_goal = (double)clock * (double)(1 << l); fvco = fout * (double)(1 << l); if (!WITHIN(fvco, 0.995*fvco_goal, 1.005*fvco_goal)) continue; if (!WITHIN(fvco, 125000.0, fmax)) continue; if (!WITHIN(fvco / (double)(n+1), 300.0, 300000.0)) continue; if (!WITHIN(fref / (double)(m+1), 300.0, 300000.0)) continue; { k = 7.0 / (175.0 - 380.0); c = -k * 380.0; f = (int)(k * fvco/1000.0 + c + 0.5); if (f > 7) f = 7; if (f < 0) f = 0; } return (n << 16) | (m << 8) | (l << 2) | (f << 4); } } } return 0;}
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