apm.c

基于组件方式开发操作系统的OSKIT源代码

/*
At3d (at25) driver - Matan Ziv-Av [e-mail]
please report problems to me,
if you have an alliance promotion at24, or 6422, it should
be easy to make the driver work on it.

This driver is based on the XFREE86 apm driver, developed by
Kent Hamilton and by Henrik Harmsen.

I used the file cirrus.c in this directory as a skeleton.

there are still the following problems:
  * svga 320x200 modes don't work. (but 320x200x8, vga works).
  * pageflipping (in threeDKit) does not work. 
  * no acceleration (is there a program that uses it anyway?).
  * sometimes does not restore textfont when going back to textmode (or maybe the palette).

*/


#include <stdlib.h>
#include <stdio.h>		/* for printf */
#include <string.h>		/* for memset */
#include <sys/types.h>
#include <sys/mman.h>		/* mmap */
#include <unistd.h>
#include "vga.h"
#include "libvga.h"
#include "driver.h"


/* New style driver interface. */
#include "timing.h"
#include "vgaregs.h"
#include "interface.h"
#include "accel.h"

#define APMREG_SAVE(i) (VGA_TOTAL_REGS+i)
#define APM_TOTAL_REGS (VGA_TOTAL_REGS + 38)


static int apm_init(int, int, int);
static void apm_unlock(void);

void __svgalib_apmaccel_init(AccelSpecs * accelspecs, int bpp, int width_in_pixels);

static int apm_memory,apm_chiptype;
static int apm_is_linear,apm_xbase;

static CardSpecs *cardspecs;

static void outXR(int index,unsigned char d)
{
    __svgalib_outbSR(0x1d,index>>2);
    outb(apm_xbase,d);
}

static void outwXR(int index,unsigned short d)
{
    __svgalib_outbSR(0x1d,index>>2);
    outw(apm_xbase,d);
}

static void outlXR(int index,unsigned long d)
{
    __svgalib_outbSR(0x1d,index>>2);
    outl(apm_xbase,d);
}

static unsigned char inXR(int index)
{
    __svgalib_outbSR(0x1d,index>>2);
    return inb(apm_xbase);
}

#if 0
/* currently not used */
static unsigned short inwXR(int index)
{
    __svgalib_outbSR(0x1d,index>>2);
    return inw(apm_xbase);
}
#endif

static unsigned long inlXR(int index)
{
    __svgalib_outbSR(0x1d,index>>2);
    return inl(apm_xbase);
}

enum {
    AT6420 = 0, AT6422, AT24, AT3D
};

static void apm_setpage(int page)
{
    /* default 4K granularity */
outwXR(0xc0,page << 4);
}

static int __svgalib_apm_inlinearmode(void)
{
return apm_is_linear;
}

/* Fill in chipset specific mode information */

static void apm_getmodeinfo(int mode, vga_modeinfo *modeinfo)
{
	modeinfo->maxpixels = apm_memory*1024/modeinfo->bytesperpixel;
    modeinfo->maxlogicalwidth = 4088;
	modeinfo->startaddressrange = apm_memory * 1024 - 1;
	modeinfo->haveblit = 0;
    modeinfo->flags &= ~HAVE_RWPAGE;

    if (modeinfo->bytesperpixel >= 1) {
	modeinfo->flags |= CAPABLE_LINEAR;
        if (__svgalib_apm_inlinearmode())
	    modeinfo->flags |= IS_LINEAR;
    }
}

/* Read and save chipset-specific registers */

static int apm_saveregs(unsigned char regs[])
{ unsigned long k;

    apm_unlock();		/* May be locked again by other programs (e.g. X) */
    regs[APMREG_SAVE(2)] = __svgalib_inCR(0x19);
    regs[APMREG_SAVE(3)] = __svgalib_inCR(0x1A);
    regs[APMREG_SAVE(4)] = __svgalib_inCR(0x1B);
    regs[APMREG_SAVE(5)] = __svgalib_inCR(0x1C);
    regs[APMREG_SAVE(6)] = __svgalib_inCR(0x1D);
    regs[APMREG_SAVE(7)] = __svgalib_inCR(0x1E);

    regs[APMREG_SAVE(0)] = __svgalib_inSR(0x1B);
    regs[APMREG_SAVE(1)] = __svgalib_inSR(0x1C);

   regs[APMREG_SAVE(8)] = inXR(0x80) ;
   regs[APMREG_SAVE(9)] = inXR(0xc0) ;
   k = inlXR(0xe8) ;
   regs[APMREG_SAVE(10)] = k&0xff;
   regs[APMREG_SAVE(11)] = (k >> 8)&0xff;
   regs[APMREG_SAVE(12)] = (k >> 16) & 0xff ;
   regs[APMREG_SAVE(13)] = ( k >> 24 ) & 0xff ;
   k = inlXR(0xec) ;
   regs[APMREG_SAVE(14)] = k&0xff;
   regs[APMREG_SAVE(15)] = (k >> 8)&0xff;
   regs[APMREG_SAVE(16)] = (k >> 16) & 0xff ;
   regs[APMREG_SAVE(17)] = ( k >> 24 ) & 0xff ;
   (unsigned long)regs[APMREG_SAVE(18)] = inlXR(0xf0) ;
   (unsigned long)regs[APMREG_SAVE(22)] = inlXR(0xf4) ;
   (unsigned long)regs[APMREG_SAVE(26)] = inlXR(0x140) ;
   (unsigned short)regs[APMREG_SAVE(30)] = inlXR(0x144) ;
   (unsigned long)regs[APMREG_SAVE(32)] = inXR(0x148) ;
   (unsigned short)regs[APMREG_SAVE(36)] = inXR(0x14c) ;

    return APM_TOTAL_REGS - VGA_TOTAL_REGS;
}

/* Set chipset-specific registers */

static void apm_setregs(const unsigned char regs[], int mode)
{  unsigned long k ; 

    apm_unlock();		/* May be locked again by other programs (eg. X) */
    apm_setpage(0);

    __svgalib_outSR(0x1b,regs[APMREG_SAVE(0)]);
    __svgalib_outSR(0x1c,regs[APMREG_SAVE(1)]);
    __svgalib_outCR(0x19,regs[APMREG_SAVE(2)]);
    __svgalib_outCR(0x1a,regs[APMREG_SAVE(3)]);
    __svgalib_outCR(0x1b,regs[APMREG_SAVE(4)]);
    __svgalib_outCR(0x1c,regs[APMREG_SAVE(5)]);
    __svgalib_outCR(0x1d,regs[APMREG_SAVE(6)]);
    __svgalib_outCR(0x1e,regs[APMREG_SAVE(7)]);

   k=regs[APMREG_SAVE(10)]+(regs[APMREG_SAVE(11)] << 8)+(regs[APMREG_SAVE(12)] << 16)+(regs[APMREG_SAVE(13)] << 24);
   outlXR(0xe8,k) ;

   k=regs[APMREG_SAVE(14)]+(regs[APMREG_SAVE(15)] << 8)+(regs[APMREG_SAVE(16)] << 16)+(regs[APMREG_SAVE(17)] << 24);
   outlXR(0xec,k & ~(1 << 7)) ;
   outlXR(0xec,k | (1 << 7)) ;

   outXR(0x80,regs[APMREG_SAVE(8)]) ;

}


/* Return nonzero if mode is available */

static int apm_modeavailable(int mode)
{
    struct info *info;
    ModeTiming *modetiming;
    ModeInfo *modeinfo;

    modeinfo = __svgalib_createModeInfoStructureForSvgalibMode(mode);

/*    if((modeinfo->bitsPerPixel==24)||(0))return 0;
  */
    if ((mode < G640x480x256 )
	|| mode == G720x348x2)
	return __svgalib_vga_driverspecs.modeavailable(mode);

    info = &__svgalib_infotable[mode];
    if (apm_memory * 1024 < info->ydim * info->xbytes)
	return 0;

    modeinfo = __svgalib_createModeInfoStructureForSvgalibMode(mode);

    modetiming = malloc(sizeof(ModeTiming));
    if (__svgalib_getmodetiming(modetiming, modeinfo, cardspecs)) {
	free(modetiming);
	free(modeinfo);
	return 0;
    }
    free(modetiming);
    free(modeinfo);

    return SVGADRV;
}


static unsigned comp_lmn(unsigned clock) ;
/* Set a mode */

/* Local, called by apm_setmode(). */

static void apm_initializemode(unsigned char *moderegs,
			    ModeTiming * modetiming, ModeInfo * modeinfo, int mode)
{ long k;
  
    apm_saveregs(moderegs);
    __svgalib_setup_VGA_registers(moderegs, modetiming, modeinfo);

  {
    int offset;
    offset = modeinfo->lineWidth >> 3;
    moderegs[0x13] = offset;
    /* Bit 8 resides at CR1C bits 7:4. */
    moderegs[APMREG_SAVE(5)] = (offset & 0xf00) >> 4;
  }

  /* Set pixel depth. */
  switch(modeinfo->bitsPerPixel)
  {
    case 8:
         moderegs[APMREG_SAVE(8)] = 0x42;
         break;
    case 16:
         moderegs[APMREG_SAVE(8)] = modeinfo->greenWeight+7;
         break;
    case 24:
         moderegs[APMREG_SAVE(8)] = 0xe;
         break;
    case 32:
         moderegs[APMREG_SAVE(8)] = 0x0f;
         break;
    default:
         break;
  }

  /*
   * Enable VESA Super VGA memory organisation.
   * Also enable Linear Addressing.
   */
    moderegs[APMREG_SAVE(0)] = 0;
    moderegs[APMREG_SAVE(1)] = 21;
  /* Set banking register to zero. */
  moderegs[APMREG_SAVE(9)] = 0;

  /* Handle the CRTC overflow bits. */
  {
    unsigned char val;
    /* Vertical Overflow. */
    val = 0;
    if ((modetiming->CrtcVTotal - 2) & 0x400)
      val |= 0x01;
    if ((modetiming->CrtcVDisplay - 1) & 0x400)
      val |= 0x02;
    /* VBlankStart is equal to VSyncStart + 1. */
    if (modetiming->CrtcVSyncStart & 0x400)
      val |= 0x04;
    /* VRetraceStart is equal to VSyncStart + 1. */
    if (modetiming->CrtcVSyncStart & 0x400)
      val |= 0x08;
    moderegs[APMREG_SAVE(3)] = val;

    /* Horizontal Overflow. */
    val = 0;
    if ((modetiming->CrtcHTotal / 8 - 5) & 0x100)
      val |= 1;
    if ((modetiming->CrtcHDisplay / 8 - 1) & 0x100)
      val |= 2;
    /* HBlankStart is equal to HSyncStart - 1. */
    if ((modetiming->CrtcHSyncStart / 8 - 1) & 0x100)
      val |= 4;
    /* HRetraceStart is equal to HSyncStart. */
    if ((modetiming->CrtcHSyncStart / 8) & 0x100)
      val |= 8;
    moderegs[APMREG_SAVE(4)] = val;
  }
  moderegs[APMREG_SAVE(7)]= 1;          /* disable autoreset feature */

    k = comp_lmn(modetiming->pixelClock);
    moderegs[APMREG_SAVE(14)]=k&0xff;
    moderegs[APMREG_SAVE(15)]=(k >> 8)&0xff;
    moderegs[APMREG_SAVE(16)]=(k >> 16)&0xff;
    moderegs[APMREG_SAVE(17)]=(k >> 24)&0xff;   
    moderegs[MIS] |= 0xc;
moderegs[MIS]=0xef; 
  /* Set up the RAMDAC registers. */

  if (modeinfo->bitsPerPixel > 8)
    /* Get rid of white border. */
    {moderegs[VGA_AR11] = 0;} else 
{ int p,q,r;

moderegs[VGA_AR11]=0xff;
p=moderegs[1]+((moderegs[APMREG_SAVE(4)]&2)<<7); 
moderegs[2]=p&0xff;
moderegs[APMREG_SAVE(4)]&=0xfd;
moderegs[APMREG_SAVE(4)]|=(p&0x100)>>7;
q=moderegs[4]+((moderegs[APMREG_SAVE(4)]&8)<<5); 
/*switch(mode){
case 10:
r=p-q-24;
break;
case 11:
r=p-q-55;
break;
case 12:
r=p-q-21;
break;
case 39:
r=p-q-2;
break;
}*/
r=moderegs[0]+4;
moderegs[3]&=0xe0;
moderegs[3]|=(r&0x1f);
moderegs[5]&=0x7f;
moderegs[5]|=(r&0x20)<<2;

p=moderegs[0x12]+((moderegs[0x7]&2)<<7)+((moderegs[7]&0x40)<<3)+((moderegs[APMREG_SAVE(3)]&2)<<9);
moderegs[0x15]=p&0xff;
moderegs[0x7]&=0xf7;
moderegs[0x7]|=(p&0x100)>>5;
moderegs[0x9]&=0xdf;
moderegs[0x9]|=(p&0x200)>>4;
moderegs[APMREG_SAVE(3)]&=0xfb;
moderegs[APMREG_SAVE(3)]|=(p&0x400)>>7;
/*switch(mode){
case 10:
moderegs[0x16]+=43;