chips.c

基于组件方式开发操作系统的OSKIT源代码

					      mode->CrtcVDisplay));
	    }
	    moderegs[XR5A] = temp > 0x0F ? 0 : (unsigned char)temp;
	} else if (ctFlagsSet & ctFlags_StretchDisable) {
	    moderegs[XR55] &= 0xDF;
	    moderegs[XR57] &= 0x9F;
	}
    }

    moderegs[XR03] |= 0x02;   /* 32 bit I/O enable etc.          */
    moderegs[XR07] = 0xF4;    /* 32 bit I/O port selection       */
    moderegs[XR03] |= 0x08;   /* High bandwidth on 65548         */
    moderegs[XR40] = 0x01;    /*BitBLT Draw Mode for 8 and 24 bpp*/
  
    moderegs[XR52] |= 0x01;   /* Refresh count                   */
    moderegs[XR0F] &= 0xEF;   /* not Hi-/True-Colour             */
    moderegs[XR02] |= 0x01;   /* 16bit CPU Memory Access         */
    moderegs[XR02] &= 0xE3;   /* Attr. Cont. default access      */
                              /* use ext. regs. for hor. in dual */
    moderegs[XR06] &= 0xF3;   /* bpp clear                       */

    outb(0x3D6, 0x01);
    if ((inb(0x3D7)&7) == 6)
        moderegs[XR03] |= 0x40;	/* PCI Burst for 65548 */

    /* sync. polarities */
    if ((mode->flags & (PHSYNC | NHSYNC))
	&& (mode->flags & (PVSYNC | NVSYNC))) {
	if (mode->flags & (PHSYNC | NHSYNC)) {
	    if (mode->flags & PHSYNC) {
		moderegs[XR55] &= 0xBF;	/* CRT Hsync positive */
	    } else {
		moderegs[XR55] |= 0x40;	/* CRT Hsync negative */
	    }
	}
	if (mode->flags & (PVSYNC | NVSYNC)) {
	    if (mode->flags & PVSYNC) {
		moderegs[XR55] &= 0x7F;	/* CRT Vsync positive */
	    } else {
		moderegs[XR55] |= 0x80;	/* CRT Vsync negative */
	    }
	}
    }

    if (modeinfo->bitsPerPixel == 16) {
	moderegs[XR06] |= 0xC4;   /*15 or 16 bpp colour         */
	moderegs[XR0F] |= 0x10;   /*Hi-/True-Colour             */
	moderegs[XR40] = 0x02;    /*BitBLT Draw Mode for 16 bpp */
	if (modeinfo->greenWeight != 5)
	    moderegs[XR06] |= 0x08;	/*16bpp              */
    } else if (modeinfo->bitsPerPixel == 24) {
	moderegs[XR06] |= 0xC8;   /*24 bpp colour               */
        moderegs[XR0F] |= 0x10;   /*Hi-/True-Colour             */
	if (ctFlagsSet & ctFlags_Use18BitBus) { 
	    moderegs[XR50] &= 0x7F;   /*18 bit TFT data width   */
	} else {
	    moderegs[XR50] |= 0x80;   /*24 bit TFT data width   */
	}
    }

    /* STN specific */
    if (IS_STN(__svgalib_ctPanelType)) {
	moderegs[XR50] &= ~0x03;  /* FRC clear                  */
	moderegs[XR50] |= 0x01;   /* 16 frame FRC               */
	moderegs[XR50] &= ~0x0C;  /* Dither clear               */
	moderegs[XR50] |= 0x08;   /* Dither all modes           */
 	if (CHIPSchipset == CT_548) {
	    moderegs[XR03] |= 0x20; /* CRT I/F priority           */
	    moderegs[XR04] |= 0x10; /* RAS precharge 65548        */
	}
    }
}

static void CHIPS_HiQV_initializemode(unsigned char *moderegs,
			    ModeTiming * mode, ModeInfo * modeinfo)
{
    int lcdHTotal, lcdHDisplay;
    int lcdVTotal, lcdVDisplay;
    int lcdHRetraceStart, lcdHRetraceEnd;
    int lcdVRetraceStart, lcdVRetraceEnd;
    int lcdHSyncStart;
    unsigned int temp;

#ifdef DEBUG
    printf("CHIPS: CHIPS_HiQV_initializemode\n");
#endif

    /* Get current values. */
    CHIPS_saveregs(moderegs);

    /* Set up the standard VGA registers for a generic SVGA. */
    __svgalib_setup_VGA_registers(moderegs, mode, modeinfo);

    /* init clock */
    ctCalcClock(moderegs,mode->pixelClock);

    moderegs[VGA_AR10] = 0x01;   /* mode */
    moderegs[VGA_AR11] = 0x00;   /* overscan (border) color */
    moderegs[VGA_AR12] = 0x0F;   /* enable all color planes */
    moderegs[VGA_AR13] = 0x00;   /* horiz pixel panning 0 */
    moderegs[VGA_GR5] = 0x00;   /* normal read/write mode */

    temp = mode->CrtcHDisplay;
    if (modeinfo->bitsPerPixel == 24) {
      temp += temp << 1;
    } else if (modeinfo->bitsPerPixel == 16) {
      temp <<= 1;
    }
    moderegs[VGA_CR13] = (temp >> 3) & 0xFF ;
    moderegs[HiQVCR41] = (temp >> 11) & 0xF ;

    moderegs[HiQVXR0A] |= 0x1;	  /* Paging mode enabled */
    moderegs[HiQVXR09] |= 0x1;	  /* Enable extended CRT registers */
    moderegs[HiQVXR0E] = 0;		  /* Single map */
    moderegs[HiQVXR40] |= 0x3;	  /* High Resolution. XR40[1] reserved? */
    moderegs[HiQVXR81] &= 0xF8;       /* 256 Color Video */
    moderegs[HiQVXR81] |= 0x2;
    moderegs[HiQVXR80] |= 0x10;       /* Enable cursor output on P0 and P1 */
    moderegs[HiQVXR20] = 0x0;         /* BitBLT Draw mode for 8bpp */

    /* panel timing */
    /* By default don't set panel timings, but allow it as an option */
    if (ctFlagsSet & ctFlags_UseModeline) {
	lcdHTotal = (mode->CrtcHTotal >> 3) - 5;
	lcdHDisplay = (__svgalib_ctSize.HDisplay >> 3) - 1;
	lcdHRetraceStart = (mode->CrtcHSyncStart >> 3);
	lcdHRetraceEnd = (mode->CrtcHSyncEnd >> 3);
	lcdHSyncStart = lcdHRetraceStart - 2;

	lcdVTotal = mode->CrtcVTotal - 2;
	lcdVDisplay = __svgalib_ctSize.VDisplay - 1;
	lcdVRetraceStart = mode->CrtcVSyncStart;
	lcdVRetraceEnd = mode->CrtcVSyncEnd;

	moderegs[HiQVFR20] = lcdHDisplay & 0xFF;
	moderegs[HiQVFR21] = lcdHRetraceStart & 0xFF;
	moderegs[HiQVFR25] = ((lcdHRetraceStart & 0xF00) >> 4) |
	    ((lcdHDisplay & 0xF00) >> 8);
	moderegs[HiQVFR22] = lcdHRetraceEnd & 0x1F;
	moderegs[HiQVFR23] = lcdHTotal & 0xFF;
	moderegs[HiQVFR24] = (lcdHSyncStart >> 3) & 0xFF;
	moderegs[HiQVFR26] = (moderegs[HiQVFR26] & ~0x1F)
	    | ((lcdHTotal & 0xF00) >> 8)
	    | (((lcdHSyncStart >> 3) & 0x100) >> 4);
	moderegs[HiQVFR27] &= 0x7F;

	moderegs[HiQVFR30] = lcdVDisplay & 0xFF;
	moderegs[HiQVFR31] = lcdVRetraceStart & 0xFF;
	moderegs[HiQVFR35] = ((lcdVRetraceStart & 0xF00) >> 4)
	    | ((lcdVDisplay & 0xF00) >> 8);
	moderegs[HiQVFR32] = lcdVRetraceEnd & 0x0F;
	moderegs[HiQVFR33] = lcdVTotal & 0xFF;
	moderegs[HiQVFR34] = (lcdVTotal - lcdVRetraceStart) & 0xFF;
	moderegs[HiQVFR36] = ((lcdVTotal & 0xF00) >> 8) |
	    (((lcdVTotal - lcdVRetraceStart) & 0x700) >> 4);
	moderegs[HiQVFR37] |= 0x80;
    }

    /* Set up the extended CRT registers of the HiQV32 chips */
    moderegs[HiQVCR30] = ((mode->CrtcVTotal - 2) & 0xF00) >> 8;
    moderegs[HiQVCR31] = ((mode->CrtcVDisplay - 1) & 0xF00) >> 8;
    moderegs[HiQVCR32] = (mode->CrtcVSyncStart & 0xF00) >> 8;
    moderegs[HiQVCR33] = (mode->CrtcVSyncStart & 0xF00) >> 8;

    /* Screen Centring */
    if (ctFlagsSet & ctFlags_CenterEnable) {
	moderegs[HiQVFR40] |= 0x3;     /* Enable Horizontal centering */
	moderegs[HiQVFR48] |= 0x3;     /* Enable Vertical centering */
    } else if (ctFlagsSet & ctFlags_CenterDisable) {
	moderegs[HiQVFR40] |= 0xFD;    /* Disable Horizontal centering */
	moderegs[HiQVFR48] |= 0xFD;    /* Disable Vertical centering */
    }

    /* Screen Stretching */
    if (ctFlagsSet & ctFlags_StretchEnable) {
	moderegs[HiQVFR40] |= 0x21;    /* Enable Horizontal stretching */
	moderegs[HiQVFR48] |= 0x05;    /* Enable Vertical stretching */
    } else if (ctFlagsSet & ctFlags_StretchDisable) {
	moderegs[HiQVFR40] &= 0xDF;    /* Disable Horizontal stretching */
	moderegs[HiQVFR48] &= 0xFB;    /* Disable Vertical stretching */
    }

    /* sync. polarities */
    if ((mode->flags & (PHSYNC | NHSYNC))
	&& (mode->flags & (PVSYNC | NVSYNC))) {
	if (mode->flags & (PHSYNC | NHSYNC)) {
	    if (mode->flags & PHSYNC)
		moderegs[HiQVFR08] &= 0xBF;	/* Alt. CRT Hsync positive */
	    else
		moderegs[HiQVFR08] |= 0x40;	/* Alt. CRT Hsync negative */
	}
	if (mode->flags & (PVSYNC | NVSYNC)) {
	    if (mode->flags & PVSYNC)
	        moderegs[HiQVFR08] &= 0x7F;	/* Alt. CRT Vsync positive */
	    else
		moderegs[HiQVFR08] |= 0x80;	/* Alt. CRT Vsync negative */
	}
    }

    if (modeinfo->bitsPerPixel == 16) {
	moderegs[HiQVXR81] = (moderegs[HiQVXR81] & 0xF0) | 0x4; /* 15bpp */
	moderegs[HiQVFR10] |= 0x0C;   /*Colour Panel                 */
	moderegs[HiQVXR20] = 0x10;    /*BitBLT Draw Mode for 16 bpp  */
	if (modeinfo->greenWeight != 5)
	    moderegs[HiQVXR81] |= 0x01;	/*16bpp */
    } else if (modeinfo->bitsPerPixel == 24) {
	moderegs[HiQVXR81] = (moderegs[HiQVXR81] & 0xF0) | 0x6; /* 24bpp */
	moderegs[HiQVXR20] = 0x20;    /*BitBLT Draw Mode for 24 bpp */
    }

    /* STN specific */
    if (IS_STN(__svgalib_ctPanelType)) {
	moderegs[HiQVFR11] &= ~0x03;/* FRC clear                    */
	moderegs[HiQVFR11] |= 0x01;	/* 16 frame FRC                 */
	moderegs[HiQVFR11] &= ~0x8C;/* Dither clear                 */
	moderegs[HiQVFR11] |= 0x84;	/* Dither                       */
	if (__svgalib_ctPanelType == DD)	/* Shift Clock Mask. Use to get */
	  moderegs[HiQVFR12] |= 0x4;/* rid of line in DSTN screens  */
    }

}


/*----------------------------------------------------------------------*/
/* Check if mode is interlaced						*/
/*----------------------------------------------------------------------*/
static int CHIPS_interlaced(int mode)
{
#ifdef DEBUG
    printf("CHIPS: CHIPS_interlaced(%d)\n",mode);
#endif
	/* This driver does not support interlaced mode */
	return FALSE;
}


/*----------------------------------------------------------------------*/
/* Set a mode								*/
/*----------------------------------------------------------------------*/
static int CHIPS_setmode(int mode, int prv_mode)
{
	unsigned char *regs;
	ModeInfo *modeinfo;
	ModeTiming *modetiming;

#ifdef DEBUG
    printf("CHIPS: CHIPS_setmode(%d, %d)\n", mode, prv_mode);
#endif

        if (CHIPSchipset == CT_545 || CHIPSchipset == CT_546 ||
	     CHIPSchipset == CT_548 || CHIPSchipset == CT_550 ||
	     CHIPSchipset == CT_554) {
	    __svgalib_driverspecs->accelspecs->operations = 0;
	    __svgalib_driverspecs->accelspecs->ropOperations = 0;
	    __svgalib_driverspecs->accelspecs->transparencyOperations = 0;
	    __svgalib_driverspecs->accelspecs->ropModes = 0;
	    __svgalib_driverspecs->accelspecs->transparencyModes = 0;
	}

	if (!CHIPS_modeavailable(mode))
	{	return 1;
	}

	if (mode < G640x480x256 || mode == G720x348x2)
	    return (int) (__svgalib_vga_driverspecs.setmode(mode, prv_mode));

	modeinfo = __svgalib_createModeInfoStructureForSvgalibMode(mode);
	modetiming = malloc(sizeof(ModeTiming));
	if (__svgalib_getmodetiming(modetiming, modeinfo, cardspecs)) {
	    free(modetiming);
	    free(modeinfo);
	    return 1;
	}

	regs = malloc(CHIPS_TOTAL_REGS);
	if (ctisHiQV) {
	    CHIPS_HiQV_initializemode(regs, modetiming, modeinfo);
	} else {
	    CHIPS_initializemode(regs, modetiming, modeinfo);
	}
	free(modetiming);

	__svgalib_setregs(regs);
	CHIPS_setregs(regs, mode);

	if (ctFlagsSet & ctFlags_NoBitBlt) return 0;

	if (CHIPSchipset == CT_545 || CHIPSchipset == CT_546 ||
	    CHIPSchipset == CT_548) {
	    outb(0x3D6, 0x01);
	    if ((inb(0x3D7) & 7) == 6) {
		/* We are a PCI machine */
		if (__svgalib_modeinfo_linearset && IS_LINEAR) {
		    /* Linear addressing is enabled. So we can use
		     * MMIO with linear addressing. Map the required
		     * memory space
		     */
		    ctMMIO = TRUE;
		    __svgalib_ctMMIOPage = -1;
		    if (__svgalib_ctMMIOBase == NULL) {
#ifdef OSKIT
   		    {
			caddr_t dummy;
			osenv_mem_map_phys(__svgalib_ctMMIOBase + __svgalib_CHIPS_LinearBase + 0x200000L, 
					   0x10000, &dummy, 0);
		    }
#else
			mmap(__svgalib_ctMMIOBase, 0x10000, PROT_WRITE, MAP_FIXED | 
			     MAP_SHARED, __svgalib_mem_fd, 
			     __svgalib_CHIPS_LinearBase + 0x200000L);
#endif
		    }
		} else {
		    if (CHIPSchipset == CT_545 || CHIPSchipset == CT_546) {
			/* We are a 65545 or 65546 PCI machine. We only
			 * support acceleration on these machines with MMIO.
			 * Hence we have to use page mode to access the
			 * MMIO registers.
			 */
			 ctMMIO = TRUE;
			 __svgalib_ctMMIOPage = 32; /* MMIO starts at 2MBytes */
			 __svgalib_ctMMIOBase = __svgalib_graph_mem;
		    } else {
			/* Let the register address acceleration handle this */
			ctMMIO = FALSE;
		    }
		}
	    }
	}
	
	if (CHIPSchipset == CT_550 || CHIPSchipset == CT_554) {
	    if (__svgalib_modeinfo_linearset && IS_LINEAR) {
		/* Linear addressing is enabled. So we can use
		 * MMIO with linear addressing. Map the required
		 * memory space
		 */
		ctMMIO = TRUE;
		__svgalib_ctMMIOPage = -1;
		if (__svgalib_ctMMIOBase == NULL) {
#ifdef OSKIT
   		    {
			caddr_t dummy;
			osenv_mem_map_phys(__svgalib_ctMMIOBase + __svgalib_CHIPS_LinearBase + 0x400000L, 
					   0x20000, &dummy, 0);
		    }
#else
		    mmap(__svgalib_ctMMIOBase, 0x20000, PROT_WRITE, MAP_FIXED | 
			 MAP_SHARED, __svgalib_mem_fd, 
			 __svgalib_CHIPS_LinearBase + 0x400000L);
#endif
		}
		__svgalib_ctBltDataWindow = __svgalib_ctMMIOBase + 0x10000;
	    } else {
		/* Use paged addressing mode to program the MMIO registers */
		ctMMIO = TRUE;
		__svgalib_ctMMIOPage = 64; /* MMIO starts at 4MBytes */
		__svgalib_ctMMIOBase = __svgalib_graph_mem;
		__svgalib_ctBltDataWindow = __svgalib_graph_mem;
	    }
	}
	
	if (CHIPSchipset == CT_545 || CHIPSchipset == CT_546 ||
	    CHIPSchipset == CT_548 || CHIPSchipset == CT_550 ||
	    CHIPSchipset == CT_554) {
	    __svgalib_InitializeAcceleratorInterface(modeinfo);

	    __svgalib_driverspecs->accelspecs->operations =
	        ACCELFLAG_FILLBOX | ACCELFLAG_SETFGCOLOR |
		ACCELFLAG_SETBGCOLOR | ACCELFLAG_SCREENCOPY |
		ACCELFLAG_SETRASTEROP | ACCELFLAG_SETTRANSPARENCY |
		ACCELFLAG_SYNC;
    	    __svgalib_driverspecs->accelspecs->ropModes = (1<<ROP_COPY) |
		(1<<ROP_OR) | (1<<ROP_AND) | (1<<ROP_XOR) | (1<<ROP_INVERT);
	    __svgalib_driverspecs->accelspecs->transparencyModes =
		(1<<ENABLE_TRANSPARENCY_COLOR) | (1<<ENABLE_BITMAP_TRANSPARENCY);

	    if ((CHIPSchipset == CT_545 || CHIPSchipset == CT_546 ||
		CHIPSchipset == CT_548) && (modeinfo->bitsPerPixel == 24)) {
		__svgalib_driverspecs->accelspecs->ropOperations =
		    ACCELFLAG_SCREENCOPY;
	    } else {
		__svgalib_driverspecs->accelspecs->ropOperations =
	            ACCELFLAG_FILLBOX | ACCELFLAG_SCREENCOPY;
	    }
	    
	    if ((CHIPSchipset == CT_545 || CHIPSchipset == CT_546 ||
		CHIPSchipset == CT_548) && (modeinfo->bitsPerPixel != 24)) {
		/* For now PutBitmap is only supported on 6554x's. I
		 * don't have a 65550 machine to debug it on */
		__svgalib_driverspecs->accelspecs->operations |=
		    ACCELFLAG_PUTBITMAP;
		__svgalib_driverspecs->accelspecs->ropOperations |=
		    ACCELFLAG_PUTBITMAP;
		__svgalib_driverspecs->accelspecs->transparencyOperations |=
		    ACCELFLAG_PUTBITMAP;
	    }
	    
	    /* Set the function pointers; availability is handled by flags. */
	    __svgalib_driverspecs->accelspecs->SetFGColor = __svgalib_CHIPS_SetFGColor;
	    __svgalib_driverspecs->accelspecs->SetBGColor = __svgalib_CHIPS_SetBGColor;
	    __svgalib_driverspecs->accelspecs->SetRasterOp = __svgalib_CHIPS_SetRasterOp;
	    __svgalib_driverspecs->accelspecs->SetTransparency = __svgalib_CHIPS_SetTransparency;
	    if (ctMMIO) {
		if (ctisHiQV) {
		    __svgalib_driverspecs->accelspecs->FillBox = __svgalib_CHIPS_hiqv_FillBox;
		    __svgalib_driverspecs->accelspecs->ScreenCopy = CHIPS_hiqv_ScreenCopy;
		    __svgalib_driverspecs->accelspecs->Sync = CHIPS_hiqv_Sync;
		} else {
		    if (modeinfo->bitsPerPixel == 24) {
			__svgalib_driverspecs->accelspecs->FillBox = __svgalib_CHIPS_mmio_FillBox24;
		    } else {
			__svgalib_driverspecs->accelspecs->FillBox = __svgalib_CHIPS_mmio_FillBox;
			__svgalib_driverspecs->accelspecs->PutBitmap = __svgalib_CHIPS_mmio_PutBitmap;
		    }
		    __svgalib_driverspecs->accelspecs->ScreenCopy = CHIPS_mmio_ScreenCopy;