📄 vgahw.c
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/* * $XFree86: xc/programs/Xserver/hw/xfree86/vga256/vga/vgaHW.c,v 3.50.2.1 1997/05/10 07:03:00 hohndel Exp $ * * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that * the above copyright notice appear in all copies and that both that * copyright notice and this permission notice appear in supporting * documentation, and that the name of Thomas Roell not be used in * advertising or publicity pertaining to distribution of the software without * specific, written prior permission. Thomas Roell makes no representations * about the suitability of this software for any purpose. It is provided * "as is" without express or implied warranty. * * THOMAS ROELL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO * EVENT SHALL THOMAS ROELL BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. * * Author: Thomas Roell, roell@informatik.tu-muenchen.de *//* $XConsortium: vgaHW.c /main/19 1996/10/28 04:55:33 kaleb $ */#ifdef ISC202#include <sys/types.h>#define WIFEXITED(a) ((a & 0x00ff) == 0) /* LSB will be 0 */#define WEXITSTATUS(a) ((a & 0xff00) >> 8)#define WIFSIGNALED(a) ((a & 0xff00) == 0) /* MSB will be 0 */#define WTERMSIG(a) (a & 0x00ff)#else#if defined(ISC) && !defined(_POSIX_SOURCE)#define _POSIX_SOURCE#include <sys/types.h>#include <sys/wait.h>#undef _POSIX_SOURCE#else#if defined(MINIX) || defined(AMOEBA) || (defined(ISC) && defined(_POSIX_SOURCE)) || defined(Lynx) || defined(OSKIT)#include <sys/types.h>#endif#include <sys/wait.h>#endif#endif#if !defined(AMOEBA) && !defined(MINIX)#define _NEED_SYSI86#endif#include "X.h"#include "misc.h"#include "compiler.h"#include "xf86.h"#include "xf86Priv.h"#if 0#include <errno.h>#else#include "xf86_OSlib.h"#endif#include "xf86_HWlib.h"#include "vga.h"#ifdef PC98_EGC/* I/O port address define for extended EGC */#define EGC_READ 0x4a2 /* EGC FGC,EGC,Read Plane */#define EGC_MASK 0x4a8 /* EGC Mask register */#define EGC_ADD 0x4ac /* EGC Dest/Source address */#define EGC_LENGTH 0x4ae /* EGC Bit length */#endif#if !defined(PC98_NEC480) && !defined(PC98_EGC)#if !defined(MONOVGA) && !defined(SCO)#ifndef SAVE_FONT1#define SAVE_FONT1#endif#endif#if defined(Lynx) || defined(CSRG_BASED) || defined(MACH386) || defined(linux) || defined(AMOEBA) || defined(MINIX) || defined (OSKIT)#ifndef NEED_SAVED_CMAP#define NEED_SAVED_CMAP#endif#ifndef MONOVGA#ifndef SAVE_TEXT#define SAVE_TEXT#endif#endif#ifndef SAVE_FONT2#define SAVE_FONT2#endif#endif/* bytes per plane to save for text */#if defined(Lynx) || defined(linux) || defined(MINIX)#define TEXT_AMOUNT 16384#else#define TEXT_AMOUNT 4096#endif/* bytes per plane to save for font data */#define FONT_AMOUNT 8192#endif /* !defined(PC98_NEC480) && !defined(PC98_EGC) */#if defined(CSRG_BASED) || defined(MACH386)#include <sys/time.h>#endif#ifdef MACH386#define WEXITSTATUS(x) (x.w_retcode)#define WTERMSIG(x) (x.w_termsig)#define WSTOPSIG(x) (x.w_stopsig)#endif/* This the only where the definition seems to work (out of * vga.c/vgaHW.c/vgaCmap.c). */Bool clgd6225Lcd= FALSE;#ifdef MONOVGA/* DAC indices for white and black */#define WHITE_VALUE 0x3F#define BLACK_VALUE 0x00#define OVERSCAN_VALUE 0x01#endifstatic CARD32vgaOffMode(#if NeedFunctionPrototypes OsTimerPtr /* timer */, CARD32 /* now */, pointer /* arg */#endif);static CARD32vgaSuspendMode(#if NeedFunctionPrototypes OsTimerPtr /* timer */, CARD32 /* now */, pointer /* arg */#endif);static BoolsetExternClock(#if NeedFunctionPrototypes int /* clock */#endif);static int currentGraphicsClock = -1;static int currentExternClock = -1;int vgaRamdacMask = 0x3F;#define new ((vgaHWPtr)vgaNewVideoState)unsigned VGA_IOPorts[] = {#ifdef PC98_NEC480 0x60, 0x62, 0x6a, 0x7c, 0x7e, 0x80, 0xa0, 0xa2, 0x3c0, 0x3c2, 0x3c4, 0x3c6, 0x3c7, 0x3c8, 0x3c9, 0x3cc, 0x3ce, 0x3d0, 0x9a0, 0x9a8,#else#ifdef PC98_EGC/* I/O port address define Normal & Hireso mode */ 0xa8, 0xaa, 0xac, 0xae, 0x4a0, 0x4a1, 0x4a2, 0x4a3, 0x4a4, 0x4a5, 0x4a6, 0x4a7, 0x4a8, 0x4a9, 0x4aa, 0x4ab, 0x4ac, 0x4ad, 0x4ae, 0x4af,#else 0x3B4, 0x3B5, 0x3BA, 0x3C0, 0x3C1, 0x3C2, 0x3C4, 0x3C5, 0x3C6, 0x3C7, 0x3C8, 0x3C9, 0x3CA, 0x3CB, 0x3CC, 0x3CE, 0x3CF, 0x3D4, 0x3D5, 0x3DA,#endif#endif};int Num_VGA_IOPorts = (sizeof(VGA_IOPorts)/sizeof(VGA_IOPorts[0]));#ifdef NEED_SAVED_CMAP/* This default colourmap is used only when it can't be read from the VGA */unsigned char defaultDAC[768] ={ 0, 0, 0, 0, 0, 42, 0, 42, 0, 0, 42, 42, 42, 0, 0, 42, 0, 42, 42, 21, 0, 42, 42, 42, 21, 21, 21, 21, 21, 63, 21, 63, 21, 21, 63, 63, 63, 21, 21, 63, 21, 63, 63, 63, 21, 63, 63, 63, 0, 0, 0, 5, 5, 5, 8, 8, 8, 11, 11, 11, 14, 14, 14, 17, 17, 17, 20, 20, 20, 24, 24, 24, 28, 28, 28, 32, 32, 32, 36, 36, 36, 40, 40, 40, 45, 45, 45, 50, 50, 50, 56, 56, 56, 63, 63, 63, 0, 0, 63, 16, 0, 63, 31, 0, 63, 47, 0, 63, 63, 0, 63, 63, 0, 47, 63, 0, 31, 63, 0, 16, 63, 0, 0, 63, 16, 0, 63, 31, 0, 63, 47, 0, 63, 63, 0, 47, 63, 0, 31, 63, 0, 16, 63, 0, 0, 63, 0, 0, 63, 16, 0, 63, 31, 0, 63, 47, 0, 63, 63, 0, 47, 63, 0, 31, 63, 0, 16, 63, 31, 31, 63, 39, 31, 63, 47, 31, 63, 55, 31, 63, 63, 31, 63, 63, 31, 55, 63, 31, 47, 63, 31, 39, 63, 31, 31, 63, 39, 31, 63, 47, 31, 63, 55, 31, 63, 63, 31, 55, 63, 31, 47, 63, 31, 39, 63, 31, 31, 63, 31, 31, 63, 39, 31, 63, 47, 31, 63, 55, 31, 63, 63, 31, 55, 63, 31, 47, 63, 31, 39, 63, 45, 45, 63, 49, 45, 63, 54, 45, 63, 58, 45, 63, 63, 45, 63, 63, 45, 58, 63, 45, 54, 63, 45, 49, 63, 45, 45, 63, 49, 45, 63, 54, 45, 63, 58, 45, 63, 63, 45, 58, 63, 45, 54, 63, 45, 49, 63, 45, 45, 63, 45, 45, 63, 49, 45, 63, 54, 45, 63, 58, 45, 63, 63, 45, 58, 63, 45, 54, 63, 45, 49, 63, 0, 0, 28, 7, 0, 28, 14, 0, 28, 21, 0, 28, 28, 0, 28, 28, 0, 21, 28, 0, 14, 28, 0, 7, 28, 0, 0, 28, 7, 0, 28, 14, 0, 28, 21, 0, 28, 28, 0, 21, 28, 0, 14, 28, 0, 7, 28, 0, 0, 28, 0, 0, 28, 7, 0, 28, 14, 0, 28, 21, 0, 28, 28, 0, 21, 28, 0, 14, 28, 0, 7, 28, 14, 14, 28, 17, 14, 28, 21, 14, 28, 24, 14, 28, 28, 14, 28, 28, 14, 24, 28, 14, 21, 28, 14, 17, 28, 14, 14, 28, 17, 14, 28, 21, 14, 28, 24, 14, 28, 28, 14, 24, 28, 14, 21, 28, 14, 17, 28, 14, 14, 28, 14, 14, 28, 17, 14, 28, 21, 14, 28, 24, 14, 28, 28, 14, 24, 28, 14, 21, 28, 14, 17, 28, 20, 20, 28, 22, 20, 28, 24, 20, 28, 26, 20, 28, 28, 20, 28, 28, 20, 26, 28, 20, 24, 28, 20, 22, 28, 20, 20, 28, 22, 20, 28, 24, 20, 28, 26, 20, 28, 28, 20, 26, 28, 20, 24, 28, 20, 22, 28, 20, 20, 28, 20, 20, 28, 22, 20, 28, 24, 20, 28, 26, 20, 28, 28, 20, 26, 28, 20, 24, 28, 20, 22, 28, 0, 0, 16, 4, 0, 16, 8, 0, 16, 12, 0, 16, 16, 0, 16, 16, 0, 12, 16, 0, 8, 16, 0, 4, 16, 0, 0, 16, 4, 0, 16, 8, 0, 16, 12, 0, 16, 16, 0, 12, 16, 0, 8, 16, 0, 4, 16, 0, 0, 16, 0, 0, 16, 4, 0, 16, 8, 0, 16, 12, 0, 16, 16, 0, 12, 16, 0, 8, 16, 0, 4, 16, 8, 8, 16, 10, 8, 16, 12, 8, 16, 14, 8, 16, 16, 8, 16, 16, 8, 14, 16, 8, 12, 16, 8, 10, 16, 8, 8, 16, 10, 8, 16, 12, 8, 16, 14, 8, 16, 16, 8, 14, 16, 8, 12, 16, 8, 10, 16, 8, 8, 16, 8, 8, 16, 10, 8, 16, 12, 8, 16, 14, 8, 16, 16, 8, 14, 16, 8, 12, 16, 8, 10, 16, 11, 11, 16, 12, 11, 16, 13, 11, 16, 15, 11, 16, 16, 11, 16, 16, 11, 15, 16, 11, 13, 16, 11, 12, 16, 11, 11, 16, 12, 11, 16, 13, 11, 16, 15, 11, 16, 16, 11, 15, 16, 11, 13, 16, 11, 12, 16, 11, 11, 16, 11, 11, 16, 12, 11, 16, 13, 11, 16, 15, 11, 16, 16, 11, 15, 16, 11, 13, 16, 11, 12, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,};#endif /* NEED_SAVED_CMAP *//* * With Intel, the version in common_hw/SlowBcopy.s is used. * This avoids port I/O during the copy (which causes problems with * some hardware). */#ifdef __alpha__#define slowbcopy_tobus(src,dst,count) SlowBCopyToBus(src,dst,count)#define slowbcopy_frombus(src,dst,count) SlowBCopyFromBus(src,dst,count)#else /* __alpha__ */#define slowbcopy_tobus(src,dst,count) SlowBcopy(src,dst,count)#define slowbcopy_frombus(src,dst,count) SlowBcopy(src,dst,count)#endif /* __alpha__ *//* * vgaProtect -- * Protect VGA registers and memory from corruption during loads. */voidvgaProtect(on) Bool on;{#if !defined(PC98_NEC480) && !defined(PC98_EGC) unsigned char tmp; if (xf86VTSema) { if (on) { /* * Turn off screen and disable sequencer. */ outb(0x3C4, 0x01); tmp = inb(0x3C5); (*vgaSaveScreenFunc)(SS_START); /* start synchronous reset */ outw(0x3C4, ((tmp | 0x20) << 8) | 0x01); /* disable the display */ tmp = inb(vgaIOBase + 0x0A); outb(0x3C0, 0x00); /* enable pallete access */ } else { /* * Reenable sequencer, then turn on screen. */ outb(0x3C4, 0x01); tmp = inb(0x3C5); outw(0x3C4, ((tmp & 0xDF) << 8) | 0x01); /* reenable display */ (*vgaSaveScreenFunc)(SS_FINISH); /* clear synchronousreset */ tmp = inb(vgaIOBase + 0x0A); outb(0x3C0, 0x20); /* disable pallete access */ } }#endif /* !defined(PC98_NEC480) && !defined(PC98_EGC) */}/* * vgaSaveScreen -- blank the screen. */BoolvgaSaveScreen(pScreen, on) ScreenPtr pScreen; Bool on;{#if !defined(PC98_EGC) && !defined(PC98_NEC480) unsigned char scrn;#ifndef OSKIT if (on) SetTimeSinceLastInputEvent();#endif /* !OSKIT */ if (xf86VTSema) { /* the server is running on the current vt */ /* so just go for it */ outb(0x3C4,1); scrn = inb(0x3C5); if (on) { scrn &= 0xDF; /* enable screen */ } else { scrn |= 0x20; /* blank screen */ } (*vgaSaveScreenFunc)(SS_START); outw(0x3C4, (scrn << 8) | 0x01); /* change mode */ (*vgaSaveScreenFunc)(SS_FINISH); }#else /* PC98_EGC || PC98_NEC480 */ if (on) SetTimeSinceLastInputEvent(); if (xf86VTSema) { if (on) outb(0xa2, 0xd); else outb(0xa2, 0xc); }#endif /* PC98_EGC || PC98_NEC480 */ return (TRUE);}/* * vgaDPMSSet -- Sets VESA Display Power Management Signaling (DPMS) Mode * * This generic VGA function can only set the Off and On modes. If the * Standby and Suspend modes are to be supported, a chip specific replacement * for this function must be written. */voidvgaDPMSSet(PowerManagementMode) int PowerManagementMode;{#ifdef DPMSExtension unsigned char seq1, crtc17; if (!xf86VTSema) return; switch (PowerManagementMode) { case DPMSModeOn: /* Screen: On; HSync: On, VSync: On */ seq1 = 0x00; crtc17 = 0x80; break; case DPMSModeStandby: /* Screen: Off; HSync: Off, VSync: On -- Not Supported */ seq1 = 0x20; crtc17 = 0x80; break; case DPMSModeSuspend: /* Screen: Off; HSync: On, VSync: Off -- Not Supported */ seq1 = 0x20; crtc17 = 0x80; break; case DPMSModeOff: /* Screen: Off; HSync: Off, VSync: Off */ seq1 = 0x20; crtc17 = 0x00; break; } outw(0x3C4, 0x0100); /* Synchronous Reset */ outb(0x3C4, 0x01); /* Select SEQ1 */ seq1 |= inb(0x3C5) & ~0x20; outb(0x3C5, seq1); outb(vgaIOBase+4, 0x17); /* Select CRTC17 */
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