cxreg.h

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/*
 * Defines for Cronyx-Sigma adapter, based on Cirrus Logic multiprotocol
 * controller RISC processor CL-CD2400/2401.
 *
 * Copyright (C) 1994 Cronyx Ltd.
 * Author: Serge Vakulenko, <[e-mail]>
 *
 * This software is distributed with NO WARRANTIES, not even the implied
 * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 *
 * Authors grant any other persons or organizations permission to use
 * or modify this software as long as this message is kept with the software,
 * all derivative works or modified versions.
 *
 * Version 1.0, Fri Oct  7 19:34:06 MSD 1994
 */
#define NBRD      3		/* the maximum number of installed boards */
#define NPORT     16		/* the number of i/o ports per board */

#define REVCL_MIN 7		/* CD2400 min. revision number G */
#define REVCL_MAX 11		/* CD2400 max. revision number K */

#define BRD_INTR_LEVEL 0x5a	/* interrupt level (arbitrary PILR value) */

#define CS0(p)	((p) | 0x8000)	/* chip select 0 */
#define CS1(p)	((p) | 0xc000)	/* chip select 1 */
#define BSR(p)	(p)		/* board status register, read only */
#define BCR0(p)	(p)		/* board command register 0, write only */
#define BCR1(p)	((p) | 0x2000)	/* board command register 1, write only */

/*
 * Chip register address, B is chip base port, R is chip register number.
 */
#define R(b,r) ((b) | (((r)<<6 & 0x3c00) | ((r) & 0xf)))

/*
 * Interrupt acknowledge register, P is board port, L is interrupt level,
 * as programmed in PILR.
 */
#define IACK(p,l)   (R(p,l) | 0x4000)

/*
 * Global registers.
 */
#define GFRCR(b)    R(b,0x82)	/* global firmware revision code register */
#define CAR(b)      R(b,0xec)	/* channel access register */

/*
 * Option registers.
 */
#define CMR(b)      R(b,0x18)	/* channel mode register */
#define COR1(b)     R(b,0x13)	/* channel option register 1 */
#define COR2(b)     R(b,0x14)	/* channel option register 2 */
#define COR3(b)     R(b,0x15)	/* channel option register 3 */
#define COR4(b)     R(b,0x16)	/* channel option register 4 */
#define COR5(b)     R(b,0x17)	/* channel option register 5 */
#define COR6(b)     R(b,0x1b)	/* channel option register 6 */
#define COR7(b)     R(b,0x04)	/* channel option register 7 */
#define SCHR1(b)    R(b,0x1c)	/* special character register 1 */
#define SCHR2(b)    R(b,0x1d)	/* special character register 2 */
#define SCHR3(b)    R(b,0x1e)	/* special character register 3 */
#define SCHR4(b)    R(b,0x1f)	/* special character register 4 */
#define SCRL(b)     R(b,0x20)	/* special character range low */
#define SCRH(b)     R(b,0x21)	/* special character range high */
#define LNXT(b)     R(b,0x2d)	/* LNext character */
#define RFAR1(b)    R(b,0x1c)	/* receive frame address register 1 */
#define RFAR2(b)    R(b,0x1d)	/* receive frame address register 2 */
#define RFAR3(b)    R(b,0x1e)	/* receive frame address register 3 */
#define RFAR4(b)    R(b,0x1f)	/* receive frame address register 4 */
#define CPSR(b)     R(b,0xd4)	/* CRC polynomial select register */

/*
 * Bit rate and clock option registers.
 */
#define RBPR(b)     R(b,0xc9)	/* receive baud rate period register */
#define RCOR(b)     R(b,0xca)	/* receive clock option register */
#define TBPR(b)     R(b,0xc1)	/* transmit baud rate period register */
#define TCOR(b)     R(b,0xc2)	/* receive clock option register */

/*
 * Channel command and status registers.
 */
#define CCR(b)      R(b,0x10)	/* channel command register */
#define STCR(b)     R(b,0x11)	/* special transmit command register */
#define CSR(b)      R(b,0x19)	/* channel status register */
#define MSVR(b)     R(b,0xdc)	/* modem signal value register */
#define MSVR_RTS(b) R(b,0xdc)	/* modem RTS setup register */
#define MSVR_DTR(b) R(b,0xdd)	/* modem DTR setup register */

/*
 * Interrupt registers.
 */
#define LIVR(b)     R(b,0x0a)	/* local interrupt vector register */
#define IER(b)      R(b,0x12)	/* interrupt enable register */
#define LICR(b)     R(b,0x25)	/* local interrupting channel register */
#define STK(b)      R(b,0xe0)	/* stack register */

/*
 * Receive interrupt registers.
 */
#define RPILR(b)    R(b,0xe3)	/* receive priority interrupt level register */
#define RIR(b)      R(b,0xef)	/* receive interrupt register */
#define RISR(b)     R(b,0x8a)	/* receive interrupt status register */
#define RISRL(b)    R(b,0x8a)	/* receive interrupt status register low */
#define RISRH(b)    R(b,0x8b)	/* receive interrupt status register high */
#define RFOC(b)     R(b,0x33)	/* receive FIFO output count */
#define RDR(b)      R(b,0xf8)	/* receive data register */
#define REOIR(b)    R(b,0x87)	/* receive end of interrupt register */

/*
 * Transmit interrupt registers.
 */
#define TPILR(b)    R(b,0xe2)	/* transmit priority interrupt level reg */
#define TIR(b)      R(b,0xee)	/* transmit interrupt register */
#define TISR(b)     R(b,0x89)	/* transmit interrupt status register */
#define TFTC(b)     R(b,0x83)	/* transmit FIFO transfer count */
#define TDR(b)      R(b,0xf8)	/* transmit data register */
#define TEOIR(b)    R(b,0x86)	/* transmit end of interrupt register */

/*
 * Modem interrupt registers.
 */
#define MPILR(b)    R(b,0xe1)	/* modem priority interrupt level register */
#define MIR(b)      R(b,0xed)	/* modem interrupt register */
#define MISR(b)     R(b,0x88)	/* modem/timer interrupt status register */
#define MEOIR(b)    R(b,0x85)	/* modem end of interrupt register */

/*
 * DMA registers.
 */
#define DMR(b)      R(b,0xf4)	/* DMA mode register */
#define BERCNT(b)   R(b,0x8d)	/* bus error retry count */
#define DMABSTS(b)  R(b,0x1a)	/* DMA buffer status */

/*
 * DMA receive registers.
 */
#define ARBADRL(b)  R(b,0x40)	/* A receive buffer address lower */
#define ARBADRU(b)  R(b,0x42)	/* A receive buffer address upper */
#define BRBADRL(b)  R(b,0x44)	/* B receive buffer address lower */
#define BRBADRU(b)  R(b,0x46)	/* B receive buffer address upper */
#define ARBCNT(b)   R(b,0x48)	/* A receive buffer byte count */
#define BRBCNT(b)   R(b,0x4a)	/* B receive buffer byte count */
#define ARBSTS(b)   R(b,0x4c)	/* A receive buffer status */
#define BRBSTS(b)   R(b,0x4d)	/* B receive buffer status */
#define RCBADRL(b)  R(b,0x3c)	/* receive current buffer address lower */
#define RCBADRU(b)  R(b,0x3e)	/* receive current buffer address upper */

/*
 * DMA transmit registers.
 */
#define ATBADRL(b)  R(b,0x50)	/* A transmit buffer address lower */
#define ATBADRU(b)  R(b,0x52)	/* A transmit buffer address upper */
#define BTBADRL(b)  R(b,0x54)	/* B transmit buffer address lower */
#define BTBADRU(b)  R(b,0x56)	/* B transmit buffer address upper */
#define ATBCNT(b)   R(b,0x58)	/* A transmit buffer byte count */
#define BTBCNT(b)   R(b,0x5a)	/* B transmit buffer byte count */
#define ATBSTS(b)   R(b,0x5c)	/* A transmit buffer status */
#define BTBSTS(b)   R(b,0x5d)	/* B transmit buffer status */
#define TCBADRL(b)  R(b,0x38)	/* transmit current buffer address lower */
#define TCBADRU(b)  R(b,0x3a)	/* transmit current buffer address upper */

/*
 * Timer registers.
 */
#define TPR(b)      R(b,0xd8)	/* timer period register */
#define RTPR(b)     R(b,0x26)	/* receive timeout period register */
#define RTPRL(b)    R(b,0x26)	/* receive timeout period register low */
#define RTPTH(b)    R(b,0x27)	/* receive timeout period register high */
#define GT1(b)      R(b,0x28)	/* general timer 1 */
#define GT1L(b)     R(b,0x28)	/* general timer 1 low */
#define GT1H(b)     R(b,0x29)	/* general timer 1 high */
#define GT2(b)      R(b,0x2a)	/* general timer 2 */
#define TTR(b)      R(b,0x2a)	/* transmit timer register */

/*
 * Board status register bits.
 */
#define BSR_NOINTR     0x01	/* no interrupt pending flag */

#define BSR_VAR_MASK   0x66	/* adapter variant mask */

#define BSR_OSC_MASK   0x18	/* oscillator frequency mask */
#define BSR_OSC_20     0x18	/* 20 MHz */
#define BSR_OSC_18432  0x10	/* 18.432 MHz */

#define BSR_NOCHAIN    0x80	/* no daisy chained board */

#define BSR_NODSR(n)   (0x100 << (n))	/* DSR from channels 0-3, inverted */
#define BSR_NOCD(n)    (0x1000 << (n))	/* CD from channels 0-3, inverted */

/*
 * Board revision mask.
 */
#define BSR_REV_MASK   (BSR_OSC_MASK|BSR_VAR_MASK|BSR_NOCHAIN)

/*
 * Board control register 0 bits.
 */
#define BCR0_IRQ_DIS  0x00	/* no interrupt generated */
#define BCR0_IRQ_3    0x01	/* select IRQ number 3 */
#define BCR0_IRQ_5    0x02	/* select IRQ number 5 */
#define BCR0_IRQ_7    0x03	/* select IRQ number 7 */
#define BCR0_IRQ_10   0x04	/* select IRQ number 10 */
#define BCR0_IRQ_11   0x05	/* select IRQ number 11 */
#define BCR0_IRQ_12   0x06	/* select IRQ number 12 */
#define BCR0_IRQ_15   0x07	/* select IRQ number 15 */

#define BCR0_NORESET  0x08	/* CD2400 reset flag (inverted) */

#define BCR0_DMA_DIS  0x00	/* no interrupt generated */
#define BCR0_DMA_5    0x10	/* select DMA channel 5 */
#define BCR0_DMA_6    0x20	/* select DMA channel 6 */
#define BCR0_DMA_7    0x30	/* select DMA channel 7 */