pdqreg.h

来自「基于组件方式开发操作系统的OSKIT源代码」· C头文件 代码 · 共 1,066 行 · 第 1/3 页

/*-
 * Copyright (c) 1995, 1996 Matt Thomas <[e-mail]>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. The name of the author may not be used to endorse or promote products
 *    derived from this software withough specific prior written permission
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * $Id: pdqreg.h,v 1.1.1.1 1997/01/17 23:19:49 joerg Exp $
 *
 */

/*
 * DEC PDQ FDDI Controller; PDQ port driver definitions
 *
 */

#ifndef _PDQREG_H
#define	_PDQREG_H

#include <stddef.h>
#if defined(PDQTEST) && !defined(PDQ_NDEBUG)
#include <assert.h>
#define	PDQ_ASSERT	assert
#else
#define	PDQ_ASSERT(x)	do { } while(0)
#endif

#define	PDQ_RING_SIZE(array)	((sizeof(array) / sizeof(array[0])))
#define	PDQ_ARRAY_SIZE(array)	((sizeof(array) / sizeof(array[0])))
#define	PDQ_RING_MASK(array)	(PDQ_RING_SIZE(array) - 1)
#define	PDQ_BITMASK(n)		(1L << (pdq_uint32_t) (n))

#define	PDQ_FDDI_MAX		4495
#define	PDQ_FDDI_LLC_MIN	20
#define	PDQ_FDDI_SMT_MIN	37

#define	PDQ_FDDI_SMT		0x40
#define	PDQ_FDDI_LLC_ASYNC	0x50
#define	PDQ_FDDI_LLC_SYNC	0xD0
#define	PDQ_FDDI_IMP_ASYNC	0x60
#define	PDQ_FDDI_IMP_SYNC	0xE0

#define	PDQ_FDDIFC_C		0x80
#define	PDQ_FDDIFC_L		0x40
#define	PDQ_FDDIFC_F		0x30
#define	PDQ_FDDIFC_Z		0x0F

#define	PDQ_FDDI_PH0		0x20
#define	PDQ_FDDI_PH1		0x38
#define	PDQ_FDDI_PH2		0x00

typedef pdq_uint32_t pdq_physaddr_t;

struct _pdq_lanaddr_t {
    pdq_uint8_t lanaddr_bytes[8];
};

typedef struct {
    pdq_uint8_t fwrev_bytes[4];
} pdq_fwrev_t;

enum _pdq_state_t {
    PDQS_RESET=0,
    PDQS_UPGRADE=1,
    PDQS_DMA_UNAVAILABLE=2,
    PDQS_DMA_AVAILABLE=3,
    PDQS_LINK_AVAILABLE=4,
    PDQS_LINK_UNAVAILABLE=5,
    PDQS_HALTED=6,
    PDQS_RING_MEMBER=7
};

struct _pdq_csrs_t {
    pdq_bus_memoffset_t csr_port_reset;			/* 0x00 [RW] */
    pdq_bus_memoffset_t csr_host_data;			/* 0x04 [R]  */
    pdq_bus_memoffset_t csr_port_control;		/* 0x08 [RW] */
    pdq_bus_memoffset_t csr_port_data_a;		/* 0x0C [RW] */
    pdq_bus_memoffset_t csr_port_data_b;		/* 0x10 [RW] */
    pdq_bus_memoffset_t csr_port_status;		/* 0x14 [R]  */
    pdq_bus_memoffset_t csr_host_int_type_0;		/* 0x18 [RW] */
    pdq_bus_memoffset_t csr_host_int_enable;		/* 0x1C [RW] */
    pdq_bus_memoffset_t csr_type_2_producer;		/* 0x20 [RW] */
    pdq_bus_memoffset_t csr_cmd_response_producer;	/* 0x28 [RW] */
    pdq_bus_memoffset_t csr_cmd_request_producer;	/* 0x2C [RW] */
    pdq_bus_memoffset_t csr_host_smt_producer;		/* 0x30 [RW] */
    pdq_bus_memoffset_t csr_unsolicited_producer;	/* 0x34 [RW] */
    pdq_bus_t csr_bus;
    pdq_bus_memaddr_t csr_base;
};

struct _pdq_pci_csrs_t {
    pdq_bus_memoffset_t csr_pfi_mode_control;		/* 0x40 [RW] */
    pdq_bus_memoffset_t csr_pfi_status;			/* 0x44 [RW] */
    pdq_bus_memoffset_t csr_fifo_write;			/* 0x48 [RW] */
    pdq_bus_memoffset_t csr_fifo_read;			/* 0x4C [RW] */
    pdq_bus_t csr_bus;
    pdq_bus_memaddr_t csr_base;
};

#define PDQ_PFI_MODE_DMA_ENABLE		0x01	/* DMA Enable */
#define PDQ_PFI_MODE_PFI_PCI_INTR	0x02	/* PFI-to-PCI Int Enable */
#define PDQ_PFI_MODE_PDQ_PCI_INTR	0x04	/* PDQ-to-PCI Int Enable */

#define PDQ_PFI_STATUS_PDQ_INTR		0x10	/* PDQ Int received */
#define PDQ_PFI_STATUS_DMA_ABORT	0x08	/* PDQ DMA Abort asserted */

#define	PDQ_EISA_BURST_HOLDOFF			0x0040
#define	PDQ_EISA_SLOT_ID			0x0C80
#define	PDQ_EISA_SLOT_CTRL			0x0C84
#define	PDQ_EISA_MEM_ADD_CMP_0			0x0C85
#define	PDQ_EISA_MEM_ADD_CMP_1			0x0C86
#define	PDQ_EISA_MEM_ADD_CMP_2			0x0C87
#define	PDQ_EISA_MEM_ADD_HI_CMP_0		0x0C88
#define	PDQ_EISA_MEM_ADD_HI_CMP_1		0x0C89
#define	PDQ_EISA_MEM_ADD_HI_CMP_2		0x0C8A
#define	PDQ_EISA_MEM_ADD_MASK_0			0x0C8B
#define	PDQ_EISA_MEM_ADD_MASK_1			0x0C8C
#define	PDQ_EISA_MEM_ADD_MASK_2			0x0C8D
#define	PDQ_EISA_MEM_ADD_LO_CMP_0		0x0C8E
#define	PDQ_EISA_MEM_ADD_LO_CMP_1		0x0C8F
#define	PDQ_EISA_MEM_ADD_LO_CMP_2		0x0C90
#define	PDQ_EISA_IO_CMP_0_0			0x0C91
#define	PDQ_EISA_IO_CMP_0_1			0x0C92
#define	PDQ_EISA_IO_CMP_1_0			0x0C93
#define	PDQ_EISA_IO_CMP_1_1			0x0C94
#define	PDQ_EISA_IO_CMP_2_0			0x0C95
#define	PDQ_EISA_IO_CMP_2_1			0x0C96
#define	PDQ_EISA_IO_CMP_3_0			0x0C97
#define	PDQ_EISA_IO_CMP_3_1			0x0C98
#define	PDQ_EISA_IO_ADD_MASK_0_0		0x0C99
#define	PDQ_EISA_IO_ADD_MASK_0_1		0x0C9A
#define	PDQ_EISA_IO_ADD_MASK_1_0		0x0C9B
#define	PDQ_EISA_IO_ADD_MASK_1_1		0x0C9C
#define	PDQ_EISA_IO_ADD_MASK_2_0		0x0C9D
#define	PDQ_EISA_IO_ADD_MASK_2_1		0x0C9E
#define	PDQ_EISA_IO_ADD_MASK_3_0		0x0C9F
#define	PDQ_EISA_IO_ADD_MASK_3_1		0x0CA0
#define	PDQ_EISA_MOD_CONFIG_1			0x0CA1
#define	PDQ_EISA_MOD_CONFIG_2			0x0CA2
#define	PDQ_EISA_MOD_CONFIG_3			0x0CA3
#define	PDQ_EISA_MOD_CONFIG_4			0x0CA4
#define	PDQ_EISA_MOD_CONFIG_5			0x0CA5
#define	PDQ_EISA_MOD_CONFIG_6			0x0CA6
#define	PDQ_EISA_MOD_CONFIG_7			0x0CA7
#define	PDQ_EISA_DIP_SWITCH			0x0CA8
#define	PDQ_EISA_IO_CONFIG_STAT_0		0x0CA9
#define	PDQ_EISA_IO_CONFIG_STAT_1		0x0CAA
#define	PDQ_EISA_DMA_CONFIG			0x0CAB
#define	PDQ_EISA_INPUT_PORT			0x0CAC
#define	PDQ_EISA_OUTPUT_PORT			0x0CAD
#define	PDQ_EISA_FUNCTION_CTRL			0x0CAE

#define	PDQ_TC_CSR_OFFSET			0x00100000
#define	PDQ_TC_CSR_SPACE			0x0040
#define	PDQ_FBUS_CSR_OFFSET			0x00200000
#define	PDQ_FBUS_CSR_SPACE			0x0080

/*
 * Port Reset Data A Definitions
 */
#define	PDQ_PRESET_SKIP_SELFTEST	0x0004
#define	PDQ_PRESET_SOFT_RESET		0x0002
#define	PDQ_PRESET_UPGRADE		0x0001
/*
 * Port Control Register Definitions
 */
#define	PDQ_PCTL_CMD_ERROR		0x8000
#define	PDQ_PCTL_FLASH_BLAST		0x4000
#define	PDQ_PCTL_HALT			0x2000
#define	PDQ_PCTL_COPY_DATA		0x1000
#define	PDQ_PCTL_ERROR_LOG_START	0x0800
#define	PDQ_PCTL_ERROR_LOG_READ		0x0400
#define	PDQ_PCTL_XMT_DATA_FLUSH_DONE	0x0200
#define	PDQ_PCTL_DMA_INIT		0x0100
#define	PDQ_DMA_INIT_LW_BSWAP_DATA	0x02
#define	PDQ_DMA_INIT_LW_BSWAP_LITERAL	0x01
#define	PDQ_PCTL_INIT_START		0x0080
#define	PDQ_PCTL_CONSUMER_BLOCK		0x0040
#define	PDQ_PCTL_DMA_UNINIT		0x0020
#define	PDQ_PCTL_RING_MEMBER		0x0010
#define	PDQ_PCTL_MLA_READ		0x0008
#define	PDQ_PCTL_FW_REV_READ		0x0004
#define	PDQ_PCTL_DEVICE_SPECIFIC	0x0002
#define	PDQ_PCTL_SUB_CMD		0x0001

typedef enum {
    PDQ_SUB_CMD_LINK_UNINIT=1,
    PDQ_SUB_CMD_DMA_BURST_SIZE_SET=2,
    PDQ_SUB_CMD_PDQ_REV_GET=4
} pdq_sub_cmd_t;

typedef enum {
    PDQ_DMA_BURST_4LW=0,
    PDQ_DMA_BURST_8LW=1,
    PDQ_DMA_BURST_16LW=2,
    PDQ_DMA_BURST_32LW=3
} pdq_dma_burst_size_t;

typedef enum {
    PDQ_CHIP_REV_A_B_OR_C=0,
    PDQ_CHIP_REV_D=2,
    PDQ_CHIP_REV_E=4
} pdq_chip_rev_t;
/*
 * Port Status Register Definitions
 */
#define	PDQ_PSTS_RCV_DATA_PENDING	0x80000000ul
#define	PDQ_PSTS_XMT_DATA_PENDING	0x40000000ul
#define	PDQ_PSTS_HOST_SMT_PENDING	0x20000000ul
#define	PDQ_PSTS_UNSOL_PENDING		0x10000000ul
#define	PDQ_PSTS_CMD_RSP_PENDING	0x08000000ul
#define	PDQ_PSTS_CMD_REQ_PENDING	0x04000000ul
#define	PDQ_PSTS_TYPE_0_PENDING		0x02000000ul
#define	PDQ_PSTS_INTR_PENDING		0xFE000000ul
#define	PDQ_PSTS_ADAPTER_STATE(sts)	((pdq_state_t) (((sts) >> 8) & 0x07))
#define	PDQ_PSTS_HALT_ID(sts)		((pdq_halt_code_t) ((sts) & 0xFF))
/*
 * Host Interrupt Register Definitions
 */
#define	PDQ_HOST_INT_TX_ENABLE			0x80000000ul
#define	PDQ_HOST_INT_RX_ENABLE			0x40000000ul
#define	PDQ_HOST_INT_UNSOL_ENABLE		0x20000000ul
#define	PDQ_HOST_INT_HOST_SMT_ENABLE		0x10000000ul
#define	PDQ_HOST_INT_CMD_RSP_ENABLE		0x08000000ul
#define	PDQ_HOST_INT_CMD_RQST_ENABLE		0x04000000ul

#define	PDQ_HOST_INT_1MS			0x80
#define	PDQ_HOST_INT_20MS			0x40
#define	PDQ_HOST_INT_CSR_CMD_DONE		0x20
#define	PDQ_HOST_INT_STATE_CHANGE		0x10
#define	PDQ_HOST_INT_XMT_DATA_FLUSH		0x08
#define	PDQ_HOST_INT_NXM			0x04
#define	PDQ_HOST_INT_PM_PARITY_ERROR		0x02
#define	PDQ_HOST_INT_HOST_BUS_PARITY_ERROR	0x01
#define	PDQ_HOST_INT_FATAL_ERROR		0x07

typedef enum {
    PDQH_SELFTEST_TIMEOUT=0,
    PDQH_HOST_BUS_PARITY_ERROR=1,
    PDQH_HOST_DIRECTED_HALT=2,
    PDQH_SOFTWARE_FAULT=3,
    PDQH_HARDWARE_FAULT=4,
    PDQH_PC_TRACE_PATH_TEST=5,
    PDQH_DMA_ERROR=6,
    PDQH_IMAGE_CRC_ERROR=7,
    PDQH_ADAPTER_PROCESSOR_ERROR=8,
    PDQH_MAX=9
} pdq_halt_code_t;

typedef struct {
    pdq_uint16_t pdqcb_receives;
    pdq_uint16_t pdqcb_transmits;
    pdq_uint32_t pdqcb__filler1;
    pdq_uint32_t pdqcb_host_smt;
    pdq_uint32_t pdqcb__filler2;
    pdq_uint32_t pdqcb_unsolicited_event;
    pdq_uint32_t pdqcb__filler3;
    pdq_uint32_t pdqcb_command_response;
    pdq_uint32_t pdqcb__filler4;
    pdq_uint32_t pdqcb_command_request;
    pdq_uint32_t pdqcb__filler5[7];
} pdq_consumer_block_t;

#if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN
#define	PDQ_BITFIELD2(a, b)		         b, a
#define	PDQ_BITFIELD3(a, b, c)		      c, b, a
#define	PDQ_BITFIELD4(a, b, c, d)	   d, c, b, a
#define	PDQ_BITFIELD5(a, b, c, d, e)	e, d, c, b, a
#define	PDQ_BITFIELD12(a, b, c, d, e, f, g, h, i, j, k, l)	\
					l, k, j, i, h, g, f, e, d, c, b, a
#else
#define	PDQ_BITFIELD2(a, b)		a, b
#define	PDQ_BITFIELD3(a, b, c)		a, b, c
#define	PDQ_BITFIELD4(a, b, c, d)	a, b, c, d
#define	PDQ_BITFIELD5(a, b, c, d, e)	a, b, c, d, e
#define	PDQ_BITFIELD12(a, b, c, d, e, f, g, h, i, j, k, l)	\
					a, b, c, d, e, f, g, h, i, j, k, l
#endif

typedef struct {
    pdq_uint32_t PDQ_BITFIELD5(rxd_pa_hi : 16,
			       rxd_seg_cnt : 4,
			       rxd_seg_len_hi : 9,
			       rxd_seg_len_lo : 2,
			       rxd_sop : 1);
    pdq_uint32_t rxd_pa_lo;
} pdq_rxdesc_t;

typedef union {
    pdq_uint32_t rxs_status;
    pdq_uint32_t PDQ_BITFIELD12(rxs_len : 13,
				rxs_rcc_ss : 2,
				rxs_rcc_dd : 2,
				rxs_rcc_reason : 3,
				rxs_rcc_badcrc : 1,
				rxs_rcc_badpdu : 1,
				rxs_fsb__reserved : 2,
				rxs_fsb_c : 1,
				rxs_fsb_a : 1,
				rxs_fsb_e : 1,
				rxs_fsc : 3,
				rxs__reserved : 2);
} pdq_rxstatus_t;

typedef struct {
    pdq_uint32_t PDQ_BITFIELD5(txd_pa_hi : 16,
			       txd_seg_len : 13,
			       txd_mbz : 1,
			       txd_eop : 1,
			       txd_sop : 1);
    pdq_uint32_t txd_pa_lo;
} pdq_txdesc_t;

typedef struct {
    pdq_rxdesc_t pdqdb_receives[256];		/* 2048;	0x0000..0x07FF */
    pdq_txdesc_t pdqdb_transmits[256];		/* 2048;	0x0800..0x0FFF */
    pdq_rxdesc_t pdqdb_host_smt[64];		/*  512;	0x1000..0x11FF */
    pdq_rxdesc_t pdqdb_unsolicited_events[16];	/*  128;	0x1200..0x127F */
    pdq_rxdesc_t pdqdb_command_responses[16];	/*  128;	0x1280..0x12FF */
    pdq_txdesc_t pdqdb_command_requests[16];	/*  128;	0x1300..0x137F */
    /*
     * The rest of the descriptor block is unused.
     * As such we could use it for other things.
     */
    pdq_consumer_block_t pdqdb_consumer;	/*   64;	0x1380..0x13BF */
    void *pdqdb_receive_buffers[256];		/* 1024/2048;	0x13C0..0x17BF 0x13C0..0x1BBF */
    void *pdqdb_host_smt_buffers[64];		/*  256/ 512;	0x17C0..0x18BF 0x1BC0..0x1DBF */
    /*
     * The maximum command size is 512 so as long as thes
     * command is at least that long all will be fine.
     */
#if defined(__alpha) || defined(__alpha__)
    pdq_uint32_t pdqdb_command_pool[144];
#else
    pdq_uint32_t pdqdb_command_pool[464];
#endif
} pdq_descriptor_block_t;

typedef struct {
    /*