adwlib.h

基于组件方式开发操作系统的OSKIT源代码

	u_int8_t  tag_code;	  /* SCSI-2 Tag Queue Code: 00, 20-22. */
	u_int8_t  done_status;	  /* Completion status. */
	u_int8_t  scsi_status;	  /* SCSI status byte. */
	u_int8_t  host_status;	  /* Ucode host status. */

	u_int8_t  ux_sg_ix;       /* Ucode working SG variable. */
	u_int8_t  cdb[12];        /* SCSI command block. */
	u_int32_t sg_real_addr;   /* SG list physical address. */ 
	u_int32_t free_scsiq_link;/* Unused */
	u_int32_t ux_wk_data_cnt; /* Saved data count at disconnection. */
	u_int32_t scsi_req_baddr; /* Bus address of this request. */
	u_int32_t sg_block_index; /* sg_block tag (Unused) */
};

typedef enum {
	ACB_FREE		= 0x00,
	ACB_ACTIVE		= 0x01,
	ACB_RELEASE_SIMQ	= 0x02
} acb_state;

struct acb {
	struct		adw_scsi_req_q queue;
	bus_dmamap_t	dmamap;
	acb_state	state;
	union		ccb *ccb;
	struct		adw_sg_block* sg_blocks;
	bus_addr_t	sg_busaddr;
	struct		scsi_sense_data sense_data;
	SLIST_ENTRY(acb) links;
};

typedef struct {
	u_int16_t bios_init_dis    :1,/* don't act as initiator. */
	  	  bios_ext_trans   :1,/* > 1 GB support */
		  bios_more_2disk  :1,/* > 2 Disk Support */
		  bios_no_removable:1,/* don't support removables */
		  bios_cd_boot     :1,/* support bootable CD */
				   :1,
		  bios_multi_lun   :1,/* support multiple LUNs */
		  bios_message     :1,/* display BIOS message */
				   :1,
		  bios_reset_sb    :1,/* Reset SCSI bus during init. */
				   :1,
		  bios_quiet	   :1,/* No verbose initialization. */
		  bios_scsi_par_en :1,/* SCSI parity enabled */
				   :3;
} adw_bios_ctrl;

/*
 * EEPROM configuration format
 *
 * Field naming convention: 
 *
 *  *_enable indicates the field enables or disables the feature. The
 *  value is never reset.
 *
 *  *_able indicates both whether a feature should be enabled or disabled
 *  and whether a device is capable of the feature. At initialization
 *  this field may be set, but later if a device is found to be incapable
 *  of the feature, the field is cleared.
 *
 * Default values are maintained in a_init.c in the structure
 * Default_EEPROM_Config.
 */
struct adw_eeprom
{                              
	u_int16_t cfg_lsw;	/* 00 power up initialization */
#define		ADW_EEPROM_BIG_ENDIAN	0x8000
#define		ADW_EEPROM_BIOS_ENABLE	0x4000
#define		ADW_EEPROM_TERM_POL	0x2000

				/* bit 13 set - Term Polarity Control */
				/* bit 14 set - BIOS Enable */
				/* bit 15 set - Big Endian Mode */
	u_int16_t cfg_msw;	/* unused */
	u_int16_t disc_enable;
	u_int16_t wdtr_able;
	u_int16_t sdtr_able;
	u_int16_t start_motor;
	u_int16_t tagqng_able;
	u_int16_t bios_scan;
	u_int16_t scam_tolerant;
 
	u_int8_t  adapter_scsi_id;
	u_int8_t  bios_boot_delay;
 
	u_int8_t  scsi_reset_delay;
	u_int8_t  bios_id_lun;	/*    high nibble is lun */  
				/*    low nibble is scsi id */

	u_int8_t  termination;	/* 0 - automatic */
#define		ADW_EEPROM_TERM_AUTO 		0
#define		ADW_EEPROM_TERM_OFF		1
#define		ADW_EEPROM_TERM_HIGH_ON		2
#define		ADW_EEPROM_TERM_BOTH_ON		3

	u_int8_t  reserved1;	/*    reserved byte (not used) */                                  
	adw_bios_ctrl bios_ctrl;

	u_int16_t ultra_able;	/* 13 ULTRA speed able */ 
	u_int16_t reserved2;	/* 14 reserved */
	u_int8_t  max_host_qng;	/* 15 maximum host queuing */
	u_int8_t  max_dvc_qng;	/*    maximum per device queuing */
	u_int16_t dvc_cntl;	/* 16 control bit for driver */
	u_int16_t bug_fix;	/* 17 control bit for bug fix */
	u_int16_t serial_number[3];
	u_int16_t checksum;
	u_int8_t  oem_name[16];
	u_int16_t dvc_err_code;
	u_int16_t adv_err_code;
	u_int16_t adv_err_addr;
	u_int16_t saved_dvc_err_code;
	u_int16_t saved_adv_err_code;
	u_int16_t saved_adv_err_addr;
	u_int16_t num_of_err;
};

/* EEProm Addresses */
#define	ADW_EEP_DVC_CFG_BEGIN		0x00
#define	ADW_EEP_DVC_CFG_END	(offsetof(struct adw_eeprom, checksum)/2)
#define	ADW_EEP_DVC_CTL_BEGIN	(offsetof(struct adw_eeprom, oem_name)/2)
#define	ADW_EEP_MAX_WORD_ADDR	(sizeof(struct adw_eeprom)/2)

typedef enum {
	ADW_STATE_NORMAL	= 0x00,
	ADW_RESOURCE_SHORTAGE	= 0x01
} adw_state;

struct adw_softc
{
	bus_space_tag_t		  tag;
	bus_space_handle_t	  bsh;
	adw_state		  state;
	bus_dma_tag_t		  buffer_dmat;
	struct acb	         *acbs;
	LIST_HEAD(, ccb_hdr)	  pending_ccbs;
	SLIST_HEAD(, acb)	  free_acb_list;
	bus_dma_tag_t		  parent_dmat;
	bus_dma_tag_t		  acb_dmat;	/* dmat for our ccb array */
	bus_dmamap_t		  acb_dmamap;
	bus_dma_tag_t		  sg_dmat;	/* dmat for our sg maps */
	SLIST_HEAD(, sg_map_node) sg_maps;
	bus_addr_t		  acb_busbase;
	struct cam_path		 *path;
	struct cam_sim		 *sim;
	u_int			  max_acbs;
	u_int			  num_acbs;
	u_int			  initiator_id;
	u_int			  init_level;
	u_int			  unit;
	char*			  name;
	cam_status		  last_reset;	/* Last reset type */
	adw_bios_ctrl		  bios_ctrl;
	adw_idle_cmd_t		  idle_cmd;
	u_int			  idle_cmd_param;
	volatile int		  idle_command_cmp;
	u_int16_t		  user_wdtr;
	u_int16_t		  user_sdtr;
	u_int16_t		  user_ultra;
	u_int16_t		  user_tagenb;
	u_int16_t		  tagenb;
	u_int16_t		  user_discenb;
	u_int16_t		  serial_number[3];
};

extern struct adw_eeprom adw_default_eeprom;

#define adw_inb(adw, port)				\
	bus_space_read_1((adw)->tag, (adw)->bsh, port)
#define adw_inw(adw, port)				\
	bus_space_read_2((adw)->tag, (adw)->bsh, port)
#define adw_inl(adw, port)				\
	bus_space_read_4((adw)->tag, (adw)->bsh, port)

#define adw_outb(adw, port, value)			\
	bus_space_write_1((adw)->tag, (adw)->bsh, port, value)
#define adw_outw(adw, port, value)			\
	bus_space_write_2((adw)->tag, (adw)->bsh, port, value)
#define adw_outl(adw, port, value)			\
	bus_space_write_4((adw)->tag, (adw)->bsh, port, value)

static __inline const char*	adw_name(struct adw_softc *adw);
static __inline u_int	adw_lram_read_8(struct adw_softc *adw, u_int addr);
static __inline u_int	adw_lram_read_16(struct adw_softc *adw, u_int addr);
static __inline u_int	adw_lram_read_32(struct adw_softc *adw, u_int addr);
static __inline void	adw_lram_write_8(struct adw_softc *adw, u_int addr,
					 u_int value);
static __inline void	adw_lram_write_16(struct adw_softc *adw, u_int addr,
					  u_int value);
static __inline void	adw_lram_write_32(struct adw_softc *adw, u_int addr,
					  u_int value);

static __inline const char*
adw_name(struct adw_softc *adw)
{
	return (adw->name);
}

static __inline u_int
adw_lram_read_8(struct adw_softc *adw, u_int addr)
{
	adw_outw(adw, ADW_RAM_ADDR, addr);
	return (adw_inb(adw, ADW_RAM_DATA));
}

static __inline u_int
adw_lram_read_16(struct adw_softc *adw, u_int addr)
{
	adw_outw(adw, ADW_RAM_ADDR, addr);
	return (adw_inw(adw, ADW_RAM_DATA));
}

static __inline u_int
adw_lram_read_32(struct adw_softc *adw, u_int addr)
{
	u_int retval;

	adw_outw(adw, ADW_RAM_ADDR, addr);
	retval = adw_inw(adw, ADW_RAM_DATA);
	retval |= (adw_inw(adw, ADW_RAM_DATA) << 16);
	return (retval);
}

static __inline void
adw_lram_write_8(struct adw_softc *adw, u_int addr, u_int value)
{
	adw_outw(adw, ADW_RAM_ADDR, addr);
	adw_outb(adw, ADW_RAM_DATA, value);
}

static __inline void
adw_lram_write_16(struct adw_softc *adw, u_int addr, u_int value)
{
	adw_outw(adw, ADW_RAM_ADDR, addr);
	adw_outw(adw, ADW_RAM_DATA, value);
}

static __inline void
adw_lram_write_32(struct adw_softc *adw, u_int addr, u_int value)
{
	adw_outw(adw, ADW_RAM_ADDR, addr);
	adw_outw(adw, ADW_RAM_DATA, value);
	adw_outw(adw, ADW_RAM_DATA, value >> 16);
}

/* Intialization */
int		adw_find_signature(bus_space_tag_t tag, bus_space_handle_t bsh);
void		adw_reset_chip(struct adw_softc *adw);
u_int16_t	adw_eeprom_read(struct adw_softc *adw, struct adw_eeprom *buf);
void		adw_eeprom_write(struct adw_softc *adw, struct adw_eeprom *buf);
int		adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1);

/* Idle Commands */
void			adw_idle_cmd_send(struct adw_softc *adw, u_int cmd,
					  u_int parameter);
adw_idle_cmd_status_t	adw_idle_cmd_wait(struct adw_softc *adw);

/* SCSI Transaction Processing */
static __inline void	adw_send_acb(struct adw_softc *adw, struct acb *acb,
				     u_int32_t acb_baddr);

static __inline void
adw_send_acb(struct adw_softc *adw, struct acb *acb, u_int32_t acb_baddr)
{
	u_int next_queue;

	/* Determine the next free queue. */
	next_queue = adw_lram_read_8(adw, ADW_MC_HOST_NEXT_READY);
	next_queue = ADW_MC_RISC_Q_LIST_BASE
		   + (next_queue * ADW_MC_RISC_Q_LIST_SIZE);

	/*
	 * Write the physical address of the host Q to the free Q.
	 */
    	adw_lram_write_32(adw, next_queue + RQL_PHYADDR, acb_baddr);

	adw_lram_write_8(adw, next_queue + RQL_TID, acb->queue.target_id);

	/*
	 * Set the ADW_MC_HOST_NEXT_READY (0x128) microcode variable to
	 * the 'next_queue' request forward pointer.
	 *
	 * Do this *before* changing the 'next_queue' queue to QS_READY.
	 * After the state is changed to QS_READY 'RQL_FWD' will be changed
	 * by the microcode.
	 *
	 */
	adw_lram_write_8(adw, ADW_MC_HOST_NEXT_READY,
			 adw_lram_read_8(adw, next_queue + RQL_FWD));

	/*
	 * Change the state of 'next_queue' request from QS_FREE to
	 * QS_READY which will cause the microcode to pick it up and
	 * execute it.
	 *  
	 * Can't reference 'next_queue' after changing the request
	 * state to QS_READY. The microcode now owns the request.
	 */
	adw_lram_write_8(adw, next_queue + RQL_STATE, ADW_MC_QS_READY);
}
     
#endif /* _ADWLIB_H_ */