eni.h

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/*
 *
 * ===================================
 * HARP  |  Host ATM Research Platform
 * ===================================
 *
 *
 * This Host ATM Research Platform ("HARP") file (the "Software") is
 * made available by Network Computing Services, Inc. ("NetworkCS")
 * "AS IS".  NetworkCS does not provide maintenance, improvements or
 * support of any kind.
 *
 * NETWORKCS MAKES NO WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED,
 * INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY
 * AND FITNESS FOR A PARTICULAR PURPOSE, AS TO ANY ELEMENT OF THE
 * SOFTWARE OR ANY SUPPORT PROVIDED IN CONNECTION WITH THIS SOFTWARE.
 * In no event shall NetworkCS be responsible for any damages, including
 * but not limited to consequential damages, arising from or relating to
 * any use of the Software or related support.
 *
 * Copyright 1994-1998 Network Computing Services, Inc.
 *
 * Copies of this Software may be made, however, the above copyright
 * notice must be reproduced on all copies.
 *
 *	@(#) $Id: eni.h,v 1.1 1998/09/15 08:22:53 phk Exp $
 *
 */

/*
 * Efficient ENI Adapter Support
 *
 * Protocol and implementation definitions
 *
 */

#ifndef	_ENI_ENI_H
#define	_ENI_ENI_H

#include <pci/pcireg.h>
#include <pci/pcivar.h>

/*
 * Physical device name - used to configure HARP devices
 */
#ifndef	ENI_DEV_NAME
#define	ENI_DEV_NAME	"hea"		/* HARP Efficient ATM */
#endif

#define	ENI_MAX_UNITS	4

#define	ENI_IFF_MTU	9188
#define	ENI_MAX_VCI	1023		/* 0 - 1023 */
#define	ENI_MAX_VPI	0

#define	ENI_IFQ_MAXLEN	1000		/* rx/tx queue lengths */

#ifdef	BSD
/*
 * Size of small and large receive buffers
 */
#define	ENI_SMALL_BSIZE		64
#define	ENI_LARGE_BSIZE		MCLBYTES
#endif	/* BSD */

/*
 * ENI memory map offsets IN WORDS, not bytes
 *
 * The Efficient Adapter implements a 4 MB address space. The lower
 * 2 MB are used by bootprom (E)EPROM and by chipset registers such
 * as the MIDWAY and SUNI chips. The (upto) upper 2 MB is used for
 * RAM. Of the RAM, the lower 28 KB is used for fixed tables - the
 * VCI table, the RX and TX DMA queues, and the Service List queue.
 * Memory above the 28 KB range is available for RX and TX buffers.
 *
 * NOTE: Access to anything other then the (E)EPROM MUST be as a 32 bit
 * access. Also note that Efficient uses both byte addresses and word
 * addresses when describing offsets. BE CAREFUL or you'll get confused!
 */
/*
 * Size of memory space reserved for registers and expansion (e)eprom.
 */
#define	ENI_REG_SIZE	0x200000	/* Two megabytes */

#define	SUNI_OFFSET	0x008000	/* SUNI chip registers */
#define	MIDWAY_OFFSET	0x010000	/* MIDWAY chip registers */
#define	RAM_OFFSET	0x080000	/* Adapter RAM */
#define	VCITBL_OFFSET	0x080000	/* VCI Table offset */
#define	RXQUEUE_OFFSET	0x081000	/* RX DMA Queue offset */
#define	TXQUEUE_OFFSET	0x081400	/* TX DMA Queue offset */
#define	SVCLIST_OFFSET	0x081800	/* SVC List Queue offset */

#define	SEGBUF_BASE	0x007000	/* Base from start of RAM */

#define	DMA_LIST_SIZE	512		/* 1024 words / 2 words per entry */
#define	SVC_LIST_SIZE	1024		/* 1024 words / 1 word  per entry */

/*
 * Values for testing size of RAM on adapter
 *
 * Efficient has (at least) two different memory sizes available. One
 * is a client card which has either 128 KB or 512 KB RAM, the other
 * is a server card which has 2 MB RAM. The driver will size and test
 * the memory to correctly determine what's available.
 */
#define	MAX_ENI_MEM	0x200000	/* 2 MB - max. mem supported */
#define	TEST_STEP	0x000400	/* Look at 1 KB steps */
#define	TEST_PAT	0xA5A5A5A5	/* Test pattern */

/*
 * Values for memory allocator
 */
#define	ENI_BUF_PGSZ	1024		/* Allocation unit of buffers */
#define	ENI_BUF_NBIT	8		/* Number of bits to get from */
					/* min buffer (1KB) to max (128KB) */

/*
 * Values for allocating TX buffers
 */
#define	MAX_CLIENT_RAM	512		/* Most RAM a client card will have */
#define	TX_SMALL_BSIZE	32		/* Small buffer - 32KB */
#define	TX_LARGE_BSIZE	128		/* Large buffer - 128KB */

/*
 * Values for allocating RX buffers
 */
#define	RX_SIG_BSIZE	4		/* Signalling buffer - 4KB */
#define	RX_CLIENT_BSIZE	16		/* Client buffer - 16KB */
#define	RX_SERVER_BSIZE	32		/* Server buffer - 32KB */

/*
 * Adapter bases all addresses off of some power from 1KB. Thus, it
 * only needs to store the most sigificant bits and can drop the lower
 * 10 bits.
 */
#define	ENI_LOC_PREDIV	10		/* Bits location is shifted */
					/* Location is prescaled by 1KB */
					/* before use in various places */

#define	MIDWAY_DELAY	10		/* Time to wait for Midway finish */

/*
 * Define the MIDWAY register offsets and any interesting bits within
 * the register
 */
#define	MIDWAY_ID		0x00		/* ID/Reset register */
	#define	MIDWAY_RESET	0		/* iWrite of any value */
	#define	ID_SHIFT	27		/* Midway ID version */
	#define	ID_MASK		0x1F		/* ID mask */
	#define	MID_SHIFT	7		/* Mother board ID */
	#define	MID_MASK	0x7		/* MID mask */
	#define	DID_SHIFT	0		/* Daughter board ID */
	#define	DID_MASK	0x1F		/* DID mask */
	/*
	 * Efficient defines the following IDs for their adapters:
	 * 0x420/0x620 - SONET MMF, client memory size
	 * 0x430/0x630 - SONET MMF, server memory size
	 * 0x424/0x624 - UTP-5, client memory size
	 * 0x434/0x634 - UTP-5, server memory size
	 */
	#define	MEDIA_MASK	0x04		/* Mask off UTP-5/MMF media */

#define	MIDWAY_ISA		0x01		/* Interrupt Status Ack. */
						/* Reading this register */
						/* also acknowledges the */
						/* posted interrupt(s) */

#define	MIDWAY_IS		0x02		/* Interrupt Status */
						/* Reading this register */
						/* does NOT acknowledge the */
						/* posted interrupt(s) */
	/* Interrupt names */
	#define	ENI_INT_STAT		0x00000001
	#define	ENI_INT_SUNI		0x00000002
	#define	ENI_INT_SERVICE		0x00000004
	#define	ENI_INT_TX_DMA		0x00000008
	#define	ENI_INT_RX_DMA		0x00000010
	#define	ENI_INT_DMA_ERR		0x00000020
	#define	ENI_INT_DMA_LERR	0x00000040
	#define	ENI_INT_IDEN		0x00000080
	#define	ENI_INT_DMA_OVFL	0x00000100
	#define	ENI_INT_TX_MASK		0x0001FE00

#define	MIDWAY_IE		0x03		/* Interrupt Enable register */
	/* Interrupt enable bits are the same as the Interrupt names */

#define	MIDWAY_MASTER		0x04		/* Master Control */
	/* Master control bits */
	#define	ENI_M_WAIT500	0x00000001	/* Disable interrupts .5 ms */
	#define	ENI_M_WAIT1	0x00000002	/* Disable interrupts 1 ms */
	#define	ENI_M_RXENABLE	0x00000004	/* Enable RX engine */
	#define	ENI_M_TXENABLE	0x00000008	/* Enable TX engine */
	#define	ENI_M_DMAENABLE	0x00000010	/* Enable DMA */
	#define	ENI_M_TXLOCK	0x00000020	/* 0: Streaming, 1: Lock */
	#define	ENI_M_INTSEL	0x000001C0	/* Int Select mask */
	#define	ENI_ISEL_SHIFT	6		/* Bits to shift ISEL value */

#define	MIDWAY_STAT		0x05		/* Statistics register */

#define	MIDWAY_SVCWR		0x06		/* Svc List write pointer */
	#define	SVC_SIZE_MASK	0x3FF		/* Valid bits in svc pointer */

#define	MIDWAY_DMAADDR		0x07		/* Current virtual DMA addr */

#define	MIDWAY_RX_WR		0x08		/* Write ptr to RX DMA queue */

#define	MIDWAY_RX_RD		0x09		/* Read ptr to RX DMA queue */

#define	MIDWAY_TX_WR		0x0A		/* Write ptr to TX DMA queue */

#define	MIDWAY_TX_RD		0x0B		/* Read ptr to TX DMA queue */

/*
 * Registers 0x0C - 0x0F are unused
 */

/*
 * MIDWAY supports 8 transmit channels. Each channel has 3 registers
 * to control operation. Each new channel starts on N * 4 set. Thus,
 * channel 0 uses register 0x10 - 0x13, channel 1 uses 0x14 - 0x17, etc.
 * Register 0x13 + N * 4 is unused.
 */

#define	MIDWAY_TXPLACE		0x10		/* Channel N TX location */
	#define	TXSIZE_SHIFT	11		/* Bits to shift size by */
	#define	TX_PLACE_MASK	0x7FF		/* Valid bits in TXPLACE */

#define	MIDWAY_RDPTR		0x11		/* Channel N Read ptr */

#define	MIDWAY_DESCR		0x12		/* Channel N Descr ptr */

/*
 * Register 0x30 on up are unused
 */

/*
 * Part of PCI configuration registers but not defined in <pci/pcireg.h>
 */
#define	PCI_CONTROL_REG		0x60
#define	ENDIAN_SWAP_DMA		0x80		/* Enable endian swaps on DMA */

/*
 * The Efficient adapter references adapter RAM through the use of
 * location and size values. Eight sizes are defined. When allocating
 * buffers, there size must be rounded up to the next size which will
 * hold the requested size. Buffers are allocated on 'SIZE' boundaries.
 * See eni_buffer.c for more info.
 */

/*