ispreg.h

基于组件方式开发操作系统的OSKIT源代码

/* PROCESSOR STATUS REGISTER */
#define	RISC_PSR_FORCE_TRUE		0x8000
#define	RISC_PSR_LOOP_COUNT_DONE	0x4000
#define	RISC_PSR_RISC_INT		0x2000
#define	RISC_PSR_TIMER_ROLLOVER		0x1000
#define	RISC_PSR_ALU_OVERFLOW		0x0800
#define	RISC_PSR_ALU_MSB		0x0400
#define	RISC_PSR_ALU_CARRY		0x0200
#define	RISC_PSR_ALU_ZERO		0x0100

#define	RISC_PSR_PCI_ULTRA		0x0080
#define	RISC_PSR_SBUS_ULTRA		0x0020

#define	RISC_PSR_DMA_INT		0x0010
#define	RISC_PSR_SXP_INT		0x0008
#define	RISC_PSR_HOST_INT		0x0004
#define	RISC_PSR_INT_PENDING		0x0002
#define	RISC_PSR_FORCE_FALSE  		0x0001


/* Host Command and Control */
#define	HCCR_CMD_NOP			0x0000	/* NOP */
#define	HCCR_CMD_RESET			0x1000	/* Reset RISC */
#define	HCCR_CMD_PAUSE			0x2000	/* Pause RISC */
#define	HCCR_CMD_RELEASE		0x3000	/* Release Paused RISC */
#define	HCCR_CMD_STEP			0x4000	/* Single Step RISC */
#define	HCCR_CMD_SET_HOST_INT		0x5000	/* Set Host Interrupt */
#define	HCCR_CMD_CLEAR_HOST_INT		0x6000	/* Clear Host Interrupt */
#define	HCCR_CMD_CLEAR_RISC_INT		0x7000	/* Clear RISC interrupt */
#define	HCCR_CMD_BREAKPOINT		0x8000	/* Change breakpoint enables */
#define	PCI_HCCR_CMD_BIOS		0x9000	/* Write BIOS (disable) */
#define	PCI_HCCR_CMD_PARITY		0xA000	/* Write parity enable */
#define	PCI_HCCR_CMD_PARITY_ERR		0xE000	/* Generate parity error */
#define	HCCR_CMD_TEST_MODE		0xF000	/* Set Test Mode */

#define	ISP2100_HCCR_PARITY_ENABLE_2	0x0400
#define	ISP2100_HCCR_PARITY_ENABLE_1	0x0200
#define	ISP2100_HCCR_PARITY_ENABLE_0	0x0100
#define	ISP2100_HCCR_PARITY		0x0001

#define	PCI_HCCR_PARITY			0x0400	/* Parity error flag */
#define	PCI_HCCR_PARITY_ENABLE_1	0x0200	/* Parity enable bank 1 */
#define	PCI_HCCR_PARITY_ENABLE_0	0x0100	/* Parity enable bank 0 */

#define	HCCR_HOST_INT			0x0080	/* R  : Host interrupt set */
#define	HCCR_RESET			0x0040	/* R  : reset in progress */
#define	HCCR_PAUSE			0x0020	/* R  : RISC paused */

#define	PCI_HCCR_BIOS			0x0001	/*  W : BIOS enable */

/*
 * NVRAM Definitions (PCI cards only)
 */

#define	ISPBSMX(c, byte, shift, mask)	\
	(((c)[(byte)] >> (shift)) & (mask))
/*
 * Qlogic 1020/1040 NVRAM is an array of 128 bytes.
 *
 * Some portion of the front of this is for general host adapter properties
 * This is followed by an array of per-target parameters, and is tailed off
 * with a checksum xor byte at offset 127. For non-byte entities data is
 * stored in Little Endian order.
 */

#define	ISP_NVRAM_SIZE	128

#define	ISP_NVRAM_VERSION(c)			(c)[4]
#define	ISP_NVRAM_FIFO_THRESHOLD(c)		ISPBSMX(c, 5, 0, 0x03)
#define	ISP_NVRAM_BIOS_DISABLE(c)		ISPBSMX(c, 5, 2, 0x01)
#define	ISP_NVRAM_HBA_ENABLE(c)			ISPBSMX(c, 5, 3, 0x01)
#define	ISP_NVRAM_INITIATOR_ID(c)		ISPBSMX(c, 5, 4, 0x0f)
#define	ISP_NVRAM_BUS_RESET_DELAY(c)		(c)[6]
#define	ISP_NVRAM_BUS_RETRY_COUNT(c)		(c)[7]
#define	ISP_NVRAM_BUS_RETRY_DELAY(c)		(c)[8]
#define	ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c)	ISPBSMX(c, 9, 0, 0x0f)
#define	ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c)	ISPBSMX(c, 9, 4, 0x01)
#define	ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c)	ISPBSMX(c, 9, 5, 0x01)
#define	ISP_NVRAM_DATA_DMA_BURST_ENABLE(c)	ISPBSMX(c, 9, 6, 0x01)
#define	ISP_NVRAM_CMD_DMA_BURST_ENABLE(c)	ISPBSMX(c, 9, 7, 0x01)
#define	ISP_NVRAM_TAG_AGE_LIMIT(c)		(c)[10]
#define	ISP_NVRAM_LOWTRM_ENABLE(c)		ISPBSMX(c, 11, 0, 0x01)
#define	ISP_NVRAM_HITRM_ENABLE(c)		ISPBSMX(c, 11, 1, 0x01)
#define	ISP_NVRAM_PCMC_BURST_ENABLE(c)		ISPBSMX(c, 11, 2, 0x01)
#define	ISP_NVRAM_ENABLE_60_MHZ(c)		ISPBSMX(c, 11, 3, 0x01)
#define	ISP_NVRAM_SCSI_RESET_DISABLE(c)		ISPBSMX(c, 11, 4, 0x01)
#define	ISP_NVRAM_ENABLE_AUTO_TERM(c)		ISPBSMX(c, 11, 5, 0x01)
#define	ISP_NVRAM_FIFO_THRESHOLD_128(c)		ISPBSMX(c, 11, 6, 0x01)
#define	ISP_NVRAM_AUTO_TERM_SUPPORT(c)		ISPBSMX(c, 11, 7, 0x01)
#define	ISP_NVRAM_SELECTION_TIMEOUT(c)		(((c)[12]) | ((c)[13] << 8))
#define	ISP_NVRAM_MAX_QUEUE_DEPTH(c)		(((c)[14]) | ((c)[15] << 8))
#define	ISP_NVRAM_SCSI_BUS_SIZE(c)		ISPBSMX(c, 16, 0, 0x01)
#define	ISP_NVRAM_SCSI_BUS_TYPE(c)		ISPBSMX(c, 16, 1, 0x01)
#define	ISP_NVRAM_ADAPTER_CLK_SPEED(c)		ISPBSMX(c, 16, 2, 0x01)
#define	ISP_NVRAM_SOFT_TERM_SUPPORT(c)		ISPBSMX(c, 16, 3, 0x01)
#define	ISP_NVRAM_FLASH_ONBOARD(c)		ISPBSMX(c, 16, 4, 0x01)
#define	ISP_NVRAM_FAST_MTTR_ENABLE(c)		ISPBSMX(c, 22, 0, 0x01)

#define	ISP_NVRAM_TARGOFF			28
#define	ISP_NVARM_TARGSIZE			6
#define	_IxT(tgt, tidx)			\
	(ISP_NVRAM_TARGOFF + (ISP_NVARM_TARGSIZE * (tgt)) + (tidx))
#define	ISP_NVRAM_TGT_RENEG(c, t)		ISPBSMX(c, _IxT(t, 0), 0, 0x01)
#define	ISP_NVRAM_TGT_QFRZ(c, t)		ISPBSMX(c, _IxT(t, 0), 1, 0x01)
#define	ISP_NVRAM_TGT_ARQ(c, t)			ISPBSMX(c, _IxT(t, 0), 2, 0x01)
#define	ISP_NVRAM_TGT_TQING(c, t)		ISPBSMX(c, _IxT(t, 0), 3, 0x01)
#define	ISP_NVRAM_TGT_SYNC(c, t)		ISPBSMX(c, _IxT(t, 0), 4, 0x01)
#define	ISP_NVRAM_TGT_WIDE(c, t)		ISPBSMX(c, _IxT(t, 0), 5, 0x01)
#define	ISP_NVRAM_TGT_PARITY(c, t)		ISPBSMX(c, _IxT(t, 0), 6, 0x01)
#define	ISP_NVRAM_TGT_DISC(c, t)		ISPBSMX(c, _IxT(t, 0), 7, 0x01)
#define	ISP_NVRAM_TGT_EXEC_THROTTLE(c, t)	ISPBSMX(c, _IxT(t, 1), 0, 0xff)
#define	ISP_NVRAM_TGT_SYNC_PERIOD(c, t)		ISPBSMX(c, _IxT(t, 2), 0, 0xff)
#define	ISP_NVRAM_TGT_SYNC_OFFSET(c, t)		ISPBSMX(c, _IxT(t, 3), 0, 0x0f)
#define	ISP_NVRAM_TGT_DEVICE_ENABLE(c, t)	ISPBSMX(c, _IxT(t, 3), 4, 0x01)
#define	ISP_NVRAM_TGT_LUN_DISABLE(c, t)		ISPBSMX(c, _IxT(t, 3), 5, 0x01)

/*
 * Qlogic 1080/1240 NVRAM is an array of 256 bytes.
 *
 * Some portion of the front of this is for general host adapter properties
 * This is followed by an array of per-target parameters, and is tailed off
 * with a checksum xor byte at offset 256. For non-byte entities data is
 * stored in Little Endian order.
 */

#define	ISP1080_NVRAM_SIZE	256

#define	ISP1080_NVRAM_VERSION(c)		ISP_NVRAM_VERSION(c)

/* Offset 5 */
/*
	uint8_t bios_configuration_mode     :2;
	uint8_t bios_disable                :1;
	uint8_t selectable_scsi_boot_enable :1;
	uint8_t cd_rom_boot_enable          :1;
	uint8_t disable_loading_risc_code   :1;
	uint8_t enable_64bit_addressing     :1;
	uint8_t unused_7                    :1;
 */

/* Offsets 6, 7 */
/*
        uint8_t boot_lun_number    :5;
        uint8_t scsi_bus_number    :1;
        uint8_t unused_6           :1;
        uint8_t unused_7           :1;
        uint8_t boot_target_number :4;
        uint8_t unused_12          :1;
        uint8_t unused_13          :1;
        uint8_t unused_14          :1;
        uint8_t unused_15          :1;
 */

#define	ISP1080_NVRAM_HBA_ENABLE(c)			ISPBSMX(c, 16, 3, 0x01)

#define	ISP1080_NVRAM_BURST_ENABLE(c)			ISPBSMX(c, 16, 1, 0x01)
#define	ISP1080_NVRAM_FIFO_THRESHOLD(c)			ISPBSMX(c, 16, 4, 0x0f)

#define	ISP1080_NVRAM_AUTO_TERM_SUPPORT(c)		ISPBSMX(c, 17, 7, 0x01)
#define	ISP1080_NVRAM_BUS0_TERM_MODE(c)			ISPBSMX(c, 17, 0, 0x03)
#define	ISP1080_NVRAM_BUS1_TERM_MODE(c)			ISPBSMX(c, 17, 2, 0x03)

#define	ISP1080_ISP_PARAMETER(c)			\
	(((c)[18]) | ((c)[19] << 8))

#define	ISP1080_FAST_POST				ISPBSMX(c, 20, 0, 0x01)
#define	ISP1080_REPORT_LVD_TRANSITION			ISPBSMX(c, 20, 1, 0x01)

#define	ISP1080_BUS1_OFF				112

#define	ISP1080_NVRAM_INITIATOR_ID(c, b)		\
	ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 24, 0, 0x0f)
#define	ISP1080_NVRAM_BUS_RESET_DELAY(c, b)		\
	(c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 25]
#define	ISP1080_NVRAM_BUS_RETRY_COUNT(c, b)		\
	(c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 26]
#define	ISP1080_NVRAM_BUS_RETRY_DELAY(c, b)		\
	(c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 27]

#define	ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME(c, b)	\
	ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 0, 0x0f)
#define	ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION(c, b)	\
	ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 4, 0x01)
#define	ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION(c, b)	\
	ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 5, 0x01)
#define	ISP1080_NVRAM_SELECTION_TIMEOUT(c, b)		\
	(((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 30]) | \
	((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 31] << 8))
#define	ISP1080_NVRAM_MAX_QUEUE_DEPTH(c, b)		\
	(((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 32]) | \
	((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 33] << 8))

#define	ISP1080_NVRAM_TARGOFF(b)		\
	((b == 0)? 40: (40 + ISP1080_BUS1_OFF))
#define	ISP1080_NVRAM_TARGSIZE			6
#define	_IxT8(tgt, tidx, b)			\
	(ISP1080_NVRAM_TARGOFF((b)) + (ISP1080_NVRAM_TARGSIZE * (tgt)) + (tidx))

#define	ISP1080_NVRAM_TGT_RENEG(c, t, b)		\
	ISPBSMX(c, _IxT8(t, 0, (b)), 0, 0x01)
#define	ISP1080_NVRAM_TGT_QFRZ(c, t, b)			\
	ISPBSMX(c, _IxT8(t, 0, (b)), 1, 0x01)
#define	ISP1080_NVRAM_TGT_ARQ(c, t, b)			\
	ISPBSMX(c, _IxT8(t, 0, (b)), 2, 0x01)
#define	ISP1080_NVRAM_TGT_TQING(c, t, b)		\
	ISPBSMX(c, _IxT8(t, 0, (b)), 3, 0x01)
#define	ISP1080_NVRAM_TGT_SYNC(c, t, b)			\
	ISPBSMX(c, _IxT8(t, 0, (b)), 4, 0x01)
#define	ISP1080_NVRAM_TGT_WIDE(c, t, b)			\
	ISPBSMX(c, _IxT8(t, 0, (b)), 5, 0x01)
#define	ISP1080_NVRAM_TGT_PARITY(c, t, b)		\
	ISPBSMX(c, _IxT8(t, 0, (b)), 6, 0x01)
#define	ISP1080_NVRAM_TGT_DISC(c, t, b)			\
	ISPBSMX(c, _IxT8(t, 0, (b)), 7, 0x01)
#define	ISP1080_NVRAM_TGT_EXEC_THROTTLE(c, t, b)	\
	ISPBSMX(c, _IxT8(t, 1, (b)), 0, 0xff)
#define	ISP1080_NVRAM_TGT_SYNC_PERIOD(c, t, b)		\
	ISPBSMX(c, _IxT8(t, 2, (b)), 0, 0xff)
#define	ISP1080_NVRAM_TGT_SYNC_OFFSET(c, t, b)		\
	ISPBSMX(c, _IxT8(t, 3, (b)), 0, 0x0f)
#define	ISP1080_NVRAM_TGT_DEVICE_ENABLE(c, t, b)	\
	ISPBSMX(c, _IxT8(t, 3, (b)), 4, 0x01)
#define	ISP1080_NVRAM_TGT_LUN_DISABLE(c, t, b)		\
	ISPBSMX(c, _IxT8(t, 3, (b)), 5, 0x01)

/*
 * Qlogic 2XXX NVRAM is an array of 256 bytes.
 *
 * Some portion of the front of this is for general RISC engine parameters,
 * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command.
 *
 * This is followed by some general host adapter parameters, and ends with
 * a checksum xor byte at offset 255. For non-byte entities data is stored
 * in Little Endian order.
 */
#define	ISP2100_NVRAM_SIZE	256
/* ISP_NVRAM_VERSION is in same overall place */
#define	ISP2100_NVRAM_RISCVER(c)		(c)[6]
#define	ISP2100_NVRAM_OPTIONS(c)		(c)[8]
#define	ISP2100_NVRAM_MAXFRAMELENGTH(c)		(((c)[10]) | ((c)[11] << 8))
#define	ISP2100_NVRAM_MAXIOCBALLOCATION(c)	(((c)[12]) | ((c)[13] << 8))
#define	ISP2100_NVRAM_EXECUTION_THROTTLE(c)	(((c)[14]) | ((c)[15] << 8))
#define	ISP2100_NVRAM_RETRY_COUNT(c)		(c)[16]
#define	ISP2100_NVRAM_RETRY_DELAY(c)		(c)[17]

#define	ISP2100_NVRAM_NODE_NAME(c)	(\
		(((u_int64_t)(c)[18]) << 56) | \
		(((u_int64_t)(c)[19]) << 48) | \
		(((u_int64_t)(c)[20]) << 40) | \
		(((u_int64_t)(c)[21]) << 32) | \
		(((u_int64_t)(c)[22]) << 24) | \
		(((u_int64_t)(c)[23]) << 16) | \
		(((u_int64_t)(c)[24]) <<  8) | \
		(((u_int64_t)(c)[25]) <<  0))
#define	ISP2100_NVRAM_HARDLOOPID(c)		(c)[26]

#define	ISP2100_NVRAM_HBA_OPTIONS(c)		(c)[70]
#define	ISP2100_NVRAM_HBA_DISABLE(c)		ISPBSMX(c, 70, 0, 0x01)
#define	ISP2100_NVRAM_BIOS_DISABLE(c)		ISPBSMX(c, 70, 1, 0x01)
#define	ISP2100_NVRAM_LUN_DISABLE(c)		ISPBSMX(c, 70, 2, 0x01)
#define	ISP2100_NVRAM_ENABLE_SELECT_BOOT(c)	ISPBSMX(c, 70, 3, 0x01)
#define	ISP2100_NVRAM_DISABLE_CODELOAD(c)	ISPBSMX(c, 70, 4, 0x01)
#define	ISP2100_NVRAM_SET_CACHELINESZ(c)	ISPBSMX(c, 70, 5, 0x01)

#define	ISP2100_NVRAM_BOOT_NODE_NAME(c)	(\
		(((u_int64_t)(c)[72]) << 56) | \
		(((u_int64_t)(c)[73]) << 48) | \
		(((u_int64_t)(c)[74]) << 40) | \
		(((u_int64_t)(c)[75]) << 32) | \
		(((u_int64_t)(c)[76]) << 24) | \
		(((u_int64_t)(c)[77]) << 16) | \
		(((u_int64_t)(c)[78]) <<  8) | \
		(((u_int64_t)(c)[79]) <<  0))

#define	ISP2100_NVRAM_BOOT_LUN(c)		(c)[80]

#endif	/* _ISPREG_H */