if_ax.c

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/*
 * Copyright (c) 1997, 1998, 1999
 *	Bill Paul <[e-mail]>.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by Bill Paul.
 * 4. Neither the name of the author nor the names of any co-contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 * THE POSSIBILITY OF SUCH DAMAGE.
 *
 *	$Id: if_ax.c,v 1.3.2.3 1999/04/08 17:45:22 wpaul Exp $
 */

/*
 * ASIX AX88140A and AX88141 fast ethernet PCI NIC driver.
 *
 * Written by Bill Paul <[e-mail]>
 * Electrical Engineering Department
 * Columbia University, New York City
 */

/*
 * The ASIX Electronics AX88140A is still another DEC 21x4x clone. It's
 * a reasonably close copy of the tulip, except for the receiver filter
 * programming. Where the DEC chip has a special setup frame that
 * needs to be downloaded into the transmit DMA engine, the ASIX chip
 * has a less complicated setup frame which is written into one of
 * the registers.
 */

#include "bpfilter.h"

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/sockio.h>
#include <sys/mbuf.h>
#include <sys/malloc.h>
#include <sys/kernel.h>
#include <sys/socket.h>

#include <net/if.h>
#include <net/if_arp.h>
#include <net/ethernet.h>
#include <net/if_dl.h>
#include <net/if_media.h>

#if NBPFILTER > 0
#include <net/bpf.h>
#endif

#include <vm/vm.h>              /* for vtophys */
#include <vm/pmap.h>            /* for vtophys */
#include <machine/clock.h>      /* for DELAY */
#include <machine/bus_pio.h>
#include <machine/bus_memio.h>
#include <machine/bus.h>

#include <pci/pcireg.h>
#include <pci/pcivar.h>

#define AX_USEIOSPACE

/* #define AX_BACKGROUND_AUTONEG */

#include <pci/if_axreg.h>

#ifndef lint
static const char rcsid[] =
	"$Id: if_ax.c,v 1.3.2.3 1999/04/08 17:45:22 wpaul Exp $";
#endif

/*
 * Various supported device vendors/types and their names.
 */
static struct ax_type ax_devs[] = {
	{ AX_VENDORID, AX_DEVICEID_AX88140A,
		"ASIX AX88140A 10/100BaseTX" },
	{ AX_VENDORID, AX_DEVICEID_AX88140A,
		"ASIX AX88141 10/100BaseTX" },
	{ 0, 0, NULL }
};

/*
 * Various supported PHY vendors/types and their names. Note that
 * this driver will work with pretty much any MII-compliant PHY,
 * so failure to positively identify the chip is not a fatal error.
 */

static struct ax_type ax_phys[] = {
	{ TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" },
	{ TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" },
	{ NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"},
	{ LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" }, 
	{ INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" },
	{ SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" },
	{ 0, 0, "<MII-compliant physical interface>" }
};

static unsigned long ax_count = 0;
static const char *ax_probe	__P((pcici_t, pcidi_t));
static void ax_attach		__P((pcici_t, int));

static int ax_newbuf		__P((struct ax_softc *,
						struct ax_chain_onefrag *));
static int ax_encap		__P((struct ax_softc *, struct ax_chain *,
						struct mbuf *));

static void ax_rxeof		__P((struct ax_softc *));
static void ax_rxeoc		__P((struct ax_softc *));
static void ax_txeof		__P((struct ax_softc *));
static void ax_txeoc		__P((struct ax_softc *));
static void ax_intr		__P((void *));
static void ax_start		__P((struct ifnet *));
static int ax_ioctl		__P((struct ifnet *, u_long, caddr_t));
static void ax_init		__P((void *));
static void ax_stop		__P((struct ax_softc *));
static void ax_watchdog		__P((struct ifnet *));
static void ax_shutdown		__P((int, void *));
static int ax_ifmedia_upd	__P((struct ifnet *));
static void ax_ifmedia_sts	__P((struct ifnet *, struct ifmediareq *));

static void ax_delay		__P((struct ax_softc *));
static void ax_eeprom_idle	__P((struct ax_softc *));
static void ax_eeprom_putbyte	__P((struct ax_softc *, int));
static void ax_eeprom_getword	__P((struct ax_softc *, int, u_int16_t *));
static void ax_read_eeprom	__P((struct ax_softc *, caddr_t, int,
							int, int));

static void ax_mii_writebit	__P((struct ax_softc *, int));
static int ax_mii_readbit	__P((struct ax_softc *));
static void ax_mii_sync		__P((struct ax_softc *));
static void ax_mii_send		__P((struct ax_softc *, u_int32_t, int));
static int ax_mii_readreg	__P((struct ax_softc *, struct ax_mii_frame *));
static int ax_mii_writereg	__P((struct ax_softc *, struct ax_mii_frame *));
static u_int16_t ax_phy_readreg	__P((struct ax_softc *, int));
static void ax_phy_writereg	__P((struct ax_softc *, int, int));

static void ax_autoneg_xmit	__P((struct ax_softc *));
static void ax_autoneg_mii	__P((struct ax_softc *, int, int));
static void ax_setmode_mii	__P((struct ax_softc *, int));
static void ax_setmode		__P((struct ax_softc *, int, int));
static void ax_getmode_mii	__P((struct ax_softc *));
static void ax_setcfg		__P((struct ax_softc *, int));
static u_int32_t ax_calchash	__P((caddr_t));
static void ax_setmulti		__P((struct ax_softc *));
static void ax_reset		__P((struct ax_softc *));
static int ax_list_rx_init	__P((struct ax_softc *));
static int ax_list_tx_init	__P((struct ax_softc *));

#define AX_SETBIT(sc, reg, x)				\
	CSR_WRITE_4(sc, reg,				\
		CSR_READ_4(sc, reg) | x)

#define AX_CLRBIT(sc, reg, x)				\
	CSR_WRITE_4(sc, reg,				\
		CSR_READ_4(sc, reg) & ~x)

#define SIO_SET(x)					\
	CSR_WRITE_4(sc, AX_SIO,				\
		CSR_READ_4(sc, AX_SIO) | x)

#define SIO_CLR(x)					\
	CSR_WRITE_4(sc, AX_SIO,				\
		CSR_READ_4(sc, AX_SIO) & ~x)

static void ax_delay(sc)
	struct ax_softc		*sc;
{
	int			idx;

	for (idx = (300 / 33) + 1; idx > 0; idx--)
		CSR_READ_4(sc, AX_BUSCTL);
}

static void ax_eeprom_idle(sc)
	struct ax_softc		*sc;
{
	register int		i;

	CSR_WRITE_4(sc, AX_SIO, AX_SIO_EESEL);
	ax_delay(sc);
	AX_SETBIT(sc, AX_SIO,  AX_SIO_ROMCTL_READ);
	ax_delay(sc);
	AX_SETBIT(sc, AX_SIO, AX_SIO_EE_CS);
	ax_delay(sc);
	AX_SETBIT(sc, AX_SIO, AX_SIO_EE_CLK);
	ax_delay(sc);

	for (i = 0; i < 25; i++) {
		AX_CLRBIT(sc, AX_SIO, AX_SIO_EE_CLK);
		ax_delay(sc);
		AX_SETBIT(sc, AX_SIO, AX_SIO_EE_CLK);
		ax_delay(sc);
	}

	AX_CLRBIT(sc, AX_SIO, AX_SIO_EE_CLK);
	ax_delay(sc);
	AX_CLRBIT(sc, AX_SIO, AX_SIO_EE_CS);
	ax_delay(sc);
	CSR_WRITE_4(sc, AX_SIO, 0x00000000);

	return;
}

/*
 * Send a read command and address to the EEPROM, check for ACK.
 */
static void ax_eeprom_putbyte(sc, addr)
	struct ax_softc		*sc;
	int			addr;
{
	register int		d, i;

	d = addr | AX_EECMD_READ;

	/*
	 * Feed in each bit and stobe the clock.
	 */
	for (i = 0x400; i; i >>= 1) {
		if (d & i) {
			SIO_SET(AX_SIO_EE_DATAIN);
		} else {
			SIO_CLR(AX_SIO_EE_DATAIN);
		}
		ax_delay(sc);
		SIO_SET(AX_SIO_EE_CLK);
		ax_delay(sc);
		SIO_CLR(AX_SIO_EE_CLK);
		ax_delay(sc);
	}

	return;
}

/*
 * Read a word of data stored in the EEPROM at address 'addr.'
 */
static void ax_eeprom_getword(sc, addr, dest)
	struct ax_softc		*sc;
	int			addr;
	u_int16_t		*dest;
{
	register int		i;
	u_int16_t		word = 0;

	/* Force EEPROM to idle state. */
	ax_eeprom_idle(sc);

	/* Enter EEPROM access mode. */
	CSR_WRITE_4(sc, AX_SIO, AX_SIO_EESEL);
	ax_delay(sc);
	AX_SETBIT(sc, AX_SIO,  AX_SIO_ROMCTL_READ);
	ax_delay(sc);
	AX_SETBIT(sc, AX_SIO, AX_SIO_EE_CS);
	ax_delay(sc);
	AX_SETBIT(sc, AX_SIO, AX_SIO_EE_CLK);
	ax_delay(sc);

	/*
	 * Send address of word we want to read.
	 */
	ax_eeprom_putbyte(sc, addr);

	/*
	 * Start reading bits from EEPROM.
	 */
	for (i = 0x8000; i; i >>= 1) {
		SIO_SET(AX_SIO_EE_CLK);
		ax_delay(sc);
		if (CSR_READ_4(sc, AX_SIO) & AX_SIO_EE_DATAOUT)
			word |= i;
		ax_delay(sc);
		SIO_CLR(AX_SIO_EE_CLK);
		ax_delay(sc);
	}

	/* Turn off EEPROM access mode. */
	ax_eeprom_idle(sc);

	*dest = word;

	return;
}

/*
 * Read a sequence of words from the EEPROM.
 */
static void ax_read_eeprom(sc, dest, off, cnt, swap)
	struct ax_softc		*sc;
	caddr_t			dest;
	int			off;
	int			cnt;
	int			swap;
{
	int			i;
	u_int16_t		word = 0, *ptr;

	for (i = 0; i < cnt; i++) {
		ax_eeprom_getword(sc, off + i, &word);
		ptr = (u_int16_t *)(dest + (i * 2));
		if (swap)
			*ptr = ntohs(word);
		else
			*ptr = word;
	}

	return;
}

/*
 * Write a bit to the MII bus.
 */
static void ax_mii_writebit(sc, bit)
	struct ax_softc		*sc;
	int			bit;
{
	if (bit)
		CSR_WRITE_4(sc, AX_SIO, AX_SIO_ROMCTL_WRITE|AX_SIO_MII_DATAOUT);
	else
		CSR_WRITE_4(sc, AX_SIO, AX_SIO_ROMCTL_WRITE);

	AX_SETBIT(sc, AX_SIO, AX_SIO_MII_CLK);
	AX_CLRBIT(sc, AX_SIO, AX_SIO_MII_CLK);

	return;
}

/*
 * Read a bit from the MII bus.
 */
static int ax_mii_readbit(sc)
	struct ax_softc		*sc;
{
	CSR_WRITE_4(sc, AX_SIO, AX_SIO_ROMCTL_READ|AX_SIO_MII_DIR);
	CSR_READ_4(sc, AX_SIO);
	AX_SETBIT(sc, AX_SIO, AX_SIO_MII_CLK);
	AX_CLRBIT(sc, AX_SIO, AX_SIO_MII_CLK);
	if (CSR_READ_4(sc, AX_SIO) & AX_SIO_MII_DATAIN)
		return(1);

	return(0);
}

/*
 * Sync the PHYs by setting data bit and strobing the clock 32 times.
 */
static void ax_mii_sync(sc)
	struct ax_softc		*sc;
{
	register int		i;

	CSR_WRITE_4(sc, AX_SIO, AX_SIO_ROMCTL_WRITE);

	for (i = 0; i < 32; i++)
		ax_mii_writebit(sc, 1);

	return;
}

/*
 * Clock a series of bits through the MII.
 */
static void ax_mii_send(sc, bits, cnt)
	struct ax_softc		*sc;
	u_int32_t		bits;
	int			cnt;
{
	int			i;

	for (i = (0x1 << (cnt - 1)); i; i >>= 1)
		ax_mii_writebit(sc, bits & i);
}

/*
 * Read an PHY register through the MII.
 */
static int ax_mii_readreg(sc, frame)
	struct ax_softc		*sc;
	struct ax_mii_frame	*frame;
	
{
	int			i, ack, s;

	s = splimp();

	/*
	 * Set up frame for RX.
	 */
	frame->mii_stdelim = AX_MII_STARTDELIM;
	frame->mii_opcode = AX_MII_READOP;
	frame->mii_turnaround = 0;
	frame->mii_data = 0;
	
	/*
	 * Sync the PHYs.
	 */
	ax_mii_sync(sc);

	/*
	 * Send command/address info.
	 */
	ax_mii_send(sc, frame->mii_stdelim, 2);
	ax_mii_send(sc, frame->mii_opcode, 2);
	ax_mii_send(sc, frame->mii_phyaddr, 5);
	ax_mii_send(sc, frame->mii_regaddr, 5);

#ifdef notdef
	/* Idle bit */
	ax_mii_writebit(sc, 1);
	ax_mii_writebit(sc, 0);
#endif

	/* Check for ack */
	ack = ax_mii_readbit(sc);

	/*
	 * Now try reading data bits. If the ack failed, we still
	 * need to clock through 16 cycles to keep the PHY(s) in sync.
	 */
	if (ack) {
		for(i = 0; i < 16; i++) {
			ax_mii_readbit(sc);
		}
		goto fail;
	}

	for (i = 0x8000; i; i >>= 1) {
		if (!ack) {
			if (ax_mii_readbit(sc))
				frame->mii_data |= i;
		}
	}

fail:

	ax_mii_writebit(sc, 0);
	ax_mii_writebit(sc, 0);

	splx(s);

	if (ack)
		return(1);
	return(0);
}

/*
 * Write to a PHY register through the MII.
 */
static int ax_mii_writereg(sc, frame)
	struct ax_softc		*sc;
	struct ax_mii_frame	*frame;
	
{
	int			s;

	s = splimp();
	/*
	 * Set up frame for TX.
	 */

	frame->mii_stdelim = AX_MII_STARTDELIM;
	frame->mii_opcode = AX_MII_WRITEOP;
	frame->mii_turnaround = AX_MII_TURNAROUND;

	/*
	 * Sync the PHYs.
	 */	
	ax_mii_sync(sc);

	ax_mii_send(sc, frame->mii_stdelim, 2);
	ax_mii_send(sc, frame->mii_opcode, 2);
	ax_mii_send(sc, frame->mii_phyaddr, 5);
	ax_mii_send(sc, frame->mii_regaddr, 5);
	ax_mii_send(sc, frame->mii_turnaround, 2);
	ax_mii_send(sc, frame->mii_data, 16);

	/* Idle bit. */
	ax_mii_writebit(sc, 0);
	ax_mii_writebit(sc, 0);

	splx(s);

	return(0);
}

static u_int16_t ax_phy_readreg(sc, reg)
	struct ax_softc		*sc;
	int			reg;
{
	struct ax_mii_frame	frame;

	bzero((char *)&frame, sizeof(frame));

	frame.mii_phyaddr = sc->ax_phy_addr;
	frame.mii_regaddr = reg;
	ax_mii_readreg(sc, &frame);

	return(frame.mii_data);
}

static void ax_phy_writereg(sc, reg, data)
	struct ax_softc		*sc;
	int			reg;
	int			data;
{
	struct ax_mii_frame	frame;

	bzero((char *)&frame, sizeof(frame));

	frame.mii_phyaddr = sc->ax_phy_addr;
	frame.mii_regaddr = reg;
	frame.mii_data = data;

	ax_mii_writereg(sc, &frame);

	return;
}

/*
 * Calculate CRC of a multicast group address, return the lower 6 bits.
 */
static u_int32_t ax_calchash(addr)
	caddr_t			addr;
{
	u_int32_t		crc, carry;
	int			i, j;
	u_int8_t		c;

	/* Compute CRC for the address value. */
	crc = 0xFFFFFFFF; /* initial value */

	for (i = 0; i < 6; i++) {
		c = *(addr + i);
		for (j = 0; j < 8; j++) {
			carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
			crc <<= 1;
			c >>= 1;
			if (carry)
				crc = (crc ^ 0x04c11db6) | carry;
		}