if_tlreg.h

基于组件方式开发操作系统的OSKIT源代码

 * ThunderLAN SIO register bits
 */
#define TL_SIO_MINTEN		0x80
#define TL_SIO_ECLOK		0x40
#define TL_SIO_ETXEN		0x20
#define TL_SIO_EDATA		0x10
#define TL_SIO_NMRST		0x08
#define TL_SIO_MCLK		0x04
#define TL_SIO_MTXEN		0x02
#define TL_SIO_MDATA		0x01

/*
 * Thunderlan NETCONFIG bits
 */
#define TL_CFG_RCLKTEST		0x8000
#define TL_CFG_TCLKTEST		0x4000
#define TL_CFG_BITRATE		0x2000
#define TL_CFG_RXCRC		0x1000
#define TL_CFG_PEF		0x0800
#define TL_CFG_ONEFRAG		0x0400
#define TL_CFG_ONECHAN		0x0200
#define TL_CFG_MTEST		0x0100
#define TL_CFG_PHYEN		0x0080
#define TL_CFG_MACSEL6		0x0040
#define TL_CFG_MACSEL5		0x0020
#define TL_CFG_MACSEL4		0x0010
#define TL_CFG_MACSEL3		0x0008
#define TL_CFG_MACSEL2		0x0004
#define TL_CFG_MACSEL1		0x0002
#define TL_CFG_MACSEL0		0x0001

/*
 * ThunderLAN NETSTS bits
 */
#define TL_STS_MIRQ		0x80
#define TL_STS_HBEAT		0x40
#define TL_STS_TXSTOP		0x20
#define TL_STS_RXSTOP		0x10

/*
 * ThunderLAN NETCMD bits
 */
#define TL_CMD_NRESET		0x80
#define TL_CMD_NWRAP		0x40
#define TL_CMD_CSF		0x20
#define TL_CMD_CAF		0x10
#define TL_CMD_NOBRX		0x08
#define TL_CMD_DUPLEX		0x04
#define TL_CMD_TRFRAM		0x02
#define TL_CMD_TXPACE		0x01

/*
 * ThunderLAN NETMASK bits
 */
#define TL_MASK_MASK7		0x80
#define TL_MASK_MASK6		0x40
#define TL_MASK_MASK5		0x20
#define TL_MASK_MASK4		0x10

/*
 * MII frame format
 */
#ifdef ANSI_DOESNT_ALLOW_BITFIELDS
struct tl_mii_frame {
	u_int16_t		mii_stdelim:2,
				mii_opcode:2,
				mii_phyaddr:5,
				mii_regaddr:5,
				mii_turnaround:2;
	u_int16_t		mii_data;
};
#else
struct tl_mii_frame {
	u_int8_t		mii_stdelim;
	u_int8_t		mii_opcode;
	u_int8_t		mii_phyaddr;
	u_int8_t		mii_regaddr;
	u_int8_t		mii_turnaround;
	u_int16_t		mii_data;
};
#endif
/*
 * MII constants
 */
#define TL_MII_STARTDELIM	0x01
#define TL_MII_READOP		0x02
#define TL_MII_WRITEOP		0x01
#define TL_MII_TURNAROUND	0x02

#define TL_LAST_FRAG		0x80000000
#define TL_CSTAT_UNUSED		0x8000
#define TL_CSTAT_FRAMECMP	0x4000
#define TL_CSTAT_READY		0x3000
#define TL_CSTAT_UNUSED13	0x2000
#define TL_CSTAT_UNUSED12	0x1000
#define TL_CSTAT_EOC		0x0800
#define TL_CSTAT_RXERROR	0x0400
#define TL_CSTAT_PASSCRC	0x0200
#define TL_CSTAT_DPRIO		0x0100

#define TL_FRAME_MASK		0x00FFFFFF
#define tl_tx_goodframes(x)	(x.tl_txstat & TL_FRAME_MASK)
#define tl_tx_underrun(x)	((x.tl_txstat & ~TL_FRAME_MASK) >> 24)
#define tl_rx_goodframes(x)	(x.tl_rxstat & TL_FRAME_MASK)
#define tl_rx_overrun(x)	((x.tl_rxstat & ~TL_FRAME_MASK) >> 24)

struct tl_stats {
	u_int32_t		tl_txstat;
	u_int32_t		tl_rxstat;
	u_int16_t		tl_deferred;
	u_int8_t		tl_crc_errors;
	u_int8_t		tl_code_errors;
	u_int16_t		tl_tx_multi_collision;
	u_int16_t		tl_tx_single_collision;
	u_int8_t		tl_excessive_collision;
	u_int8_t		tl_late_collision;
	u_int8_t		tl_carrier_loss;
	u_int8_t		acommit;
};

/*
 * ACOMMIT register bits. These are used only when a bitrate
 * PHY is selected ('bitrate' bit in netconfig register is set).
 */
#define TL_AC_MTXER		0x01	/* reserved */
#define TL_AC_MTXD1		0x02	/* 0 == 10baseT 1 == AUI */
#define TL_AC_MTXD2		0x04	/* loopback disable */
#define TL_AC_MTXD3		0x08	/* full duplex disable */

/*
 * register space access macros
 */
#define CSR_WRITE_4(sc, reg, val)	\
	bus_space_write_4(sc->tl_btag, sc->tl_bhandle, reg, val)
#define CSR_WRITE_2(sc, reg, val)	\
	bus_space_write_2(sc->tl_btag, sc->tl_bhandle, reg, val)
#define CSR_WRITE_1(sc, reg, val)	\
	bus_space_write_1(sc->tl_btag, sc->tl_bhandle, reg, val)

#define CSR_READ_4(sc, reg)		\
	bus_space_read_4(sc->tl_btag, sc->tl_bhandle, reg)
#define CSR_READ_2(sc, reg)		\
	bus_space_read_2(sc->tl_btag, sc->tl_bhandle, reg)
#define CSR_READ_1(sc, reg)		\
	bus_space_read_1(sc->tl_btag, sc->tl_bhandle, reg)

#define CMD_PUT(sc, x) CSR_WRITE_4(sc, TL_HOSTCMD, x)
#define CMD_SET(sc, x)	\
	CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) | (x))
#define CMD_CLR(sc, x)	\
	CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) & ~(x))

/*
 * ThunderLAN adapters typically have a serial EEPROM containing
 * configuration information. The main reason we're interested in
 * it is because it also contains the adapters's station address.
 *
 * Access to the EEPROM is a bit goofy since it is a serial device:
 * you have to do reads and writes one bit at a time. The state of
 * the DATA bit can only change while the CLOCK line is held low.
 * Transactions work basically like this:
 *
 * 1) Send the EEPROM_START sequence to prepare the EEPROM for
 *    accepting commands. This pulls the clock high, sets
 *    the data bit to 0, enables transmission to the EEPROM,
 *    pulls the data bit up to 1, then pulls the clock low.
 *    The idea is to do a 0 to 1 transition of the data bit
 *    while the clock pin is held high.
 *
 * 2) To write a bit to the EEPROM, set the TXENABLE bit, then
 *    set the EDATA bit to send a 1 or clear it to send a 0.
 *    Finally, set and then clear ECLOK. Strobing the clock
 *    transmits the bit. After 8 bits have been written, the
 *    EEPROM should respond with an ACK, which should be read.
 *
 * 3) To read a bit from the EEPROM, clear the TXENABLE bit,
 *    then set ECLOK. The bit can then be read by reading EDATA.
 *    ECLOCK should then be cleared again. This can be repeated
 *    8 times to read a whole byte, after which the 
 *
 * 4) We need to send the address byte to the EEPROM. For this
 *    we have to send the write control byte to the EEPROM to
 *    tell it to accept data. The byte is 0xA0. The EEPROM should
 *    ack this. The address byte can be send after that.
 *
 * 5) Now we have to tell the EEPROM to send us data. For that we
 *    have to transmit the read control byte, which is 0xA1. This
 *    byte should also be acked. We can then read the data bits
 *    from the EEPROM.
 *
 * 6) When we're all finished, send the EEPROM_STOP sequence.
 *
 * Note that we use the ThunderLAN's NetSio register to access the
 * EEPROM, however there is an alternate method. There is a PCI NVRAM
 * register at PCI offset 0xB4 which can also be used with minor changes.
 * The difference is that access to PCI registers via pci_conf_read()
 * and pci_conf_write() is done using programmed I/O, which we want to
 * avoid.
 */

/*
 * Note that EEPROM_START leaves transmission enabled.
 */
#define EEPROM_START							\
	tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock pin high */\
	tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Set DATA bit to 1 */	\
	tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Enable xmit to write bit */\
	tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Pull DATA bit to 0 again */\
	tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock low again */

/*
 * EEPROM_STOP ends access to the EEPROM and clears the ETXEN bit so
 * that no further data can be written to the EEPROM I/O pin.
 */
#define EEPROM_STOP							\
	tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Disable xmit */	\
	tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Pull DATA to 0 */	\
	tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock high */	\
	tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Enable xmit */	\
	tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Toggle DATA to 1 */	\
	tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Disable xmit. */	\
	tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock low again */


/*
 * These are the register definitions for the PHY (physical layer
 * interface chip).
 * The ThunderLAN chip has a built-in 10Mb/sec PHY which may be used
 * in some configurations. The Compaq 10/100 cards based on the ThunderLAN
 * use a National Semiconductor DP83840A PHY. The generic BMCR and BMSR
 * layouts for both PHYs are identical, however some of the bits are not
 * used by the ThunderLAN's internal PHY (most notably those dealing with
 * switching between 10 and 100Mb/sec speeds). Since Both PHYs use the
 * same bits, we #define them with generic names here.
 */
/*
 * PHY BMCR Basic Mode Control Register
 */
#define PHY_BMCR			0x00
#define PHY_BMCR_RESET			0x8000
#define PHY_BMCR_LOOPBK			0x4000
#define PHY_BMCR_SPEEDSEL		0x2000
#define PHY_BMCR_AUTONEGENBL		0x1000
#define PHY_BMCR_RSVD0			0x0800	/* write as zero */
#define PHY_BMCR_PWRDOWN		0x0800	/* tlan internal PHY only */
#define PHY_BMCR_ISOLATE		0x0400
#define PHY_BMCR_AUTONEGRSTR		0x0200
#define PHY_BMCR_DUPLEX			0x0100
#define PHY_BMCR_COLLTEST		0x0080
#define PHY_BMCR_RSVD1			0x0040	/* write as zero, don't care */
#define PHY_BMCR_RSVD2			0x0020	/* write as zero, don't care */
#define PHY_BMCR_RSVD3			0x0010	/* write as zero, don't care */
#define PHY_BMCR_RSVD4			0x0008	/* write as zero, don't care */
#define PHY_BMCR_RSVD5			0x0004	/* write as zero, don't care */
#define PHY_BMCR_RSVD6			0x0002	/* write as zero, don't care */
#define PHY_BMCR_RSVD7			0x0001	/* write as zero, don't care */
/*
 * RESET: 1 == software reset, 0 == normal operation
 * Resets status and control registers to default values.
 * Relatches all hardware config values.
 *
 * LOOPBK: 1 == loopback operation enabled, 0 == normal operation
 *
 * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
 * Link speed is selected byt his bit or if auto-negotiation if bit
 * 12 (AUTONEGENBL) is set (in which case the value of this register
 * is ignored).
 *
 * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
 * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
 * determine speed and mode. Should be cleared and then set if PHY configured
 * for no autoneg on startup.
 *
 * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
 *
 * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
 *
 * DUPLEX: 1 == full duplex mode, 0 == half duplex mode
 *
 * COLLTEST: 1 == collision test enabled, 0 == normal operation
 */

/* 
 * PHY, BMSR Basic Mode Status Register 
 */   
#define PHY_BMSR			0x01
#define PHY_BMSR_100BT4			0x8000
#define PHY_BMSR_100BTXFULL		0x4000
#define PHY_BMSR_100BTXHALF		0x2000
#define PHY_BMSR_10BTFULL		0x1000
#define PHY_BMSR_10BTHALF		0x0800
#define PHY_BMSR_RSVD1			0x0400	/* write as zero, don't care */
#define PHY_BMSR_RSVD2			0x0200	/* write as zero, don't care */
#define PHY_BMSR_RSVD3			0x0100	/* write as zero, don't care */
#define PHY_BMSR_RSVD4			0x0080	/* write as zero, don't care */
#define PHY_BMSR_MFPRESUP		0x0040
#define PHY_BMSR_AUTONEGCOMP		0x0020
#define PHY_BMSR_REMFAULT		0x0010
#define PHY_BMSR_CANAUTONEG		0x0008
#define PHY_BMSR_LINKSTAT		0x0004
#define PHY_BMSR_JABBER			0x0002
#define PHY_BMSR_EXTENDED		0x0001

#define PHY_CTL_IGLINK			0x8000
#define PHY_CTL_SWAPOL			0x4000
#define PHY_CTL_AUISEL			0x2000
#define PHY_CTL_SQEEN			0x1000
#define PHY_CTL_MTEST			0x0800
#define PHY_CTL_NFEW			0x0004
#define PHY_CTL_INTEN			0x0002
#define PHY_CTL_TINT			0x0001

#define TL_PHY_GENCTL			0x00
#define TL_PHY_GENSTS			0x01

/*
 * PHY Generic Identifier Register, hi bits
 */
#define TL_PHY_VENID			0x02

/*
 * PHY Generic Identifier Register, lo bits
 */
#define TL_PHY_DEVID			0x03

#define TL_PHY_ANAR			0x04
#define TL_PHY_LPAR			0x05 
#define TL_PHY_ANEXP			0x06

#define TL_PHY_PHYID			0x10
#define TL_PHY_CTL			0x11
#define TL_PHY_STS			0x12

#define TL_LPAR_RMFLT			0x2000
#define TL_LPAR_RSVD0			0x1000
#define TL_LPAR_RSVD1			0x0800
#define TL_LPAR_100BT4			0x0400
#define TL_LPAR_100BTXFULL		0x0200
#define TL_LPAR_100BTXHALF		0x0100
#define TL_LPAR_10BTFULL		0x0080
#define TL_LPAR_10BTHALF		0x0040

/*
 * PHY Antoneg advertisement register.
 */
#define PHY_ANAR			TL_PHY_ANAR
#define PHY_ANAR_NEXTPAGE		0x8000
#define PHY_ANAR_RSVD0			0x4000
#define PHY_ANAR_TLRFLT			0x2000
#define PHY_ANAR_RSVD1			0x1000
#define PHY_RSVD_RSDV2			0x0800
#define PHY_RSVD_RSVD3			0x0400
#define PHY_ANAR_100BT4			0x0200
#define PHY_ANAR_100BTXFULL		0x0100
#define PHY_ANAR_100BTXHALF		0x0080
#define PHY_ANAR_10BTFULL		0x0040
#define PHY_ANAR_10BTHALF		0x0020
#define PHY_ANAR_PROTO4			0x0010
#define PHY_ANAR_PROTO3			0x0008
#define PHY_ANAR_PROTO2			0x0004
#define PHY_AHAR_PROTO1			0x0002
#define PHY_AHAR_PROTO0			0x0001

/*
 * DP83840 PHY, PCS Confifguration Register
 */
#define TL_DP83840_PCS			0x17
#define TL_DP83840_PCS_LED4_MODE	0x0002
#define TL_DP83840_PCS_F_CONNECT	0x0020
#define TL_DP83840_PCS_BIT8		0x0100
#define TL_DP83840_PCS_BIT10		0x0400

/*
 * DP83840 PHY, PAR register
 */
#define TL_DP83840_PAR			0x19

#define PAR_RSVD0			0x8000
#define PAR_RSVD1			0x4000
#define PAR_RSVD2			0x2000
#define PAR_RSVD3			0x1000
#define PAR_DIS_CRS_JAB			0x0800
#define PAR_AN_EN_STAT			0x0400
#define PAR_RSVD4			0x0200
#define PAR_FEFI_EN			0x0100
#define PAR_DUPLEX_STAT			0x0080
#define PAR_SPEED_10			0x0040
#define PAR_CIM_STATUS			0x0020
#define PAR_PHYADDR4			0x0010
#define PAR_PHYADDR3			0x0008
#define PAR_PHYADDR2			0x0004
#define PAR_PHYADDR1			0x0002
#define PAR_PHYADDR0			0x0001


/*
 * Microchip Technology 24Cxx EEPROM control bytes
 */
#define EEPROM_CTL_READ			0xA1	/* 0101 0001 */
#define EEPROM_CTL_WRITE		0xA0	/* 0101 0000 */

#ifdef __alpha__
#undef vtophys
#define vtophys(va)		(pmap_kextract(((vm_offset_t) (va))) \
					+ 1*1024*1024*1024)
#endif