if_mx.c

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/*
 * Copyright (c) 1997, 1998
 *	Bill Paul <[e-mail]>.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by Bill Paul.
 * 4. Neither the name of the author nor the names of any co-contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 * THE POSSIBILITY OF SUCH DAMAGE.
 *
 *	$Id: if_mx.c,v 1.8.2.5 1999/05/06 15:39:32 wpaul Exp $
 */

/*
 * Macronix PMAC fast ethernet PCI NIC driver
 *
 * Written by Bill Paul <[e-mail]>
 * Electrical Engineering Department
 * Columbia University, New York City
 */

/*
 * The Macronix 98713, 98715 and 98725 chips are still more tulip clones.
 * The 98713 has an internal transceiver and an MII bus for external PHYs.
 * The other two chips have only the internal transceiver. All have
 * support for built-in autonegotiation. Additionally, there are 98713A
 * and 98715A chips which support power management. The 98725 chip
 * supports power management as well.
 *
 * Datasheets for the Macronix parts can be obtained from www.macronix.com.
 * Note however that the datasheets do not describe the TX and RX
 * descriptor structures or the setup frame format(s). For this, you should
 * obtain a DEC 21x4x datasheet from developer.intel.com. The Macronix
 * chips look to be fairly straightforward tulip clones, except for
 * the NWAY support.
 */

#include "bpfilter.h"

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/sockio.h>
#include <sys/mbuf.h>
#include <sys/malloc.h>
#include <sys/kernel.h>
#include <sys/socket.h>

#include <net/if.h>
#include <net/if_arp.h>
#include <net/ethernet.h>
#include <net/if_dl.h>
#include <net/if_media.h>

#if NBPFILTER > 0
#include <net/bpf.h>
#endif

#include <vm/vm.h>              /* for vtophys */
#include <vm/pmap.h>            /* for vtophys */
#include <machine/clock.h>      /* for DELAY */
#include <machine/bus_pio.h>
#include <machine/bus_memio.h>
#include <machine/bus.h>

#include <pci/pcireg.h>
#include <pci/pcivar.h>

#define MX_USEIOSPACE

/* #define MX_BACKGROUND_AUTONEG */

#include <pci/if_mxreg.h>

#ifndef lint
static const char rcsid[] =
	"$Id: if_mx.c,v 1.8.2.5 1999/05/06 15:39:32 wpaul Exp $";
#endif

/*
 * Various supported device vendors/types and their names.
 */
static struct mx_type mx_devs[] = {
	{ MX_VENDORID, MX_DEVICEID_98713,
		"Macronix 98713 10/100BaseTX" },
	{ MX_VENDORID, MX_DEVICEID_98713,
		"Macronix 98713A 10/100BaseTX" },
	{ CP_VENDORID, CP_DEVICEID_98713,
		"Compex RL100-TX 10/100BaseTX" },
	{ CP_VENDORID, CP_DEVICEID_98713,
		"Compex RL100-TX 10/100BaseTX" },
	{ MX_VENDORID, MX_DEVICEID_987x5,
		"Macronix 98715/98715A 10/100BaseTX" },
	{ MX_VENDORID, MX_DEVICEID_987x5,
		"Macronix 98725 10/100BaseTX" },
	{ 0, 0, NULL }
};

/*
 * Various supported PHY vendors/types and their names. Note that
 * this driver will work with pretty much any MII-compliant PHY,
 * so failure to positively identify the chip is not a fatal error.
 */

static struct mx_type mx_phys[] = {
	{ TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" },
	{ TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" },
	{ NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"},
	{ LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" }, 
	{ INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" },
	{ SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" },
	{ 0, 0, "<MII-compliant physical interface>" }
};

static unsigned long mx_count = 0;
static const char *mx_probe	__P((pcici_t, pcidi_t));
static void mx_attach		__P((pcici_t, int));

static int mx_newbuf		__P((struct mx_softc *,
						struct mx_chain_onefrag *));
static int mx_encap		__P((struct mx_softc *, struct mx_chain *,
						struct mbuf *));

static void mx_rxeof		__P((struct mx_softc *));
static void mx_rxeoc		__P((struct mx_softc *));
static void mx_txeof		__P((struct mx_softc *));
static void mx_txeoc		__P((struct mx_softc *));
static void mx_intr		__P((void *));
static void mx_start		__P((struct ifnet *));
static int mx_ioctl		__P((struct ifnet *, u_long, caddr_t));
static void mx_init		__P((void *));
static void mx_stop		__P((struct mx_softc *));
static void mx_watchdog		__P((struct ifnet *));
static void mx_shutdown		__P((int, void *));
static int mx_ifmedia_upd	__P((struct ifnet *));
static void mx_ifmedia_sts	__P((struct ifnet *, struct ifmediareq *));

static void mx_delay		__P((struct mx_softc *));
static void mx_eeprom_idle	__P((struct mx_softc *));
static void mx_eeprom_putbyte	__P((struct mx_softc *, int));
static void mx_eeprom_getword	__P((struct mx_softc *, int, u_int16_t *));
static void mx_read_eeprom	__P((struct mx_softc *, caddr_t, int,
							int, int));

static void mx_mii_writebit	__P((struct mx_softc *, int));
static int mx_mii_readbit	__P((struct mx_softc *));
static void mx_mii_sync		__P((struct mx_softc *));
static void mx_mii_send		__P((struct mx_softc *, u_int32_t, int));
static int mx_mii_readreg	__P((struct mx_softc *, struct mx_mii_frame *));
static int mx_mii_writereg	__P((struct mx_softc *, struct mx_mii_frame *));
static u_int16_t mx_phy_readreg	__P((struct mx_softc *, int));
static void mx_phy_writereg	__P((struct mx_softc *, int, int));

static void mx_autoneg_xmit	__P((struct mx_softc *));
static void mx_autoneg_mii	__P((struct mx_softc *, int, int));
static void mx_autoneg		__P((struct mx_softc *, int, int));
static void mx_setmode_mii	__P((struct mx_softc *, int));
static void mx_setmode		__P((struct mx_softc *, int, int));
static void mx_getmode_mii	__P((struct mx_softc *));
static void mx_setcfg		__P((struct mx_softc *, int));
static u_int32_t mx_calchash	__P((caddr_t));
static void mx_setfilt		__P((struct mx_softc *));
static void mx_reset		__P((struct mx_softc *));
static int mx_list_rx_init	__P((struct mx_softc *));
static int mx_list_tx_init	__P((struct mx_softc *));

#define MX_SETBIT(sc, reg, x)				\
	CSR_WRITE_4(sc, reg,				\
		CSR_READ_4(sc, reg) | x)

#define MX_CLRBIT(sc, reg, x)				\
	CSR_WRITE_4(sc, reg,				\
		CSR_READ_4(sc, reg) & ~x)

#define SIO_SET(x)					\
	CSR_WRITE_4(sc, MX_SIO,				\
		CSR_READ_4(sc, MX_SIO) | x)

#define SIO_CLR(x)					\
	CSR_WRITE_4(sc, MX_SIO,				\
		CSR_READ_4(sc, MX_SIO) & ~x)

static void mx_delay(sc)
	struct mx_softc		*sc;
{
	int			idx;

	for (idx = (300 / 33) + 1; idx > 0; idx--)
		CSR_READ_4(sc, MX_BUSCTL);
}

static void mx_eeprom_idle(sc)
	struct mx_softc		*sc;
{
	register int		i;

	CSR_WRITE_4(sc, MX_SIO, MX_SIO_EESEL);
	mx_delay(sc);
	MX_SETBIT(sc, MX_SIO,  MX_SIO_ROMCTL_READ);
	mx_delay(sc);
	MX_SETBIT(sc, MX_SIO, MX_SIO_EE_CS);
	mx_delay(sc);
	MX_SETBIT(sc, MX_SIO, MX_SIO_EE_CLK);
	mx_delay(sc);

	for (i = 0; i < 25; i++) {
		MX_CLRBIT(sc, MX_SIO, MX_SIO_EE_CLK);
		mx_delay(sc);
		MX_SETBIT(sc, MX_SIO, MX_SIO_EE_CLK);
		mx_delay(sc);
	}

	MX_CLRBIT(sc, MX_SIO, MX_SIO_EE_CLK);
	mx_delay(sc);
	MX_CLRBIT(sc, MX_SIO, MX_SIO_EE_CS);
	mx_delay(sc);
	CSR_WRITE_4(sc, MX_SIO, 0x00000000);

	return;
}

/*
 * Send a read command and address to the EEPROM, check for ACK.
 */
static void mx_eeprom_putbyte(sc, addr)
	struct mx_softc		*sc;
	int			addr;
{
	register int		d, i;

	d = addr | MX_EECMD_READ;

	/*
	 * Feed in each bit and stobe the clock.
	 */
	for (i = 0x400; i; i >>= 1) {
		if (d & i) {
			SIO_SET(MX_SIO_EE_DATAIN);
		} else {
			SIO_CLR(MX_SIO_EE_DATAIN);
		}
		mx_delay(sc);
		SIO_SET(MX_SIO_EE_CLK);
		mx_delay(sc);
		SIO_CLR(MX_SIO_EE_CLK);
		mx_delay(sc);
	}

	return;
}

/*
 * Read a word of data stored in the EEPROM at address 'addr.'
 */
static void mx_eeprom_getword(sc, addr, dest)
	struct mx_softc		*sc;
	int			addr;
	u_int16_t		*dest;
{
	register int		i;
	u_int16_t		word = 0;

	/* Force EEPROM to idle state. */
	mx_eeprom_idle(sc);

	/* Enter EEPROM access mode. */
	CSR_WRITE_4(sc, MX_SIO, MX_SIO_EESEL);
	mx_delay(sc);
	MX_SETBIT(sc, MX_SIO,  MX_SIO_ROMCTL_READ);
	mx_delay(sc);
	MX_SETBIT(sc, MX_SIO, MX_SIO_EE_CS);
	mx_delay(sc);
	MX_SETBIT(sc, MX_SIO, MX_SIO_EE_CLK);
	mx_delay(sc);

	/*
	 * Send address of word we want to read.
	 */
	mx_eeprom_putbyte(sc, addr);

	/*
	 * Start reading bits from EEPROM.
	 */
	for (i = 0x8000; i; i >>= 1) {
		SIO_SET(MX_SIO_EE_CLK);
		mx_delay(sc);
		if (CSR_READ_4(sc, MX_SIO) & MX_SIO_EE_DATAOUT)
			word |= i;
		mx_delay(sc);
		SIO_CLR(MX_SIO_EE_CLK);
		mx_delay(sc);
	}

	/* Turn off EEPROM access mode. */
	mx_eeprom_idle(sc);

	*dest = word;

	return;
}

/*
 * Read a sequence of words from the EEPROM.
 */
static void mx_read_eeprom(sc, dest, off, cnt, swap)
	struct mx_softc		*sc;
	caddr_t			dest;
	int			off;
	int			cnt;
	int			swap;
{
	int			i;
	u_int16_t		word = 0, *ptr;

	for (i = 0; i < cnt; i++) {
		mx_eeprom_getword(sc, off + i, &word);
		ptr = (u_int16_t *)(dest + (i * 2));
		if (swap)
			*ptr = ntohs(word);
		else
			*ptr = word;
	}

	return;
}

/*
 * The following two routines are taken from the Macronix 98713
 * Application Notes pp.19-21.
 */
/*
 * Write a bit to the MII bus.
 */
static void mx_mii_writebit(sc, bit)
	struct mx_softc		*sc;
	int			bit;
{
	if (bit)
		CSR_WRITE_4(sc, MX_SIO, MX_SIO_ROMCTL_WRITE|MX_SIO_MII_DATAOUT);
	else
		CSR_WRITE_4(sc, MX_SIO, MX_SIO_ROMCTL_WRITE);

	MX_SETBIT(sc, MX_SIO, MX_SIO_MII_CLK);
	MX_CLRBIT(sc, MX_SIO, MX_SIO_MII_CLK);

	return;
}

/*
 * Read a bit from the MII bus.
 */
static int mx_mii_readbit(sc)
	struct mx_softc		*sc;
{
	CSR_WRITE_4(sc, MX_SIO, MX_SIO_ROMCTL_READ|MX_SIO_MII_DIR);
	CSR_READ_4(sc, MX_SIO);
	MX_SETBIT(sc, MX_SIO, MX_SIO_MII_CLK);
	MX_CLRBIT(sc, MX_SIO, MX_SIO_MII_CLK);
	if (CSR_READ_4(sc, MX_SIO) & MX_SIO_MII_DATAIN)
		return(1);

	return(0);
}

/*
 * Sync the PHYs by setting data bit and strobing the clock 32 times.
 */
static void mx_mii_sync(sc)
	struct mx_softc		*sc;
{
	register int		i;

	CSR_WRITE_4(sc, MX_SIO, MX_SIO_ROMCTL_WRITE);

	for (i = 0; i < 32; i++)
		mx_mii_writebit(sc, 1);

	return;
}

/*
 * Clock a series of bits through the MII.
 */
static void mx_mii_send(sc, bits, cnt)
	struct mx_softc		*sc;
	u_int32_t		bits;
	int			cnt;
{
	int			i;

	for (i = (0x1 << (cnt - 1)); i; i >>= 1)
		mx_mii_writebit(sc, bits & i);
}

/*
 * Read an PHY register through the MII.
 */
static int mx_mii_readreg(sc, frame)
	struct mx_softc		*sc;
	struct mx_mii_frame	*frame;
	
{
	int			i, ack, s;

	s = splimp();

	/*
	 * Set up frame for RX.
	 */
	frame->mii_stdelim = MX_MII_STARTDELIM;
	frame->mii_opcode = MX_MII_READOP;
	frame->mii_turnaround = 0;
	frame->mii_data = 0;
	
	/*
	 * Sync the PHYs.
	 */
	mx_mii_sync(sc);

	/*
	 * Send command/address info.
	 */
	mx_mii_send(sc, frame->mii_stdelim, 2);
	mx_mii_send(sc, frame->mii_opcode, 2);
	mx_mii_send(sc, frame->mii_phyaddr, 5);
	mx_mii_send(sc, frame->mii_regaddr, 5);

#ifdef notdef
	/* Idle bit */
	mx_mii_writebit(sc, 1);
	mx_mii_writebit(sc, 0);
#endif

	/* Check for ack */
	ack = mx_mii_readbit(sc);

	/*
	 * Now try reading data bits. If the ack failed, we still
	 * need to clock through 16 cycles to keep the PHY(s) in sync.
	 */
	if (ack) {
		for(i = 0; i < 16; i++) {
			mx_mii_readbit(sc);
		}
		goto fail;
	}

	for (i = 0x8000; i; i >>= 1) {
		if (!ack) {
			if (mx_mii_readbit(sc))
				frame->mii_data |= i;
		}
	}

fail:

	mx_mii_writebit(sc, 0);
	mx_mii_writebit(sc, 0);

	splx(s);

	if (ack)
		return(1);
	return(0);
}

/*
 * Write to a PHY register through the MII.
 */
static int mx_mii_writereg(sc, frame)
	struct mx_softc		*sc;
	struct mx_mii_frame	*frame;
	
{
	int			s;

	s = splimp();
	/*
	 * Set up frame for TX.
	 */

	frame->mii_stdelim = MX_MII_STARTDELIM;
	frame->mii_opcode = MX_MII_WRITEOP;
	frame->mii_turnaround = MX_MII_TURNAROUND;

	/*
	 * Sync the PHYs.
	 */	
	mx_mii_sync(sc);

	mx_mii_send(sc, frame->mii_stdelim, 2);
	mx_mii_send(sc, frame->mii_opcode, 2);
	mx_mii_send(sc, frame->mii_phyaddr, 5);
	mx_mii_send(sc, frame->mii_regaddr, 5);
	mx_mii_send(sc, frame->mii_turnaround, 2);
	mx_mii_send(sc, frame->mii_data, 16);

	/* Idle bit. */
	mx_mii_writebit(sc, 0);
	mx_mii_writebit(sc, 0);

	splx(s);

	return(0);
}

static u_int16_t mx_phy_readreg(sc, reg)
	struct mx_softc		*sc;
	int			reg;
{
	struct mx_mii_frame	frame;
	u_int32_t		cfg;

	bzero((char *)&frame, sizeof(frame));

	frame.mii_phyaddr = sc->mx_phy_addr;
	frame.mii_regaddr = reg;
	cfg = CSR_READ_4(sc, MX_NETCFG);
	MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_PORTSEL);
	mx_mii_readreg(sc, &frame);
	CSR_WRITE_4(sc, MX_NETCFG, cfg);

	return(frame.mii_data);
}

static void mx_phy_writereg(sc, reg, data)
	struct mx_softc		*sc;
	int			reg;
	int			data;
{
	struct mx_mii_frame	frame;
	u_int32_t		cfg;

	bzero((char *)&frame, sizeof(frame));

	frame.mii_phyaddr = sc->mx_phy_addr;
	frame.mii_regaddr = reg;
	frame.mii_data = data;

	cfg = CSR_READ_4(sc, MX_NETCFG);
	MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_PORTSEL);
	mx_mii_writereg(sc, &frame);
	CSR_WRITE_4(sc, MX_NETCFG, cfg);

	return;
}

#define MX_POLY		0xEDB88320
#define MX_BITS		9

static u_int32_t mx_calchash(addr)
	caddr_t			addr;
{
	u_int32_t		idx, bit, data, crc;

	/* Compute CRC for the address value. */
	crc = 0xFFFFFFFF; /* initial value */

	for (idx = 0; idx < 6; idx++) {
		for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
			crc = (crc >> 1) ^ (((crc ^ data) & 1) ? MX_POLY : 0);
	}

	return (crc & ((1 << MX_BITS) - 1));
}

/*
 * Initiate an autonegotiation session.
 */
static void mx_autoneg_xmit(sc)
	struct mx_softc		*sc;
{
	u_int16_t		phy_sts;

	mx_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
	DELAY(500);
	while(mx_phy_readreg(sc, PHY_BMCR)
			& PHY_BMCR_RESET);

	phy_sts = mx_phy_readreg(sc, PHY_BMCR);
	phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR;
	mx_phy_writereg(sc, PHY_BMCR, phy_sts);

	return;
}

/*
 * Invoke autonegotiation on a PHY.
 */
static void mx_autoneg_mii(sc, flag, verbose)
	struct mx_softc		*sc;
	int			flag;
	int			verbose;
{
	u_int16_t		phy_sts = 0, media, advert, ability;
	struct ifnet		*ifp;
	struct ifmedia		*ifm;

	ifm = &sc->ifmedia;
	ifp = &sc->arpcom.ac_if;

	ifm->ifm_media = IFM_ETHER | IFM_AUTO;

	/*