if_axreg.h

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struct ax_list_data {
	volatile struct ax_desc		ax_rx_list[AX_RX_LIST_CNT];
	volatile struct ax_txdesc	ax_tx_list[AX_TX_LIST_CNT];
};

struct ax_chain {
	volatile struct ax_txdesc	*ax_ptr;
	struct mbuf			*ax_mbuf;
	struct ax_chain			*ax_nextdesc;
	u_int8_t			ax_lastdesc;
};

struct ax_chain_onefrag {
	volatile struct ax_desc	*ax_ptr;
	struct mbuf		*ax_mbuf;
	struct ax_chain_onefrag	*ax_nextdesc;
};

struct ax_chain_data {
	struct ax_chain_onefrag	ax_rx_chain[AX_RX_LIST_CNT];
	struct ax_chain		ax_tx_chain[AX_TX_LIST_CNT];

	struct ax_chain_onefrag	*ax_rx_head;

	struct ax_chain		*ax_tx_head;
	struct ax_chain		*ax_tx_tail;
	struct ax_chain		*ax_tx_free;
};

struct ax_type {
	u_int16_t		ax_vid;
	u_int16_t		ax_did;
	char			*ax_name;
};

struct ax_mii_frame {
	u_int8_t		mii_stdelim;
	u_int8_t		mii_opcode;
	u_int8_t		mii_phyaddr;
	u_int8_t		mii_regaddr;
	u_int8_t		mii_turnaround;
	u_int16_t		mii_data;
};

/*
 * MII constants
 */
#define AX_MII_STARTDELIM	0x01
#define AX_MII_READOP		0x02
#define AX_MII_WRITEOP		0x01
#define AX_MII_TURNAROUND	0x02

#define AX_FLAG_FORCEDELAY	1
#define AX_FLAG_SCHEDDELAY	2
#define AX_FLAG_DELAYTIMEO	3	

struct ax_softc {
	struct arpcom		arpcom;		/* interface info */
	struct ifmedia		ifmedia;	/* media info */
	bus_space_handle_t	ax_bhandle;	/* bus space handle */
	bus_space_tag_t		ax_btag;	/* bus space tag */
	struct ax_type		*ax_info;	/* ASIX adapter info */
	struct ax_type		*ax_pinfo;	/* phy info */
	u_int8_t		ax_unit;	/* interface number */
	u_int8_t		ax_type;
	u_int8_t		ax_phy_addr;	/* PHY address */
	u_int8_t		ax_tx_pend;	/* TX pending */
	u_int8_t		ax_want_auto;
	u_int8_t		ax_autoneg;
	caddr_t			ax_ldata_ptr;
	struct ax_list_data	*ax_ldata;
	struct ax_chain_data	ax_cdata;
};

/*
 * register space access macros
 */
#define CSR_WRITE_4(sc, reg, val)	\
	bus_space_write_4(sc->ax_btag, sc->ax_bhandle, reg, val)
#define CSR_WRITE_2(sc, reg, val)	\
	bus_space_write_2(sc->ax_btag, sc->ax_bbhandle, reg, val)
#define CSR_WRITE_1(sc, reg, val)	\
	bus_space_write_1(sc->ax_btag, sc->ax_bhandle, reg, val)

#define CSR_READ_4(sc, reg)		\
	bus_space_read_4(sc->ax_btag, sc->ax_bhandle, reg)
#define CSR_READ_2(sc, reg)		\
	bus_space_read_2(sc->ax_btag, sc->ax_bhandle, reg)
#define CSR_READ_1(sc, reg)		\
	bus_space_read_1(sc->ax_btag, sc->ax_bhandle, reg)

#define AX_TIMEOUT		1000

/*
 * General constants that are fun to know.
 *
 * ASIX PCI vendor ID
 */
#define	AX_VENDORID		0x125B

/*
 * ASIX device IDs.
 */
#define AX_DEVICEID_AX88140A	0x1400

/*
 * The ASIX AX88140 and ASIX AX88141 have the same vendor and
 * device IDs but different revision values.
 */
#define AX_REVISION_88140	0x00
#define AX_REVISION_88141	0x10

/*
 * Texas Instruments PHY identifiers
 */
#define TI_PHY_VENDORID		0x4000
#define TI_PHY_10BT		0x501F
#define TI_PHY_100VGPMI		0x502F

/*
 * These ID values are for the NS DP83840A 10/100 PHY
 */
#define NS_PHY_VENDORID		0x2000
#define NS_PHY_83840A		0x5C0F

/*
 * Level 1 10/100 PHY
 */
#define LEVEL1_PHY_VENDORID	0x7810
#define LEVEL1_PHY_LXT970	0x000F

/*
 * Intel 82555 10/100 PHY
 */
#define INTEL_PHY_VENDORID	0x0A28
#define INTEL_PHY_82555		0x015F

/*
 * SEEQ 80220 10/100 PHY
 */
#define SEEQ_PHY_VENDORID	0x0016
#define SEEQ_PHY_80220		0xF83F


/*
 * PCI low memory base and low I/O base register, and
 * other PCI registers.
 */

#define AX_PCI_VENDOR_ID	0x00
#define AX_PCI_DEVICE_ID	0x02
#define AX_PCI_COMMAND		0x04
#define AX_PCI_STATUS		0x06
#define AX_PCI_REVID		0x08
#define AX_PCI_CLASSCODE	0x09
#define AX_PCI_LATENCY_TIMER	0x0D
#define AX_PCI_HEADER_TYPE	0x0E
#define AX_PCI_LOIO		0x10
#define AX_PCI_LOMEM		0x14
#define AX_PCI_BIOSROM		0x30
#define AX_PCI_INTLINE		0x3C
#define AX_PCI_INTPIN		0x3D
#define AX_PCI_MINGNT		0x3E
#define AX_PCI_MINLAT		0x0F
#define AX_PCI_RESETOPT		0x48
#define AX_PCI_EEPROM_DATA	0x4C

/* power management registers */
#define AX_PCI_CAPID		0x44 /* 8 bits */
#define AX_PCI_NEXTPTR		0x45 /* 8 bits */
#define AX_PCI_PWRMGMTCAP	0x46 /* 16 bits */
#define AX_PCI_PWRMGMTCTRL	0x48 /* 16 bits */

#define AX_PSTATE_MASK		0x0003
#define AX_PSTATE_D0		0x0000
#define AX_PSTATE_D1		0x0001
#define AX_PSTATE_D2		0x0002
#define AX_PSTATE_D3		0x0003
#define AX_PME_EN		0x0010
#define AX_PME_STATUS		0x8000

#define PHY_UNKNOWN		6

#define AX_PHYADDR_MIN		0x00
#define AX_PHYADDR_MAX		0x1F

#define PHY_BMCR		0x00
#define PHY_BMSR		0x01
#define PHY_VENID		0x02
#define PHY_DEVID		0x03
#define PHY_ANAR		0x04
#define PHY_LPAR		0x05
#define PHY_ANEXP		0x06

#define PHY_ANAR_NEXTPAGE	0x8000
#define PHY_ANAR_RSVD0		0x4000
#define PHY_ANAR_TLRFLT		0x2000
#define PHY_ANAR_RSVD1		0x1000
#define PHY_ANAR_RSVD2		0x0800
#define PHY_ANAR_RSVD3		0x0400
#define PHY_ANAR_100BT4		0x0200
#define PHY_ANAR_100BTXFULL	0x0100
#define PHY_ANAR_100BTXHALF	0x0080
#define PHY_ANAR_10BTFULL	0x0040
#define PHY_ANAR_10BTHALF	0x0020
#define PHY_ANAR_PROTO4		0x0010
#define PHY_ANAR_PROTO3		0x0008
#define PHY_ANAR_PROTO2		0x0004
#define PHY_ANAR_PROTO1		0x0002
#define PHY_ANAR_PROTO0		0x0001

/*
 * These are the register definitions for the PHY (physical layer
 * interface chip).
 */
/*
 * PHY BMCR Basic Mode Control Register
 */
#define PHY_BMCR_RESET			0x8000
#define PHY_BMCR_LOOPBK			0x4000
#define PHY_BMCR_SPEEDSEL		0x2000
#define PHY_BMCR_AUTONEGENBL		0x1000
#define PHY_BMCR_RSVD0			0x0800	/* write as zero */
#define PHY_BMCR_ISOLATE		0x0400
#define PHY_BMCR_AUTONEGRSTR		0x0200
#define PHY_BMCR_DUPLEX			0x0100
#define PHY_BMCR_COLLTEST		0x0080
#define PHY_BMCR_RSVD1			0x0040	/* write as zero, don't care */
#define PHY_BMCR_RSVD2			0x0020	/* write as zero, don't care */
#define PHY_BMCR_RSVD3			0x0010	/* write as zero, don't care */
#define PHY_BMCR_RSVD4			0x0008	/* write as zero, don't care */
#define PHY_BMCR_RSVD5			0x0004	/* write as zero, don't care */
#define PHY_BMCR_RSVD6			0x0002	/* write as zero, don't care */
#define PHY_BMCR_RSVD7			0x0001	/* write as zero, don't care */
/*
 * RESET: 1 == software reset, 0 == normal operation
 * Resets status and control registers to default values.
 * Relatches all hardware config values.
 *
 * LOOPBK: 1 == loopback operation enabled, 0 == normal operation
 *
 * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
 * Link speed is selected byt his bit or if auto-negotiation if bit
 * 12 (AUTONEGENBL) is set (in which case the value of this register
 * is ignored).
 *
 * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
 * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
 * determine speed and mode. Should be cleared and then set if PHY configured
 * for no autoneg on startup.
 *
 * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
 *
 * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
 *
 * DUPLEX: 1 == full duplex mode, 0 == half duplex mode
 *
 * COLLTEST: 1 == collision test enabled, 0 == normal operation
 */

/* 
 * PHY, BMSR Basic Mode Status Register 
 */   
#define PHY_BMSR_100BT4			0x8000
#define PHY_BMSR_100BTXFULL		0x4000
#define PHY_BMSR_100BTXHALF		0x2000
#define PHY_BMSR_10BTFULL		0x1000
#define PHY_BMSR_10BTHALF		0x0800
#define PHY_BMSR_RSVD1			0x0400	/* write as zero, don't care */
#define PHY_BMSR_RSVD2			0x0200	/* write as zero, don't care */
#define PHY_BMSR_RSVD3			0x0100	/* write as zero, don't care */
#define PHY_BMSR_RSVD4			0x0080	/* write as zero, don't care */
#define PHY_BMSR_MFPRESUP		0x0040
#define PHY_BMSR_AUTONEGCOMP		0x0020
#define PHY_BMSR_REMFAULT		0x0010
#define PHY_BMSR_CANAUTONEG		0x0008
#define PHY_BMSR_LINKSTAT		0x0004
#define PHY_BMSR_JABBER			0x0002
#define PHY_BMSR_EXTENDED		0x0001

#ifdef __alpha__
#undef vtophys
#define vtophys(va)		(pmap_kextract(((vm_offset_t) (va))) \
					+ 1*1024*1024*1024)
#endif