53c7,8xx.h

基于组件方式开发操作系统的OSKIT源代码

/* NCR53c710 and higher */
#define DSA_REG			0x10	/* DATA structure address */

#define CTEST0_REG_700		0x14	/* Chip test 0 ro */
#define CTEST0_REG_800		0x18	/* Chip test 0 rw, general purpose */
/* 0x80 - 0x04 are reserved */
#define CTEST0_700_RTRG		0x02	/* Real target mode */
#define CTEST0_700_DDIR		0x01	/* Data direction, 1 = 
					 * SCSI bus to host, 0  =
					 * host to SCSI.
					 */

#define CTEST1_REG_700		0x15	/* Chip test 1 ro */
#define CTEST1_REG_800		0x19	/* Chip test 1 ro */
#define CTEST1_FMT3		0x80	/* Identify which byte lanes are empty */
#define CTEST1_FMT2		0x40 	/* in the DMA FIFO */
#define CTEST1_FMT1		0x20
#define CTEST1_FMT0		0x10

#define CTEST1_FFL3		0x08	/* Identify which bytes lanes are full */
#define CTEST1_FFL2		0x04	/* in the DMA FIFO */
#define CTEST1_FFL1		0x02
#define CTEST1_FFL0		0x01

#define CTEST2_REG_700		0x16	/* Chip test 2 ro */
#define CTEST2_REG_800		0x1a	/* Chip test 2 ro */

#define CTEST2_800_DDIR		0x80	/* 1 = SCSI->host */
#define CTEST2_800_SIGP		0x40	/* A copy of SIGP in ISTAT.
					   Reading this register clears */
#define CTEST2_800_CIO		0x20	/* Configured as IO */.
#define CTEST2_800_CM		0x10	/* Configured as memory */

/* 0x80 - 0x40 are reserved on 700 series chips */
#define CTEST2_700_SOFF		0x20	/* SCSI Offset Compare,
					 * As an initiator, this bit is 
					 * one when the synchronous offset
					 * is zero, as a target this bit 
					 * is one when the synchronous 
					 * offset is at the maximum
					 * defined in SXFER
					 */
#define CTEST2_700_SFP		0x10	/* SCSI FIFO parity bit,
					 * reading CTEST3 unloads a byte
					 * from the FIFO and sets this
					 */
#define CTEST2_700_DFP		0x08	/* DMA FIFO parity bit,
					 * reading CTEST6 unloads a byte
					 * from the FIFO and sets this
					 */
#define CTEST2_TEOP		0x04	/* SCSI true end of process,
					 * indicates a totally finished
					 * transfer
					 */
#define CTEST2_DREQ		0x02	/* Data request signal */
/* 0x01 is reserved on 700 series chips */
#define CTEST2_800_DACK		0x01	

/* 
 * Chip test 3 ro 
 * Unloads the bottom byte of the eight deep SCSI synchronous FIFO,
 * check SSTAT2 FIFO full bits to determine size.  Note that a GROSS
 * error results if a read is attempted on this register.  Also note 
 * that 16 and 32 bit reads of this register will cause corruption.
 */
#define CTEST3_REG_700		0x17	
/*  Chip test 3 rw */
#define CTEST3_REG_800		0x1b
#define CTEST3_800_V3		0x80	/* Chip revision */
#define CTEST3_800_V2		0x40
#define CTEST3_800_V1		0x20
#define CTEST3_800_V0		0x10
#define CTEST3_800_FLF		0x08	/* Flush DMA FIFO */
#define CTEST3_800_CLF		0x04	/* Clear DMA FIFO */
#define CTEST3_800_FM		0x02	/* Fetch mode pin */
/* bit 0 is reserved on 800 series chips */

#define CTEST4_REG_700		0x18	/* Chip test 4 rw */
#define CTEST4_REG_800		0x21	/* Chip test 4 rw */
/* 0x80 is reserved on 700 series chips */
#define CTEST4_800_BDIS		0x80	/* Burst mode disable */
#define CTEST4_ZMOD		0x40	/* High impedance mode */
#define CTEST4_SZM		0x20	/* SCSI bus high impedance */
#define CTEST4_700_SLBE		0x10	/* SCSI loopback enabled */
#define CTEST4_800_SRTM		0x10	/* Shadow Register Test Mode */
#define CTEST4_700_SFWR		0x08	/* SCSI FIFO write enable, 
					 * redirects writes from SODL
					 * to the SCSI FIFO.
					 */
#define CTEST4_800_MPEE		0x08	/* Enable parity checking
					   during master cycles on PCI
					   bus */

/* 
 * These bits send the contents of the CTEST6 register to the appropriate
 * byte lane of the 32 bit DMA FIFO.  Normal operation is zero, otherwise 
 * the high bit means the low two bits select the byte lane.
 */
#define CTEST4_FBL2		0x04	
#define CTEST4_FBL1		0x02
#define CTEST4_FBL0		0x01	
#define CTEST4_FBL_MASK		0x07
#define CTEST4_FBL_0		0x04	/* Select DMA FIFO byte lane 0 */
#define CTEST4_FBL_1		0x05	/* Select DMA FIFO byte lane 1 */
#define CTEST4_FBL_2		0x06	/* Select DMA FIFO byte lane 2 */
#define CTEST4_FBL_3		0x07	/* Select DMA FIFO byte lane 3 */
#define CTEST4_800_SAVE		(CTEST4_800_BDIS)


#define CTEST5_REG_700		0x19	/* Chip test 5 rw */
#define CTEST5_REG_800		0x22	/* Chip test 5 rw */
/* 
 * Clock Address Incrementor.  When set, it increments the 
 * DNAD register to the next bus size boundary.  It automatically 
 * resets itself when the operation is complete.
 */
#define CTEST5_ADCK		0x80
/*
 * Clock Byte Counter.  When set, it decrements the DBC register to
 * the next bus size boundary.
 */
#define CTEST5_BBCK		0x40
/*
 * Reset SCSI Offset.  Setting this bit to 1 clears the current offset
 * pointer in the SCSI synchronous offset counter (SSTAT).  This bit
 * is set to 1 if a SCSI Gross Error Condition occurs.  The offset should
 * be cleared when a synchronous transfer fails.  When written, it is 
 * automatically cleared after the SCSI synchronous offset counter is 
 * reset.
 */
/* Bit 5 is reserved on 800 series chips */
#define CTEST5_700_ROFF		0x20
/* 
 * Master Control for Set or Reset pulses. When 1, causes the low 
 * four bits of register to set when set, 0 causes the low bits to
 * clear when set.
 */
#define CTEST5_MASR 		0x10	
#define CTEST5_DDIR		0x08	/* DMA direction */
/*
 * Bits 2-0 are reserved on 800 series chips
 */
#define CTEST5_700_EOP		0x04	/* End of process */
#define CTEST5_700_DREQ		0x02	/* Data request */
#define CTEST5_700_DACK		0x01	/* Data acknowledge */

/* 
 * Chip test 6 rw - writing to this register writes to the byte 
 * lane in the DMA FIFO as determined by the FBL bits in the CTEST4
 * register.
 */
#define CTEST6_REG_700		0x1a
#define CTEST6_REG_800		0x23

#define CTEST7_REG		0x1b	/* Chip test 7 rw */
/* 0x80 - 0x40 are reserved on NCR53c700 and NCR53c700-66 chips */
#define CTEST7_10_CDIS		0x80	/* Cache burst disable */
#define CTEST7_10_SC1		0x40	/* Snoop control bits */
#define CTEST7_10_SC0		0x20	
#define CTEST7_10_SC_MASK	0x60
/* 0x20 is reserved on the NCR53c700 */
#define CTEST7_0060_FM		0x20	/* Fetch mode */
#define CTEST7_STD		0x10	/* Selection timeout disable */
#define CTEST7_DFP		0x08	/* DMA FIFO parity bit for CTEST6 */
#define CTEST7_EVP		0x04	/* 1 = host bus even parity, 0 = odd */
#define CTEST7_10_TT1		0x02	/* Transfer type */
#define CTEST7_00_DC		0x02	/* Set to drive DC low during instruction 
					   fetch */
#define CTEST7_DIFF		0x01	/* Differential mode */

#define CTEST7_SAVE ( CTEST7_EVP | CTEST7_DIFF )


#define TEMP_REG		0x1c	/* through 0x1f Temporary stack rw */

#define DFIFO_REG		0x20	/* DMA FIFO rw */
/* 
 * 0x80 is reserved on the NCR53c710, the CLF and FLF bits have been
 * moved into the CTEST8 register.
 */
#define DFIFO_00_FLF		0x80	/* Flush DMA FIFO to memory */
#define DFIFO_00_CLF		0x40	/* Clear DMA and SCSI FIFOs */
#define DFIFO_BO6		0x40
#define DFIFO_BO5		0x20
#define DFIFO_BO4		0x10
#define DFIFO_BO3		0x08
#define DFIFO_BO2		0x04 
#define DFIFO_BO1		0x02
#define DFIFO_BO0		0x01
#define DFIFO_10_BO_MASK	0x7f	/* 7 bit counter */
#define DFIFO_00_BO_MASK	0x3f	/* 6 bit counter */

/* 
 * Interrupt status rw 
 * Note that this is the only register which can be read while SCSI
 * SCRIPTS are being executed.
 */
#define ISTAT_REG_700		0x21
#define ISTAT_REG_800		0x14
#define ISTAT_ABRT		0x80	/* Software abort, write 
					 *1 to abort, wait for interrupt. */
/* 0x40 and 0x20 are reserved on NCR53c700 and NCR53c700-66 chips */
#define ISTAT_10_SRST		0x40	/* software reset */
#define ISTAT_10_SIGP		0x20	/* signal script */
/* 0x10 is reserved on NCR53c700 series chips */
#define ISTAT_800_SEM		0x10	/* semaphore */
#define ISTAT_CON		0x08	/* 1 when connected */
#define ISTAT_800_INTF		0x04	/* Interrupt on the fly */
#define ISTAT_700_PRE		0x04	/* Pointer register empty.
					 * Set to 1 when DSPS and DSP
					 * registers are empty in pipeline
					 * mode, always set otherwise.
					 */
#define ISTAT_SIP		0x02	/* SCSI interrupt pending from
					 * SCSI portion of SIOP see
					 * SSTAT0
					 */
#define ISTAT_DIP		0x01	/* DMA interrupt pending 
					 * see DSTAT
					 */

/* NCR53c700-66 and NCR53c710 only */
#define CTEST8_REG		0x22	/* Chip test 8 rw */
#define CTEST8_0066_EAS		0x80	/* Enable alternate SCSI clock,
					 * ie read from SCLK/ rather than CLK/
					 */
#define CTEST8_0066_EFM		0x40	/* Enable fetch and master outputs */
#define CTEST8_0066_GRP		0x20	/* Generate Receive Parity for 
					 * pass through.  This insures that 
					 * bad parity won't reach the host 
					 * bus.
					 */
#define CTEST8_0066_TE		0x10	/* TolerANT enable.  Enable 
					 * active negation, should only
					 * be used for slow SCSI 
					 * non-differential.
					 */
#define CTEST8_0066_HSC		0x08	/* Halt SCSI clock */
#define CTEST8_0066_SRA		0x04	/* Shorten REQ/ACK filtering,
					 * must be set for fast SCSI-II
					 * speeds.
					 */
#define CTEST8_0066_DAS		0x02	/* Disable automatic target/initiator
					 * switching.
					 */
#define CTEST8_0066_LDE		0x01	/* Last disconnect enable.
					 * The status of pending 
					 * disconnect is maintained by
					 * the core, eliminating
					 * the possibility of missing a 
					 * selection or reselection
					 * while waiting to fetch a 
					 * WAIT DISCONNECT opcode.
					 */

#define CTEST8_10_V3		0x80	/* Chip revision */
#define CTEST8_10_V2		0x40
#define CTEST8_10_V1		0x20	
#define CTEST8_10_V0		0x10
#define CTEST8_10_V_MASK	0xf0	
#define CTEST8_10_FLF		0x08	/* Flush FIFOs */
#define CTEST8_10_CLF		0x04	/* Clear FIFOs */
#define CTEST8_10_FM		0x02	/* Fetch pin mode */
#define CTEST8_10_SM		0x01	/* Snoop pin mode */


/* 
 * The CTEST9 register may be used to differentiate between a
 * NCR53c700 and a NCR53c710.  
 *
 * Write 0xff to this register.
 * Read it.
 * If the contents are 0xff, it is a NCR53c700
 * If the contents are 0x00, it is a NCR53c700-66 first revision
 * If the contents are some other value, it is some other NCR53c700-66
 */
#define CTEST9_REG_00		0x23	/* Chip test 9 ro */
#define LCRC_REG_10		0x23	

/*
 * 0x24 through 0x27 are the DMA byte counter register.  Instructions
 * write their high 8 bits into the DCMD register, the low 24 bits into
 * the DBC register.
 *
 * Function is dependent on the command type being executed.
 */

 
#define DBC_REG			0x24
/* 
 * For Block Move Instructions, DBC is a 24 bit quantity representing 
 *     the number of bytes to transfer.
 * For Transfer Control Instructions, DBC is bit fielded as follows : 
 */
/* Bits 20 - 23 should be clear */
#define DBC_TCI_TRUE		(1 << 19) 	/* Jump when true */
#define DBC_TCI_COMPARE_DATA	(1 << 18)	/* Compare data */
#define DBC_TCI_COMPARE_PHASE	(1 << 17)	/* Compare phase with DCMD field */
#define DBC_TCI_WAIT_FOR_VALID	(1 << 16)	/* Wait for REQ */
/* Bits 8 - 15 are reserved on some implementations ? */
#define DBC_TCI_MASK_MASK	0xff00 		/* Mask for data compare */
#define DBC_TCI_MASK_SHIFT	8
#define DBC_TCI_DATA_MASK	0xff		/* Data to be compared */ 
#define DBC_TCI_DATA_SHIFT	0

#define DBC_RWRI_IMMEDIATE_MASK	0xff00		/* Immediate data */
#define DBC_RWRI_IMMEDIATE_SHIFT 8		/* Amount to shift */
#define DBC_RWRI_ADDRESS_MASK	0x3f0000	/* Register address */
#define DBC_RWRI_ADDRESS_SHIFT 	16


/*
 * DMA command r/w
 */
#define DCMD_REG		0x27	
#define DCMD_TYPE_MASK		0xc0	/* Masks off type */
#define DCMD_TYPE_BMI		0x00	/* Indicates a Block Move instruction */
#define DCMD_BMI_IO		0x01	/* I/O, CD, and MSG bits selecting   */
#define DCMD_BMI_CD		0x02	/* the phase for the block MOVE      */
#define DCMD_BMI_MSG		0x04	/* instruction 			     */

#define DCMD_BMI_OP_MASK	0x18	/* mask for opcode */
#define DCMD_BMI_OP_MOVE_T	0x00	/* MOVE */
#define DCMD_BMI_OP_MOVE_I	0x08	/* MOVE Initiator */

#define DCMD_BMI_INDIRECT	0x20	/*  Indirect addressing */

#define DCMD_TYPE_TCI		0x80	/* Indicates a Transfer Control 
					   instruction */
#define DCMD_TCI_IO		0x01	/* I/O, CD, and MSG bits selecting   */
#define DCMD_TCI_CD		0x02	/* the phase for the block MOVE      */
#define DCMD_TCI_MSG		0x04	/* instruction 			     */
#define DCMD_TCI_OP_MASK	0x38	/* mask for opcode */
#define DCMD_TCI_OP_JUMP	0x00	/* JUMP */
#define DCMD_TCI_OP_CALL	0x08	/* CALL */
#define DCMD_TCI_OP_RETURN	0x10	/* RETURN */
#define DCMD_TCI_OP_INT		0x18	/* INT */

#define DCMD_TYPE_RWRI		0x40	/* Indicates I/O or register Read/Write
					   instruction */
#define DCMD_RWRI_OPC_MASK	0x38	/* Opcode mask */
#define DCMD_RWRI_OPC_WRITE	0x28	/* Write SFBR to register */
#define DCMD_RWRI_OPC_READ	0x30	/* Read register to SFBR */
#define DCMD_RWRI_OPC_MODIFY	0x38	/* Modify in place */

#define DCMD_RWRI_OP_MASK	0x07
#define DCMD_RWRI_OP_MOVE	0x00
#define DCMD_RWRI_OP_SHL	0x01
#define DCMD_RWRI_OP_OR		0x02
#define DCMD_RWRI_OP_XOR	0x03
#define DCMD_RWRI_OP_AND	0x04
#define DCMD_RWRI_OP_SHR	0x05
#define DCMD_RWRI_OP_ADD	0x06
#define DCMD_RWRI_OP_ADDC	0x07

#define DCMD_TYPE_MMI		0xc0	/* Indicates a Memory Move instruction 
					   (three words) */


#define DNAD_REG		0x28	/* through 0x2b DMA next address for 
					   data */
#define DSP_REG			0x2c	/* through 0x2f DMA SCRIPTS pointer rw */
#define DSPS_REG		0x30	/* through 0x33 DMA SCRIPTS pointer 
					   save rw */
#define DMODE_REG_00		0x34 	/* DMA mode rw */
#define DMODE_00_BL1	0x80	/* Burst length bits */
#define DMODE_00_BL0	0x40
#define DMODE_BL_MASK	0xc0
/* Burst lengths (800) */
#define DMODE_BL_2	0x00	/* 2 transfer */
#define DMODE_BL_4	0x40	/* 4 transfers */
#define DMODE_BL_8	0x80	/* 8 transfers */
#define DMODE_BL_16	0xc0	/* 16 transfers */

#define DMODE_700_BW16	0x20	/* Host buswidth = 16 */
#define DMODE_700_286	0x10	/* 286 mode */
#define DMODE_700_IOM	0x08	/* Transfer to IO port */
#define DMODE_700_FAM	0x04	/* Fixed address mode */
#define DMODE_700_PIPE	0x02	/* Pipeline mode disables 
					 * automatic fetch / exec 
					 */
#define DMODE_MAN	0x01		/* Manual start mode, 
					 * requires a 1 to be written
					 * to the start DMA bit in the DCNTL
					 * register to run scripts 
					 */