am53c974.c

基于组件方式开发操作系统的OSKIT源代码

#include <linux/config.h>
#include <linux/delay.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/errno.h>
#include <linux/pci.h>
#include <linux/string.h>
#include <linux/blk.h>
#include <linux/init.h>

#include <asm/io.h>
#include <asm/system.h>
#include <asm/spinlock.h>

#include "scsi.h"
#include "hosts.h"
#include "AM53C974.h"
#include "constants.h"
#include "sd.h"

/* AM53/79C974 (PCscsi) driver release 0.5

 * The architecture and much of the code of this device
 * driver was originally developed by Drew Eckhardt for
 * the NCR5380. The following copyrights apply:
 *  For the architecture and all pieces of code which can also be found 
 *    in the NCR5380 device driver:
 *   Copyright 1993, Drew Eckhardt
 *      Visionary Computing 
 *      (Unix and Linux consulting and custom programming)
 *      [e-mail]
 *      [phone]
 *
 *  The AM53C974_nobios_detect code was originally developed by
 *   Robin Cutshaw ([e-mail]) and is used here in a 
 *   slightly modified form.
 *
 *  PCI detection rewritten by Martin Mares <[e-mail]>
 *
 *  For the remaining code:
 *    Copyright 1994, D. Frieauff
 *    EMail: [e-mail]
 *    Phone: x49-7545-8-2256 , x49-7541-42305
 */

/*
 * $Log: AM53C974.c,v $
 */

#ifdef AM53C974_DEBUG
#define DEB(x) x
#ifdef AM53C974_DEBUG_KEYWAIT
#define KEYWAIT() AM53C974_keywait()
#else
#define KEYWAIT()
#endif
#ifdef AM53C974_DEBUG_INIT
#define DEB_INIT(x) x
#else
#define DEB_INIT(x)
#endif
#ifdef AM53C974_DEBUG_MSG
#define DEB_MSG(x) x
#else
#define DEB_MSG(x)
#endif
#ifdef AM53C974_DEB_RESEL
#define DEB_RESEL(x) x
#else
#define DEB_RESEL(x)
#endif
#ifdef AM53C974_DEBUG_QUEUE
#define DEB_QUEUE(x) x
#define LIST(x,y) {printk("LINE:%d   Adding %p to %p\n", __LINE__, (void*)(x), (void*)(y)); if ((x)==(y)) udelay(5); }
#define REMOVE(w,x,y,z) {printk("LINE:%d   Removing: %p->%p  %p->%p \n", __LINE__, (void*)(w), (void*)(x), (void*)(y), (void*)(z)); if ((x)==(y)) udelay(5); }
#else
#define DEB_QUEUE(x)
#define LIST(x,y)
#define REMOVE(w,x,y,z)
#endif
#ifdef AM53C974_DEBUG_INFO
#define DEB_INFO(x) x
#else
#define DEB_INFO(x)
#endif
#ifdef AM53C974_DEBUG_LINKED
#define DEB_LINKED(x) x
#else
#define DEB_LINKED(x)
#endif
#ifdef AM53C974_DEBUG_INTR
#define DEB_INTR(x) x
#else
#define DEB_INTR(x)
#endif
#else
#define DEB_INIT(x)
#define DEB(x)
#define DEB_QUEUE(x)
#define LIST(x,y)
#define REMOVE(w,x,y,z)
#define DEB_INFO(x)
#define DEB_LINKED(x)
#define DEB_INTR(x)
#define DEB_MSG(x)
#define DEB_RESEL(x)
#define KEYWAIT()
#endif
#ifdef AM53C974_DEBUG_ABORT
#define DEB_ABORT(x) x
#else
#define DEB_ABORT(x)
#endif

#ifdef VERBOSE_AM53C974_DEBUG
#define VDEB(x) x
#else
#define VDEB(x)
#endif

#define INSIDE(x,l,h) ( ((x) >= (l)) && ((x) <= (h)) )


#include <scsi/scsicam.h>

/***************************************************************************************
* Default setting of the controller's SCSI id. Edit and uncomment this only if your    *
* BIOS does not correctly initialize the controller's SCSI id.                         *
* If you don't get a warning during boot, it is correctly initialized.                 *
****************************************************************************************/
/* #define AM53C974_SCSI_ID 7 */

/***************************************************************************************
* Default settings for sync. negotiation enable, transfer rate and sync. offset.       *
* These settings can be replaced by LILO overrides (append) with the following syntax:          *
* AM53C974=host-scsi-id, target-scsi-id, max-rate, max-offset                          *
* Sync. negotiation is disabled by default and will be enabled for those targets which *
* are specified in the LILO override                                                   *
****************************************************************************************/
#define DEFAULT_SYNC_NEGOTIATION_ENABLED 0	/* 0 or 1 */
#define DEFAULT_RATE			 5	/* MHz, min: 3; max: 10 */
#define DEFAULT_SYNC_OFFSET		 0	/* bytes, min: 0; max: 15; use 0 for async. mode */

/***************************************************************************************
* If defined, don't allow targets to disconnect during commands.  This will reduce     *
* performance, but may be worthwhile if you suspect the driver of corrupting data when *
* a disconnect happens.                                                                *
***************************************************************************************/
#define AM53C974_PROHIBIT_DISCONNECT

/* --------------------- don't edit below here  --------------------- */

#define AM53C974_DRIVER_REVISION_MAJOR 0
#define AM53C974_DRIVER_REVISION_MINOR 5
#define SEPARATOR_LINE  \
"--------------------------------------------------------------------------\n"

/* debug control */
/* #define AM53C974_DEBUG */
/* #define AM53C974_DEBUG_MSG */
/* #define AM53C974_DEBUG_KEYWAIT */
/* #define AM53C974_DEBUG_INIT */
/* #define AM53C974_DEBUG_QUEUE */
/* #define AM53C974_DEBUG_INFO */
/* #define AM53C974_DEBUG_LINKED */
/* #define VERBOSE_AM53C974_DEBUG */
/* #define AM53C974_DEBUG_INTR */
/* #define AM53C974_DEB_RESEL */
#define AM53C974_DEBUG_ABORT
/* #define AM53C974_OPTION_DEBUG_PROBE_ONLY */

/* special options/constants */
#define DEF_CLK                 40	/* chip clock freq. in MHz */
#define MIN_PERIOD               4	/* for negotiation: min. number of clocks per cycle */
#define MAX_PERIOD              13	/* for negotiation: max. number of clocks per cycle */
#define MAX_OFFSET              15	/* for negotiation: max. offset (0=async) */

#define DEF_SCSI_TIMEOUT        245	/* STIMREG value, 40 Mhz */
#define DEF_STP                 8	/* STPREG value assuming 5.0 MB/sec, FASTCLK, FASTSCSI */
#define DEF_SOF_RAD             0	/* REQ/ACK deassertion delay */
#define DEF_SOF_RAA             0	/* REQ/ACK assertion delay */
#define DEF_ETM                 0	/* CNTLREG1, ext. timing mode */
#define DEF_PERE                1	/* CNTLREG1, parity error reporting */
#define DEF_CLKF                0	/* CLKFREG,  0=40 Mhz */
#define DEF_ENF                 1	/* CNTLREG2, enable features */
#define DEF_ADIDCHK             0	/* CNTLREG3, additional ID check */
#define DEF_FASTSCSI            1	/* CNTLREG3, fast SCSI */
#define DEF_FASTCLK             1	/* CNTLREG3, fast clocking, 5 MB/sec at 40MHz chip clk */
#define DEF_GLITCH              1	/* CNTLREG4, glitch eater, 0=12ns, 1=35ns, 2=25ns, 3=off */
#define DEF_PWD                 0	/* CNTLREG4, reduced power feature */
#define DEF_RAE                 0	/* CNTLREG4, RAE active negation on REQ, ACK only */
#define DEF_RADE                1	/* 1CNTLREG4, active negation on REQ, ACK and data */

/*** SCSI block ***/
#define CTCLREG		    	0x00	/* r      current transf. count, low byte    */
#define CTCMREG		   	0x04	/* r      current transf. count, middle byte */
#define CTCHREG		    	0x38	/* r      current transf. count, high byte   */
#define STCLREG		    	0x00	/* w      start transf. count, low byte      */
#define STCMREG		    	0x04	/* w      start transf. count, middle byte   */
#define STCHREG		    	0x38	/* w      start transf. count, high byte     */
#define FFREG		    	0x08	/* rw     SCSI FIFO reg.                     */
#define STIMREG		    	0x14	/* w      SCSI timeout reg.                  */

#define SDIDREG		    	0x10	/* w      SCSI destination ID reg.           */
#define SDIREG_MASK		0x07	/* mask                                      */

#define STPREG		    	0x18	/* w      synchronous transf. period reg.    */
#define STPREG_STP		0x1F	/* synchr. transfer period                   */

#define CLKFREG		    	0x24	/* w      clock factor reg.                  */
#define CLKFREG_MASK		0x07	/* mask                                      */

#define CMDREG		    	0x0C	/* rw     SCSI command reg.                  */
#define CMDREG_DMA         	0x80	/* set DMA mode (set together with opcodes below) */
#define CMDREG_IT          	0x10	/* information transfer              */
#define CMDREG_ICCS		0x11	/* initiator command complete steps          */
#define CMDREG_MA		0x12	/* message accepted                          */
#define CMDREG_TPB		0x98	/* transfer pad bytes, DMA mode only         */
#define CMDREG_SATN		0x1A	/* set ATN                                   */
#define CMDREG_RATN		0x1B	/* reset ATN                                 */
#define CMDREG_SOAS		0x41	/* select without ATN steps                  */
#define CMDREG_SAS		0x42	/* select with ATN steps (1 msg byte)        */
#define CMDREG_SASS		0x43	/* select with ATN and stop steps            */
#define CMDREG_ESR		0x44	/* enable selection/reselection      */
#define CMDREG_DSR		0x45	/* disable selection/reselection     */
#define CMDREG_SA3S		0x46	/* select with ATN 3 steps  (3 msg bytes)  */
#define CMDREG_NOP		0x00	/* no operation                      */
#define CMDREG_CFIFO		0x01	/* clear FIFO                                */
#define CMDREG_RDEV		0x02	/* reset device                      */
#define CMDREG_RBUS		0x03	/* reset SCSI bus                            */

#define STATREG		    	0x10	/* r      SCSI status reg.                   */
#define STATREG_INT		0x80	/* SCSI interrupt condition detected         */
#define STATREG_IOE		0x40	/* SCSI illegal operation error detected   */
#define STATREG_PE		0x20	/* SCSI parity error detected                */
#define STATREG_CTZ		0x10	/* CTC reg decremented to zero               */
#define STATREG_MSG		0x04	/* SCSI MSG phase (latched?)                 */
#define STATREG_CD		0x02	/* SCSI C/D phase (latched?)                 */
#define STATREG_IO		0x01	/* SCSI I/O phase (latched?)                 */
#define STATREG_PHASE           0x07	/* SCSI phase mask                           */

#define INSTREG		    	0x14	/* r      interrupt status reg.              */
#define INSTREG_SRST		0x80	/* SCSI reset detected                       */
#define INSTREG_ICMD		0x40	/* SCSI invalid command detected     */
#define INSTREG_DIS		0x20	/* target disconnected or sel/resel timeout */
#define INSTREG_SR		0x10	/* device on bus has service request       */
#define INSTREG_SO		0x08	/* successful operation                      */
#define INSTREG_RESEL		0x04	/* device reselected as initiator    */

#define ISREG		    	0x18	/* r      internal state reg.                */
#define ISREG_SOF		0x08	/* synchronous offset flag (act. low)        */
#define ISREG_IS		0x07	/* status of intermediate op.                */
#define ISREG_OK_NO_STOP        0x04	/* selection successful                    */
#define ISREG_OK_STOP           0x01	/* selection successful                    */

#define CFIREG		    	0x1C	/* r      current FIFO/internal state reg.   */
#define CFIREG_IS		0xE0	/* status of intermediate op.                */
#define CFIREG_CF		0x1F	/* number of bytes in SCSI FIFO              */

#define SOFREG		    	0x1C	/* w      synchr. offset reg.                */
#define SOFREG_RAD		0xC0	/* REQ/ACK deassertion delay (sync.)         */
#define SOFREG_RAA		0x30	/* REQ/ACK assertion delay (sync.)           */
#define SOFREG_SO		0x0F	/* synch. offset (sync.)             */

#define CNTLREG1	    	0x20	/* rw     control register one               */
#define CNTLREG1_ETM		0x80	/* set extended timing mode                  */
#define CNTLREG1_DISR		0x40	/* disable interrupt on SCSI reset           */
#define CNTLREG1_PERE		0x10	/* enable parity error reporting     */
#define CNTLREG1_SID		0x07	/* host adapter SCSI ID                      */

#define CNTLREG2	    	0x2C	/* rw     control register two               */
#define CNTLREG2_ENF		0x40	/* enable features                           */

#define CNTLREG3	    	0x30	/* rw     control register three             */
#define CNTLREG3_ADIDCHK	0x80	/* additional ID check                       */
#define CNTLREG3_FASTSCSI	0x10	/* fast SCSI                                 */
#define CNTLREG3_FASTCLK	0x08	/* fast SCSI clocking                        */

#define CNTLREG4	    	0x34	/* rw     control register four              */
#define CNTLREG4_GLITCH		0xC0	/* glitch eater                              */
#define CNTLREG4_PWD		0x20	/* reduced power feature             */
#define CNTLREG4_RAE		0x08	/* write only, active negot. ctrl.           */
#define CNTLREG4_RADE		0x04	/* active negot. ctrl.                       */
#define CNTLREG4_RES		0x10	/* reserved bit, must be 1                   */

/*** DMA block ***/
#define DMACMD		    	0x40	/* rw     command                            */
#define DMACMD_DIR		0x80	/* transfer direction (1=read from device) */
#define DMACMD_INTE_D		0x40	/* DMA transfer interrupt enable     */
#define DMACMD_INTE_P		0x20	/* page transfer interrupt enable            */
#define DMACMD_MDL		0x10	/* map to memory descriptor list     */
#define DMACMD_DIAG		0x04	/* diagnostics, set to 0             */
#define DMACMD_IDLE 		0x00	/* idle cmd                                  */
#define DMACMD_BLAST		0x01	/* flush FIFO to memory                      */
#define DMACMD_ABORT		0x02	/* terminate DMA                     */
#define DMACMD_START		0x03	/* start DMA                                 */

#define DMASTATUS	      	0x54	/* r      status register                    */
#define DMASTATUS_BCMPLT	0x20	/* BLAST complete                    */
#define DMASTATUS_SCSIINT	0x10	/* SCSI interrupt pending            */
#define DMASTATUS_DONE		0x08	/* DMA transfer terminated                   */
#define DMASTATUS_ABORT		0x04	/* DMA transfer aborted                      */
#define DMASTATUS_ERROR		0x02	/* DMA transfer error                        */
#define DMASTATUS_PWDN		0x02	/* power down indicator                      */

#define DMASTC		    	0x44	/* rw     starting transfer count            */
#define DMASPA		    	0x48	/* rw     starting physical address          */
#define DMAWBC		    	0x4C	/* r      working byte counter               */
#define DMAWAC		    	0x50	/* r      working address counter            */
#define DMASMDLA	    	0x58	/* rw     starting MDL address               */
#define DMAWMAC		    	0x5C	/* r      working MDL counter                */

/*** SCSI phases ***/
#define PHASE_MSGIN             0x07
#define PHASE_MSGOUT            0x06
#define PHASE_RES_1             0x05
#define PHASE_RES_0             0x04
#define PHASE_STATIN            0x03
#define PHASE_CMDOUT            0x02
#define PHASE_DATAIN            0x01
#define PHASE_DATAOUT           0x00


#define AM53C974_local_declare()	unsigned long io_port
#define AM53C974_setio(instance)	io_port = instance->io_port
#define AM53C974_read_8(addr)           inb(io_port + (addr))
#define AM53C974_write_8(addr,x)        outb((x), io_port + (addr))
#define AM53C974_read_16(addr)          inw(io_port + (addr))
#define AM53C974_write_16(addr,x)       outw((x), io_port + (addr))
#define AM53C974_read_32(addr)          inl(io_port + (addr))
#define AM53C974_write_32(addr,x)       outl((x), io_port + (addr))

#define AM53C974_poll_int()             { do { statreg = AM53C974_read_8(STATREG); } \
                                             while (!(statreg & STATREG_INT)) ; \
                                          AM53C974_read_8(INSTREG) ; }	/* clear int */
#define AM53C974_cfifo()		(AM53C974_read_8(CFIREG) & CFIREG_CF)

/* These are "special" values for the tag parameter passed to AM53C974_select. */