ml674000.h

一些典型的阿arm嵌入式应用程序集锦！

#define DMACDAD1    (DMA_BASE+0x020C)   /* Channel 1 Destination Address register */
#define DMACSIZ1    (DMA_BASE+0x0210)   /* Channel 1 Transfer Size register */
#define DMACCINT1   (DMA_BASE+0x0214)   /* Channel 1 interrupt Clear register */

/* bit field of DMAMOD register */
#define DMAMOD_FIX  0x0000  /* Priority of DMA channel : CH0 > CH1 */
#define DMAMOD_RR   0x0001  /* Priority of DMA channel : Round robin */

/* bit field of DMASTA register */
#define DMASTA_STA0 0x0001  /* Non-transmitted data is in CH0 */
#define DMASTA_STA1 0x0002  /* Non-transmitted data is in CH1 */

/* bit field of DMAINT register */
#define DMAINT_IREQ0    0x00000001  /* CH0 interrupt */
#define DMAINT_IREQ1    0x00000002  /* CH1 interrupt */
#define DMAINT_ISTA0    0x00000100  /* CH0 abnormal end */
#define DMAINT_ISTA1    0x00000200  /* CH1 abnormal end */
#define DMAINT_ISTP0    0x00010000  /* CH0 abnormal end situation */
#define DMAINT_ISTP1    0x00020000  /* CH1 abnormal end situation */

/* bit field of DMAMSK0,1 register */
#define DMACMSK_MSK  0x00000001  /* Mask */

/* bit field of DMATMOD0,1 register */
#define DMACTMOD_ARQ    0x00000001  /* Auto request */
#define DMACTMOD_ERQ    0x00000000  /* External request */
#define DMACTMOD_BYTE   0x00000000  /* Byte transmission */
#define DMACTMOD_HWORD  0x00000002  /* Half word transmission */
#define DMACTMOD_WORD   0x00000004  /* Word transmission */
#define DMACTMOD_SFA    0x00000000  /* Source data type(fixed address device) */
#define DMACTMOD_SIA    0x00000008  /* Source data type(incremental address device) */
#define DMACTMOD_DFA    0x00000000  /* Destination data type(fixed address device) */
#define DMACTMOD_DIA    0x00000010  /* Destination data type(incremental address device) */
#define DMACTMOD_BM     0x00000000  /* Bus request mode(burst mode) */
#define DMACTMOD_CSM    0x00000020  /* Bus request mode(cycle steal mode) */
#define DMACTMOD_IMK    0x00000040  /* interrupt mask */


/*****************************************************/
/*    interrupt control register                     */
/*****************************************************/
#define EIC_BASE    0x7BF00000  /* base address */
#define IRS         (EIC_BASE+0x00) /* Extended interrupt Size register */
#define IRCL        (EIC_BASE+0x04) /* Extended interrupt Clear register */
#define IRQA        (EIC_BASE+0x10) /* Extended interrupt IRQ register */
#define IDM         (EIC_BASE+0x14) /* Extended interrupt Mode control register */
#define ILC         (EIC_BASE+0x18) /* Extended interrupt IRQ Level control register */

/* bit field of IRQA register */
#define IRQA_IRQ16  0x00000001  /* IRQ16 */
#define IRQA_IRQ17  0x00000002  /* IRQ17 */
#define IRQA_IRQ18  0x00000004  /* IRQ18 */
#define IRQA_IRQ19  0x00000008  /* IRQ19 */
#define IRQA_IRQ20  0x00000010  /* IRQ20 */
#define IRQA_IRQ21  0x00000020  /* IRQ21 */
#define IRQA_IRQ22  0x00000040  /* IRQ22 */
#define IRQA_IRQ23  0x00000080  /* IRQ23 */
#define IRQA_IRQ24  0x00000100  /* IRQ24 */
#define IRQA_IRQ25  0x00000200  /* IRQ25 */
#define IRQA_IRQ26  0x00000400  /* IRQ26 */
#define IRQA_IRQ27  0x00000800  /* IRQ27 */
#define IRQA_IRQ28  0x00001000  /* IRQ28 */
#define IRQA_IRQ29  0x00002000  /* IRQ29 */
#define IRQA_IRQ30  0x00004000  /* IRQ30 */
#define IRQA_IRQ31  0x00008000  /* IRQ31 */

/* bit field of IDM register */
#define IDM_IDM16   0x00000001  /* IRQ16, IRQ17 */
#define IDM_IDM18   0x00000004  /* IRQ18, IRQ19 */
#define IDM_IDM20   0x00000010  /* IRQ20, IRQ21 */
#define IDM_IDM22   0x00000040  /* IRQ22, IRQ23 */
#define IDM_IDM24   0x00000100  /* IRQ24, IRQ25 */
#define IDM_IDM26   0x00000400  /* IRQ26, IRQ27 */
#define IDM_IDM28   0x00001000  /* IRQ28, IRQ29 */
#define IDM_IDM30   0x00004000  /* IRQ30, IRQ31 */
#define IDM_IDMP16  0x00000002  /* IRQ16, IRQ17 */
#define IDM_IDMP18  0x00000008  /* IRQ18, IRQ19 */
#define IDM_IDMP20  0x00000020  /* IRQ20, IRQ21 */
#define IDM_IDMP22  0x00000080  /* IRQ22, IRQ23 */
#define IDM_IDMP24  0x00000200  /* IRQ24, IRQ25 */
#define IDM_IDMP26  0x00000800  /* IRQ26, IRQ27 */
#define IDM_IDMP28  0x00002000  /* IRQ28, IRQ29 */
#define IDM_IDMP30  0x00008000  /* IRQ30, IRQ31 */
#define IDM_INT_L_L 0x00000000  /* level sensing, interrupt occurs when 'L' */
#define IDM_INT_L_H 0x0000AAAA  /* level sensing, interrupt occurs when 'H' */
#define IDM_INT_E_F 0x00005555  /* edge sensing, interrupt occurs when falling edge */
#define IDM_INT_E_R 0x0000FFFF  /* edge sensing, interrupt occurs when rising edge */
#define IDM_IRQ16   0x00000003	/* IRQ16 */
#define IDM_IRQ17   0x00000003	/* IRQ17 */
#define IDM_IRQ18   0x0000000C	/* IRQ18 */
#define IDM_IRQ19   0x0000000C	/* IRQ19 */
#define IDM_IRQ20   0x00000030	/* IRQ20 */
#define IDM_IRQ21   0x00000030	/* IRQ21 */
#define IDM_IRQ22   0x000000C0	/* IRQ22 */
#define IDM_IRQ23   0x000000C0	/* IRQ23 */
#define IDM_IRQ24   0x00000300	/* IRQ24 */
#define IDM_IRQ25   0x00000300	/* IRQ25 */
#define IDM_IRQ26   0x00000C00	/* IRQ26 */
#define IDM_IRQ27   0x00000C00	/* IRQ27 */
#define IDM_IRQ28   0x00003000	/* IRQ28 */
#define IDM_IRQ29   0x00003000	/* IRQ29 */
#define IDM_IRQ30   0x0000C000	/* IRQ30 */
#define IDM_IRQ31   0x0000C000	/* IRQ31 */


/* bit field of ILC register */
#define ILC_INT_LV1 0x11111111  /* interrupt level 1 */
#define ILC_INT_LV2 0x22222222  /* interrupt level 2 */
#define ILC_INT_LV3 0x33333333  /* interrupt level 3 */
#define ILC_INT_LV4 0x44444444  /* interrupt level 4 */
#define ILC_INT_LV5 0x55555555  /* interrupt level 5 */
#define ILC_INT_LV6 0x66666666  /* interrupt level 6 */
#define ILC_INT_LV7 0x77777777  /* interrupt level 7 */
#define ILC_ILC16   0x00000007  /* IRQ16, IRQ17 */
#define ILC_ILC18   0x00000070  /* IRQ18, IRQ19 */
#define ILC_ILC20   0x00000700  /* IRQ20, IRQ21 */
#define ILC_ILC22   0x00007000  /* IRQ22, IRQ23 */
#define ILC_ILC24   0x00070000  /* IRQ24, IRQ25 */
#define ILC_ILC26   0x00700000  /* IRQ26, IRQ27 */
#define ILC_ILC28   0x07000000  /* IRQ28, IRQ29 */
#define ILC_ILC30   0x70000000  /* IRQ30, IRQ31 */


/*****************************************************/
/*    DRAM control register                          */
/*****************************************************/
#define DCR_BASE    0x78180000  /* base address */
#define DBWC        (DCR_BASE+0x00) /* DRAM Bus Width control register */
#define DRMC        (DCR_BASE+0x04) /* DRAM control register */
#define DRPC        (DCR_BASE+0x08) /* DRAM Attribute parameter Setup register */
#define SDMD        (DCR_BASE+0x0C) /* SDRAM Mode Setup register */
#define DCMD        (DCR_BASE+0x10) /* DRAM Command register */
#define RFSH0       (DCR_BASE+0x14) /* DRAM Refresh Cycle register 0 */
#define PDWC        (DCR_BASE+0x18) /* Power Down Mode control register */
#define RFSH1       (DCR_BASE+0x1C) /* DRAM Refresh Cycle register 1 */

/* bit field of DBWC register */
#define DBWC_UM         0x00        /* un-mounted */
#define DBWC_8bit       0x01        /* 8bit width */
#define DBWC_16bit      0x02        /* 16bit width */
#define DBWC_32bit      0x03        /* 32bit width */

/* bit field of DRMC register */
#define DRMC_8bit       0x00        /* DRAM column length : 8bit */
#define DRMC_9bit       0x01        /* DRAM column length : 9bit */
#define DRMC_10bit      0x02        /* DRAM column length : 10bit */
#define DRMC_SDRAM      0x00        /* DRAM architecture : SDRAM */
#define DRMC_EDO        0x04        /* DRAM architecture : EDO-DRAM */
#define DRMC_2CLK       0x00        /* SDRAM pre-charge latency : 2clock */
#define DRMC_CAS        0x10        /* SDRAM pre-charge latency : same as CAS latency */
#define DRMC_PD_DIS     0x00        /* automatic shift to SDRAM power down mode : disable */
#define DRMC_PD_EN      0x40        /* automatic shift to SDRAM power down mode : enable */
#define DRMC_CBR_STOP   0x00        /* CBR refresh : stop */
#define DRMC_CBR_EXE    0x80        /* CBR refresh : execution */

/* bit field of SDMD register */
#define SDMD_CL2        0x00        /* SDRAM CAS latency : 2 */
#define SDMD_CL3        0x01        /* SDRAM CAS latency : 3 */
#define SDMD_MODEWR     0x80        /* setting operation : valid */

/* bit field of DCMD register */
#define DCMD_S_PALL     0x04        /* SDRAM all bank pre-charge command */
#define DCMD_S_REF      0x05        /* SDRAM CBR refresh command */
#define DCMD_S_SELF     0x06        /* SDRAM self refresh start command */
#define DCMD_S_SREX     0x07        /* SDRAM self refresh stop command */
#define DCMD_EDO_PC     0x04        /* EDO-DRAM pre-charge cycle */
#define DCMD_EDO_REF    0x05        /* EDO-DRAM CBR refresh cycle */
#define DCMD_EDO_SELF   0x06        /* EDO-DRAM self refresh start cycle */
#define DCMD_EDO_SREX   0x07        /* EDO-DRAM self refresh stop cycle */

/* bit field of RFSH register */
#define RFSH0_DOUBLE    0x00        /* refresh frequency = refreqa * 2 */
#define RFSH0_SINGLE    0x01        /* refresh frequency = refreqa */

/* bit field of PDWC register */
#define PDWC_1  0x00    /* when  1 or more cycles of idol state continue,
                           it shifts to power down mode. */
#define PDWC_2  0x01    /*                   :                   */
#define PDWC_3  0x02    /*                   :                   */
#define PDWC_4  0x03    /*                   :                   */
#define PDWC_5  0x04    /*                   :                   */
#define PDWC_6  0x05    /*                   :                   */
#define PDWC_7  0x06    /*                   :                   */
#define PDWC_8  0x07    /*                   :                   */
#define PDWC_9  0x08    /*                   :                   */
#define PDWC_10 0x09    /*                   :                   */
#define PDWC_11 0x0A    /*                   :                   */
#define PDWC_12 0x0B    /*                   :                   */
#define PDWC_13 0x0C    /*                   :                   */
#define PDWC_14 0x0D    /*                   :                   */
#define PDWC_15 0x0E    /*                   :                   */
#define PDWC_16 0x0F    /* when 16 or more cycles of idol state continue,
                           it shifts to power down mode. */


/*****************************************************/
/*    Chip configuration register                    */
/*****************************************************/
#define CCR_BASE    0xB7000000  /* base address */
#define GPCTL       (CCR_BASE+0x00) /* port function control register */
#define BCKCTL      (CCR_BASE+0x04) /* clock control register */
#define CSSW        (CCR_BASE+0x10) /* external ROM/RAM chip cell control register */

/* bit field of SCCW register */
#define CSSW_SET    0xA5A5  /* set CHG */
#define CSSW_RESET  0x5A5A  /* reset CHG */


/*****************************************************/
/*    interrupt number                               */
/*****************************************************/
#define INT_SYSTEM_TIMER    0
#define INT_WDT             1
#define INT_IVT             2
#define INT_GPIOA           4
#define INT_GPIOB           5
#define INT_SOFTIRQ         8
#define INT_UART            9
#define INT_SIO             10
#define INT_AD              11
#define INT_PWM0            12
#define INT_PWM1            13
#define INT_TIMER0          16
#define INT_TIMER1          17
#define INT_TIMER2          18
#define INT_TIMER3          19
#define INT_TIMER4          20
#define INT_TIMER5          21
#define INT_DMA0            24
#define INT_DMA1            25
#define INT_EX0             28
#define INT_EX1             29
#define INT_EX2             30
#define INT_EX3             31

#ifdef __cplusplus
};      /* End of 'extern "C"' */
#endif
#endif  /* End of ML674000.h */