ml674000.h

一些典型的阿arm嵌入式应用程序集锦！

#define TIMECNTL_INT    0x0000  /* interval timer */

/* bit field of TIMESTAT0-5 register */
#define TIMESTAT_STATUS 0x0001  /* status bit */

/*****************************************************/
/*    Watch Dog Timer control register               */
/*****************************************************/
#define WDT_BASE    0xB7E00000  /* base address */
#define WDTCON      (WDT_BASE+0x00) /* Watch Dog Timer control register */
#define WDTBCON     (WDT_BASE+0x04) /* time base counter control register */
#define WDSTAT     (WDT_BASE+0x14) /* Watch Dog Timer status register */

/* bit field of WDTCON */
#define WDTCON_0xC3 0xC3    /* 0xC3 */
#define WDTCON_0x3C 0x3C    /* 0x3C */

/* bit field of WDTBCON */
#define WDTBCON_WDHLT   0x80  /* HALT */
#define WDTBCON_RESET   0x20  /* reset */
#define WDTBCON_INT     0x00  /* generate interrupt */
#define WDTBCON_ITEN    0x10  /* enable interval timer */
#define WDTBCON_ITM     0x08  /* interval timer mode */
#define WDTBCON_WDTM    0x00  /* WDT mode */
#define WDTBCON_CLK32   0x00  /* CPUCLK/32 */
#define WDTBCON_CLK64   0x01  /* CPUCLK/64 */
#define WDTBCON_CLK128  0x02  /* CPUCLK/128 */
#define WDTBCON_CLK256  0x03  /* CPUCLK/256 */
#define WDTBCON_WE      0x5A  /* enable writing to this register */

/* bit field of WDTSTAT */
#define WDSTAT_RSTWDT  0x01  /* reset by WDT */
#define WDSTAT_RSTPWON 0x00  /* reset by power on */
#define WDSTAT_WDTIST  0x10  /* WDT interrupt */
#define WDSTAT_IVTIST  0x20  /* IVT interrupt */


/*****************************************************/
/*    UART control register                          */
/*****************************************************/
#define UCR_BASE    0xB7B00000  /* base address */
#define UARTRBR     (UCR_BASE+0x00) /* receiver buffer register */
#define UARTTHR     (UCR_BASE+0x00) /* transmitter buffer register */
#define UARTIER     (UCR_BASE+0x04) /* interrupt enable register */
#define UARTIIR     (UCR_BASE+0x08) /* interrupt identification */
#define UARTFCR     (UCR_BASE+0x08) /* FIFO control register */
#define UARTLCR     (UCR_BASE+0x0C) /* line control register */
#define UARTMCR     (UCR_BASE+0x10) /* modem control register */
#define UARTLSR     (UCR_BASE+0x14) /* line status register */
#define UARTMSR     (UCR_BASE+0x18) /* modem status register */
#define UARTSCR     (UCR_BASE+0x1C) /* scratchpad register */
#define UARTDLL     (UCR_BASE+0x00) /* divisor latch(LSB) */
#define UARTDLM     (UCR_BASE+0x04) /* divisor latch(MSB) */

/* bit field of UARTLCR register */
#define UARTLCR_LEN5    0x0000  /* data length : 5bit */
#define UARTLCR_LEN6    0x0001  /* data length : 6bit */
#define UARTLCR_LEN7    0x0002  /* data length : 7bit */
#define UARTLCR_LEN8    0x0003  /* data length : 8bit */
#define UARTLCR_STB1    0x0000  /* stop bit : 1 */
#define UARTLCR_STB2    0x0004  /* stop bit : 2(data length 6-8) */
#define UARTLCR_STB1_5  0x0004  /* stop bit : 1.5(data length 5) */
#define UARTLCR_PEN     0x0008  /* parity enabled */
#define UARTLCR_PDIS    0x0000  /* parity disabled */
#define UARTLCR_EVN     0x0010  /* even parity */
#define UARTLCR_ODD     0x0000  /* odd parity */
#define UARTLCR_SP      0x0020  /* stick parity */
#define UARTLCR_BRK     0x0040  /* break delivery */
#define UARTLCR_DLAB    0x0080  /* devisor latch access bit */

/* bit field of UARTLSR register */
#define UARTLSR_DR      0x0001  /* data ready */
#define UARTLSR_OE      0x0002  /* overrun error */
#define UARTLSR_PE      0x0004  /* parity error */
#define UARTLSR_FE      0x0008  /* framing error */
#define UARTLSR_BI      0x0010  /* break interrupt */
#define UARTLSR_THRE    0x0020  /* transmitter holding register empty */
#define UARTLSR_TEMT    0x0040  /* transmitter empty */
#define UARTLSR_ERF     0x0080  /* receiver FIFO error */

/* bit field of UARTFCR register */
#define UARTFCR_FE      0x0001  /* FIFO enable */
#define UARTFCR_FD      0x0000  /* FIFO disable */
#define UARTFCR_RFCLR   0x0002  /* receiver FIFO clear */
#define UARTFCR_TFCLR   0x0004  /* transmitter FIFO clear */
#define UARTFCR_RFLV1   0x0000  /* RCVR FIFO interrupt trigger level : 1byte */
#define UARTFCR_RFLV4   0x0040  /* RCVR FIFO interrupt trigger level : 4byte */
#define UARTFCR_RFLV8   0x0080  /* RCVR FIFO interrupt trigger level : 8byte */
#define UARTFCR_RFLV14  0x00C0  /* RCVR FIFO interrupt trigger level : 14byte */

/* bit field of UARTMCR register */
#define UARTMCR_DTR     0x0001  /* data terminal ready */
#define UARTMCR_RTS     0x0002  /* request to send */
#define UARTMCR_LOOP    0x0010  /* loopback */

/* bit field of UARTMSR register */
#define UARTMSR_DCTS    0x0001  /* delta clear to send */
#define UARTMSR_DDSR    0x0002  /* delta data set ready */
#define UARTMSR_TERI    0x0004  /* trailing edge of ring endicator */
#define UARTMSR_DDCD    0x0008  /* delta data carrer detect */
#define UARTMSR_CTS     0x0010  /* clear to send */
#define UARTMSR_DSR     0x0020  /* data set ready */
#define UARTMSR_RI      0x0040  /* ring indicator */
#define UARTMSR_DCD     0x0080  /* data carrer detect */

/* bit field of UARTIIR register */
#define UARTIIR_IP      0x0001  /* interrupt generated */
#define UARTIIR_LINE    0x0006  /* receiver line status interrupt */
#define UARTIIR_RCV     0x0004  /* receiver interrupt */
#define UARTIIR_TO      0x000C  /* time out interrupt */
#define UARTIIR_TRA     0x0002  /* transmitter interrupt */
#define UARTIIR_FM      0x00C0  /* FIFO mode */

/* bit field of UARTIER register */
#define UARTIER_ERBF    0x0001  /* enable received data available interrupt */
#define UARTIER_ETBEF   0x0002  /* enable transmitter holding register empty interrupt */
#define UARTIER_ELSI    0x0004  /* enable receiver line status interrupt */
#define UARTIER_EDSI    0x0008  /* enable modem status interrupt */


/*****************************************************/
/*    PWM control register                           */
/*****************************************************/
#define PWM_BASE    0xB7D00000  /* base address */
#define PWR0        (PWM_BASE+0x00) /* PWM register 0 */
#define PWCY0       (PWM_BASE+0x04) /* PWM cycle register 0 */
#define PWC0        (PWM_BASE+0x08) /* PWM counter 0 */
#define PWCON0      (PWM_BASE+0x0C) /* PWM contrlo register 0 */
#define PWR1        (PWM_BASE+0x20) /* PWM register 1 */
#define PWCY1       (PWM_BASE+0x24) /* PWM cycle register 1 */
#define PWC1        (PWM_BASE+0x28) /* PWM counter 1 */
#define PWCON1      (PWM_BASE+0x2C) /* PWM contrlo register 1 */
#define PWINTSTS    (PWM_BASE+0x3C) /* PWM interrupt status register */

/* bit field of PWCON0,1 register */
#define PWCON_PWR       0x0001  /* enable PWC */
#define PWCON_CLK1      0x0000  /* 1/1 CPUCLK */
#define PWCON_CLK4      0x0002  /* 1/4 CPUCLK */
#define PWCON_CLK16     0x0004  /* 1/16 CPUCLK */
#define PWCON_CLK32     0x0006  /* 1/32 CPUCLK */
#define PWCON_INTIE     0x0040  /* enable interrupt */
#define PWCON_PWCOV     0x0080

/* bit field of PWSTAT  register */
#define PWINTSTS_INT1S    0x0200  /* CH1 interrupt generated */
#define PWINTSTS_INT0S    0x0100  /* CH0 interrupt generated */
#define PWINTSTS_INT1CLR  0x0002  /* CH1 interrupt clear */
#define PWINTSTS_INT0CLR  0x0001  /* CH0 interrupt clear */


/*****************************************************/
/*    port control register                           */
/*****************************************************/
#define PCR_BASE    0xB7A00000  /* base address */
#define GPPOA       (PCR_BASE+0x00) /* port A output register */
#define GPPIA       (PCR_BASE+0x04) /* port A input register */
#define GPPMA       (PCR_BASE+0x08) /* port A Mode register */
#define GPIEA       (PCR_BASE+0x0C) /* port A interrupt enable */
#define GPIPA       (PCR_BASE+0x10) /* port A interrupt Polarity */
#define GPISA       (PCR_BASE+0x14) /* port A interrupt Status */
#define GPPOB       (PCR_BASE+0x20) /* port B Output register */
#define GPPIB       (PCR_BASE+0x24) /* port B Input register */
#define GPPMB       (PCR_BASE+0x28) /* port B Mode register */
#define GPIEB       (PCR_BASE+0x2C) /* port B interrupt enable */
#define GPIPB       (PCR_BASE+0x30) /* port B interrupt Polarity */
#define GPISB       (PCR_BASE+0x34) /* port B interrupt Status */


/*****************************************************/
/*    ADC control register                           */
/*****************************************************/
#define ADC_BASE    0xB6000000  /* base address */
#define ADCON0      (ADC_BASE+0x00) /* ADC control 0 register */
#define ADCON1      (ADC_BASE+0x04) /* ADC control 1 register */
#define ADCON2      (ADC_BASE+0x08) /* ADC control 2 register */
#define ADINT       (ADC_BASE+0x0C) /* AD interrupt control register */
#define ADFINT      (ADC_BASE+0x10) /* AD Forced interrupt register */
#define ADR0        (ADC_BASE+0x14) /* AD Result 0 register */
#define ADR1        (ADC_BASE+0x18) /* AD Result 1 register */
#define ADR2        (ADC_BASE+0x1C) /* AD Result 2 register */
#define ADR3        (ADC_BASE+0x20) /* AD Result 3 register */
#define ADR4        (ADC_BASE+0x24) /* AD Result 4 register */
#define ADR5        (ADC_BASE+0x28) /* AD Result 5 register */
#define ADR6        (ADC_BASE+0x2C) /* AD Result 6 register */
#define ADR7        (ADC_BASE+0x30) /* AD Result 7 register */


/* bit field of ADCON0 register */
#define ADCON0_CH0_7    0x0000  /* CH0-CH7 */
#define ADCON0_CH1_7    0x0001  /* CH1-CH7 */
#define ADCON0_CH2_7    0x0002  /* CH2-CH7 */
#define ADCON0_CH3_7    0x0003  /* CH3-CH7 */
#define ADCON0_CH4_7    0x0004  /* CH4-CH7 */
#define ADCON0_CH5_7    0x0005  /* CH5-CH7 */
#define ADCON0_CH6_7    0x0006  /* CH6-CH7 */
#define ADCON0_CH7      0x0007  /* CH7 */
#define ADCON0_ADRUN    0x0010  /* AD conversion start */
#define ADCON0_SCNC     0x0040  /* Stop after a round */

/* bit field of ADCON1 register */
#define ADCON1_CH0      0x0000  /* CH0 */
#define ADCON1_CH1      0x0001  /* CH1 */
#define ADCON1_CH2      0x0002  /* CH2 */
#define ADCON1_CH3      0x0003  /* CH3 */
#define ADCON1_CH4      0x0004  /* CH4 */
#define ADCON1_CH5      0x0005  /* CH5 */
#define ADCON1_CH6      0x0006  /* CH6 */
#define ADCON1_CH7      0x0007  /* CH7 */
#define ADCON1_STS      0x0010  /* AD conversion start */

/* bit field of ADCON2 register */
#define ADCON2_CLK2     0x0001  /* CPUCLK/2 */
#define ADCON2_CLK4     0x0002  /* CPUCLK/4 */
#define ADCON2_CLK8     0x0003  /* CPUCLK/8 */

/* bit field of ADINT register */
#define ADINT_INTSN     0x0001  /* AD conversion of ch7 finished (scan mode) */
#define ADINT_INTST     0x0002  /* AD conversion finished (select mode) */
#define ADINT_ADSNIE    0x0004  /* enable interrupt (scan mode) */
#define ADINT_ADSTIE    0x0008  /* enable interrupt (select mode) */

/* bit field of ADICNT register */
#define ADICNT_ADFAS    0x0001  /* Assert interrupt signal */


/*****************************************************/
/*    DMA control register                           */
/*****************************************************/
#define DMA_BASE    0x7BE00000  /* base address */
#define DMAMOD      (DMA_BASE+0x0000)   /* DMA Mode register */
#define DMASTA      (DMA_BASE+0x0004)   /* DMA Status register */
#define DMAINT      (DMA_BASE+0x0008)   /* DMA interrupt Status register */
#define DMACMSK0    (DMA_BASE+0x0100)   /* Channel 0 Mask register */
#define DMACTMOD0   (DMA_BASE+0x0104)   /* Channel 0 Transfer Mode register */
#define DMACSAD0    (DMA_BASE+0x0108)   /* Channel 0 Source Address register */
#define DMACDAD0    (DMA_BASE+0x010C)   /* Channel 0 Destination Address register */
#define DMACSIZ0    (DMA_BASE+0x0110)   /* Channel 0 Transfer Size register */
#define DMACCINT0   (DMA_BASE+0x0114)   /* Channel 0 interrupt Clear register */
#define DMACMSK1    (DMA_BASE+0x0200)   /* Channel 1 Mask register */
#define DMACTMOD1   (DMA_BASE+0x0204)   /* Channel 1 Transfer Mode register */
#define DMACSAD1    (DMA_BASE+0x0208)   /* Channel 1 Source Address register */