ml674000.h

一些典型的阿arm嵌入式应用程序集锦！

/**********************************************************************************/
/*                                                                                */
/*    Copyright (C) 2001 Oki Electric Industry Co., LTD.                          */
/*                                                                                */
/*    System Name    :  ML674000                                                  */
/*    Module Name    :  Common definition include file for ML674000               */
/*    File   Name    :  ML674000.h                                                */
/*    Revision       :  01.00                                                     */
/*    Date           :  2001/10/19                                                */
/*                                                                                */
/**********************************************************************************/
#ifndef ML674000_H
#define ML674000_H

#ifdef __cplusplus
extern "C" {
#endif


/*------------------------------ uPLAT-7B core -----------------------------------*/
/*****************************************************/
/*    interrupt control register                     */
/*****************************************************/
#define ICR_BASE    0x78000000      /* base address of interrupt control register */
#define IRQ         (ICR_BASE+0x00) /* IRQ register */
#define IRQS        (ICR_BASE+0x04) /* IRQ soft register */
#define FIQ         (ICR_BASE+0x08) /* FIQ register */
#define FIQRAW      (ICR_BASE+0x0C) /* FIQRAW status register */
#define FIQEN       (ICR_BASE+0x10) /* FIQ enable register */
#define IRN         (ICR_BASE+0x14) /* IRQ number register */
#define CIL         (ICR_BASE+0x18) /* current IRQ level register */
#define IRL         (ICR_BASE+0x1C) /* IRQ level register */
#define ILC0        (ICR_BASE+0x20) /* IRQ level control register 0 */
#define ILC1        (ICR_BASE+0x24) /* IRQ level control register 1 */
#define CILCL       (ICR_BASE+0x28) /* current IRQ level clear register */
#define CILE        (ICR_BASE+0x2C) /* current IRQ level encode register */

/* bit field of IRQ register */
#define IRQ_nIR0    0x00000001  /* nIR[0] */
#define IRQ_nIR1    0x00000002  /* nIR[1] */
#define IRQ_nIR2    0x00000004  /* nIR[2] */
#define IRQ_nIR3    0x00000008  /* nIR[3] */
#define IRQ_nIR4    0x00000010  /* nIR[4] */
#define IRQ_nIR5    0x00000020  /* nIR[5] */
#define IRQ_nIR6    0x00000040  /* nIR[6] */
#define IRQ_nIR7    0x00000080  /* nIR[7] */
#define IRQ_nIR8    0x00000100  /* nIR[8] */
#define IRQ_nIR9    0x00000200  /* nIR[9] */
#define IRQ_nIR10   0x00000400  /* nIR[10] */
#define IRQ_nIR11   0x00000800  /* nIR[11] */
#define IRQ_nIR12   0x00001000  /* nIR[12] */
#define IRQ_nIR13   0x00002000  /* nIR[13] */
#define IRQ_nIR14   0x00004000  /* nIR[14] */
#define IRQ_nIR15   0x00008000  /* nIR[15] */

/* bit field of CIL register */
#define CIL_INT_LV1 0x00000002  /* interrupt level 1 */
#define CIL_INT_LV2 0x00000004  /* interrupt level 2 */
#define CIL_INT_LV3 0x00000008  /* interrupt level 3 */
#define CIL_INT_LV4 0x00000010  /* interrupt level 4 */
#define CIL_INT_LV5 0x00000020  /* interrupt level 5 */
#define CIL_INT_LV6 0x00000040  /* interrupt level 6 */
#define CIL_INT_LV7 0x00000080  /* interrupt level 7 */

/* bit field of ILC0 register */
#define ILC0_INT_LV1    0x11111111  /* interrupt level 1 */
#define ILC0_INT_LV2    0x22222222  /* interrupt level 2 */
#define ILC0_INT_LV3    0x33333333  /* interrupt level 3 */
#define ILC0_INT_LV4    0x44444444  /* interrupt level 4 */
#define ILC0_INT_LV5    0x55555555  /* interrupt level 5 */
#define ILC0_INT_LV6    0x66666666  /* interrupt level 6 */
#define ILC0_INT_LV7    0x77777777  /* interrupt level 7 */
#define ILC0_ILR0       0x00000007  /* nIR[0] */
#define ILC0_ILR1       0x00000070  /* nIR[1],nIR[2],nIR[3] */
#define ILC0_ILR4       0x00070000  /* nIR[4],nIR[5] */
#define ILC0_ILR6       0x07000000  /* nIR[6],nIR[7] */

/* bit field of ILC1 register */
#define ILC1_INT_LV1    0x11111111  /* interrupt level 1 */
#define ILC1_INT_LV2    0x22222222  /* interrupt level 2 */
#define ILC1_INT_LV3    0x33333333  /* interrupt level 3 */
#define ILC1_INT_LV4    0x44444444  /* interrupt level 4 */
#define ILC1_INT_LV5    0x55555555  /* interrupt level 5 */
#define ILC1_INT_LV6    0x66666666  /* interrupt level 6 */
#define ILC1_INT_LV7    0x77777777  /* interrupt level 7 */
#define ILC1_ILR8       0x00000007  /* nIR[8] */
#define ILC1_ILR9       0x00000070  /* nIR[9] */
#define ILC1_ILR10      0x00000700  /* nIR[10] */
#define ILC1_ILR11      0x00007000  /* nIR[11] */
#define ILC1_ILR12      0x00070000  /* nIR[12] */
#define ILC1_ILR13      0x00700000  /* nIR[13] */
#define ILC1_ILR14      0x07000000  /* nIR[14] */
#define ILC1_ILR15      0x70000000  /* nIR[15] */

/* bit field of CILCL register */
#define CILCL_CLEAR     0x01        /* most significant '1' bit of CIL is cleared */

/*****************************************************/
/*    external memory control register               */
/*****************************************************/
#define EMCR_BASE   0x78100000          /* base address */
#define BWC         (EMCR_BASE+0x00)    /* bus width control register */
#define ROMAC       (EMCR_BASE+0x04)    /* external ROM access control register */
#define RAMAC       (EMCR_BASE+0x08)    /* external SRAM access control register */
#define IO0AC       (EMCR_BASE+0x0C)    /* external IO0 access control register */
#define IO1AC       (EMCR_BASE+0x10)    /* external IO1 access control register */

/*****************************************************/
/*    system control register                        */
/*****************************************************/
#define SCR_BASE    0xB8000000      /* base address */
#define IDR         (SCR_BASE+0x00) /* ID register */
#define CKSTP       (SCR_BASE+0x04) /* clock stop register */
#define CGBCNT0     (SCR_BASE+0x08) /* clock(CGB) control register 0 */
#define CKWT        (SCR_BASE+0x0C) /* clock wait register */
#define RMPCON      (SCR_BASE+0x10) /* remap control register */
#define PST         (SCR_BASE+0x14) /* peripheral status register */
#define CGBCNT1     (SCR_BASE+0x18) /* clock(CGB) control register 1 */
#define CGBCNT2     (SCR_BASE+0x1C) /* clock(CGB) control register 2 */

/* bit field of CKSTP register */
#define CKSTP_CPUG  0x04        /* CPU group HALT */
#define CKSTP_TIC   0x02        /* TIC HALT */
#define CKSTP_SIO   0x01        /* SIO HALT */
#define CKSTP_STOP  0xF0        /* clock stop */

/* bit field of CGBCNT0 register */
#define CGBCNT0_CLK1    0x00        /* CPUCLK */
#define CGBCNT0_CLK2    0x01        /* CPUCLK/2 */
#define CGBCNT0_CLK4    0x02        /* CPUCLK/4 */
#define CGBCNT0_CLK8    0x03        /* CPUCLK/8 */

/* bit field of RMPCON register */
#define RMPCON_ENABLE   0x08        /* remap enabled */
#define RMPCON_DISABLE  0x00        /* remap disabled */
#define RMPCON_AHB      0x02        /* device space is AHB bus*/
#define RMPCON_EXT      0x00        /* device space is external bus */
#define RMPCON_DRAM     0x01        /* memory type is DRAM */
#define RMPCON_SRAM     0x00        /* memory type is SRAM */
#define RMPCON_IRAM     0x04        /* memory type is internal RAM */


/*****************************************************/
/*    system timer control register                  */
/*****************************************************/
#define STCR_BASE   0xB8001000          /* base address */
#define TMEN        (STCR_BASE+0x04)    /* timer enable register */
#define TMRLR       (STCR_BASE+0x08)    /* timer reload register */
#define TMOVF       (STCR_BASE+0x10)    /* overflow register */

/* bit field of TMEN register */
#define TMEN_TCEN   0x01        /* timer enabled */

/* bit field of TMOVF register */
#define TMOVF_OVF   0x01        /* overflow generated */


/*****************************************************/
/*    SIO control register                           */
/*****************************************************/
#define SC_BASE     0xB8002000      /* base address */
#define SIOBUF      (SC_BASE+0x00)  /* transmiting/receiving buffer register */
#define SIOSTA      (SC_BASE+0x04)  /* SIO status register */
#define SIOCON      (SC_BASE+0x08)  /* SIO control register */
#define SIOBCN      (SC_BASE+0x0C)  /* baud rate control register */
#define SIOBTC      (SC_BASE+0x10)  /* baud rate timer counter */
#define SIOBT       (SC_BASE+0x14)  /* baud rate timer register */
#define SIOTCN      (SC_BASE+0x18)  /* SIO test control register */

/* bit field of SIOSTA register */
#define SIOSTA_FERR     0x0001      /* framing error */
#define SIOSTA_OERR     0x0002      /* overrun error */
#define SIOSTA_PERR     0x0004      /* parity error */
#define SIOSTA_RVIRQ    0x0010      /* receive ready */
#define SIOSTA_TRIRQ    0x0020      /* transmit ready */

/* bit field of SIOCON register */
#define SIOCON_LN7      0x0001      /* data length : 7bit */
#define SIOCON_LN8      0x0000      /* data length : 8bit */
#define SIOCON_PEN      0x0002      /* parity enabled */
#define SIOCON_PDIS     0x0000      /* parity disabled */
#define SIOCON_EVN      0x0004      /* even parity */
#define SIOCON_ODD      0x0000      /* odd parity */
#define SIOCON_TSTB1    0x0008      /* stop bit : 1 */
#define SIOCON_TSTB2    0x0000      /* stop bit : 2 */

/* bit field of SIOBCN register */
#define SIOBCN_BGRUN    0x0010      /* count start */

/* bit field of SIOTCN register */
#define SIOTCN_MFERR    0x0001      /* generate framin error */
#define SIOTCN_MPERR    0x0002      /* generate parity error */
#define SIOTCN_LBTST    0x0080      /* loop back test */


/*---------------------------------- ML674000 ------------------------------------*/
/*****************************************************/
/*    timer control register                         */
/*****************************************************/
#define TCR_BASE    0xB7F00000  /* base address */
#define TIMECNTL0   (TCR_BASE+0x00) /* timer0 control register */
#define TIMEBASE0   (TCR_BASE+0x04) /* timer0 base register */
#define TIMECNT0    (TCR_BASE+0x08) /* timer0 counter register */
#define TIMECMP0    (TCR_BASE+0x0C) /* timer0 compare register */
#define TIMESTAT0   (TCR_BASE+0x10) /* timer0 status register */
#define TIMECNTL1   (TCR_BASE+0x20) /* timer1 control register */
#define TIMEBASE1   (TCR_BASE+0x24) /* timer1 base register */
#define TIMECNT1    (TCR_BASE+0x28) /* timer1 counter register */
#define TIMECMP1    (TCR_BASE+0x2C) /* timer1 compare register */
#define TIMESTAT1   (TCR_BASE+0x30) /* timer1 status register */
#define TIMECNTL2   (TCR_BASE+0x40) /* timer2 control register */
#define TIMEBASE2   (TCR_BASE+0x44) /* timer2 base register */
#define TIMECNT2    (TCR_BASE+0x48) /* timer2 counter register */
#define TIMECMP2    (TCR_BASE+0x4C) /* timer2 compare register */
#define TIMESTAT2   (TCR_BASE+0x50) /* timer2 status register */
#define TIMECNTL3   (TCR_BASE+0x60) /* timer3 control register */
#define TIMEBASE3   (TCR_BASE+0x64) /* timer3 base register */
#define TIMECNT3    (TCR_BASE+0x68) /* timer3 counter register */
#define TIMECMP3    (TCR_BASE+0x6C) /* timer3 compare register */
#define TIMESTAT3   (TCR_BASE+0x70) /* timer3 status register */
#define TIMECNTL4   (TCR_BASE+0x80) /* timer4 control register */
#define TIMEBASE4   (TCR_BASE+0x84) /* timer4 base register */
#define TIMECNT4    (TCR_BASE+0x88) /* timer4 counter register */
#define TIMECMP4    (TCR_BASE+0x8C) /* timer4 compare register */
#define TIMESTAT4   (TCR_BASE+0x90) /* timer4 status register */
#define TIMECNTL5   (TCR_BASE+0xA0) /* timer5 control register */
#define TIMEBASE5   (TCR_BASE+0xA4) /* timer5 base register */
#define TIMECNT5    (TCR_BASE+0xA8) /* timer5 counter register */
#define TIMECMP5    (TCR_BASE+0xAC) /* timer5 compare register */
#define TIMESTAT5   (TCR_BASE+0xB0) /* timer5 status register */

/* bit field of TIMECNTL0-5 register */
#define TIMECNTL_CLK    0x0000  /* CPUCLK */
#define TIMECNTL_CLK2   0x0020  /* CPUCLK/2 */
#define TIMECNTL_CLK4   0x0040  /* CPUCLK/4 */
#define TIMECNTL_CLK8   0x0060  /* CPUCLK/8 */
#define TIMECNTL_CLK16  0x0080  /* CPUCLK/16 */
#define TIMECNTL_CLK32  0x00A0  /* CPUCLK/32 */
#define TIMECNTL_IE     0x0010  /* enable interrupt */
#define TIMECNTL_START  0x0008  /* timer start */
#define TIMECNTL_OS     0x0001  /* one shot timer */